rvv: trigger exp for illegal ncvt/wcvt eew

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

16 files changed, 26 insertions, 26 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index cdfee77..36a0c66 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -2313,12 +2313,13 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   for (reg_t i=P.VU.vstart; i<vl; ++i){ \
     VI_LOOP_ELEMENT_SKIP();
 
-#define VI_VFP_CVT_SCALE(BODY8, BODY16, BODY32, is_widen) \
+#define VI_VFP_CVT_SCALE(BODY8, BODY16, BODY32, is_widen, eew_check) \
   if (is_widen) { \
     VI_CHECK_DSS(false);\
   } else { \
     VI_CHECK_SDS(false); \
   } \
+  require(eew_check); \
   switch(P.VU.vsew) { \
     case e8: {\
       VI_VFP_LOOP_SCALE_BASE \
diff --git a/riscv/insns/vfncvt_f_f_w.h b/riscv/insns/vfncvt_f_f_w.h
index 5ccdcc3..65af339 100644
--- a/riscv/insns/vfncvt_f_f_w.h
+++ b/riscv/insns/vfncvt_f_f_w.h
@@ -1,7 +1,7 @@
 // vfncvt.f.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
-  require(0);
+  ;
 },
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
@@ -10,5 +10,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
-}, false)
-
+}, false, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfncvt_f_x_w.h b/riscv/insns/vfncvt_f_x_w.h
index 9684899..55163b3 100644
--- a/riscv/insns/vfncvt_f_x_w.h
+++ b/riscv/insns/vfncvt_f_x_w.h
@@ -1,7 +1,7 @@
 // vfncvt.f.x.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
-  require(0);
+  ;
 },
 {
   auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
@@ -10,4 +10,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<int64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = i64_to_f32(vs2);
-}, false)
+}, false, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfncvt_f_xu_w.h b/riscv/insns/vfncvt_f_xu_w.h
index 04b2b2b..686b23f 100644
--- a/riscv/insns/vfncvt_f_xu_w.h
+++ b/riscv/insns/vfncvt_f_xu_w.h
@@ -1,7 +1,7 @@
 // vfncvt.f.xu.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
-  require(0);
+  ;
 },
 {
   auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
@@ -10,4 +10,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<uint64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = ui64_to_f32(vs2);
-}, false)
+}, false, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfncvt_rod_f_f_w.h b/riscv/insns/vfncvt_rod_f_f_w.h
index bb0b851..11d87e0 100644
--- a/riscv/insns/vfncvt_rod_f_f_w.h
+++ b/riscv/insns/vfncvt_rod_f_f_w.h
@@ -1,7 +1,7 @@
 // vfncvt.rod.f.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
-  require(0);
+  ;
 },
 {
   softfloat_roundingMode = softfloat_round_odd;
@@ -12,4 +12,4 @@ VI_VFP_CVT_SCALE
   softfloat_roundingMode = softfloat_round_odd;
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
-}, false)
+}, false, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfncvt_rtz_x_f_w.h b/riscv/insns/vfncvt_rtz_x_f_w.h
index 63a1842..7e4ec3a 100644
--- a/riscv/insns/vfncvt_rtz_x_f_w.h
+++ b/riscv/insns/vfncvt_rtz_x_f_w.h
@@ -11,4 +11,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, softfloat_round_minMag, true);
-}, false)
+}, false, (P.VU.vsew <= 32))
diff --git a/riscv/insns/vfncvt_rtz_xu_f_w.h b/riscv/insns/vfncvt_rtz_xu_f_w.h
index 9316e22..e20ba0e 100644
--- a/riscv/insns/vfncvt_rtz_xu_f_w.h
+++ b/riscv/insns/vfncvt_rtz_xu_f_w.h
@@ -11,4 +11,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, softfloat_round_minMag, true);
-}, false)
+}, false, (P.VU.vsew <= 32))
diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h
index aed35e6..2b1f012 100644
--- a/riscv/insns/vfncvt_x_f_w.h
+++ b/riscv/insns/vfncvt_x_f_w.h
@@ -11,4 +11,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, STATE.frm, true);
-}, false)
+}, false, (P.VU.vsew <= 32))
diff --git a/riscv/insns/vfncvt_xu_f_w.h b/riscv/insns/vfncvt_xu_f_w.h
index c46b620..bad09d8 100644
--- a/riscv/insns/vfncvt_xu_f_w.h
+++ b/riscv/insns/vfncvt_xu_f_w.h
@@ -11,4 +11,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, STATE.frm, true);
-}, false)
+}, false, (P.VU.vsew <= 32))
diff --git a/riscv/insns/vfwcvt_f_f_v.h b/riscv/insns/vfwcvt_f_f_v.h
index 2d418a2..2e92fef 100644
--- a/riscv/insns/vfwcvt_f_f_v.h
+++ b/riscv/insns/vfwcvt_f_f_v.h
@@ -1,7 +1,7 @@
 // vfwcvt.f.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
-  require(0);
+  ;
 },
 {
   auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
@@ -10,4 +10,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = f32_to_f64(vs2);
-}, true)
+}, true, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfwcvt_f_x_v.h b/riscv/insns/vfwcvt_f_x_v.h
index 90978bc..4f0f4f4 100644
--- a/riscv/insns/vfwcvt_f_x_v.h
+++ b/riscv/insns/vfwcvt_f_x_v.h
@@ -11,4 +11,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = i32_to_f64(vs2);
-}, true)
+}, true, (P.VU.vsew >= 8))
diff --git a/riscv/insns/vfwcvt_f_xu_v.h b/riscv/insns/vfwcvt_f_xu_v.h
index 7a9be7d..b9fd0d8 100644
--- a/riscv/insns/vfwcvt_f_xu_v.h
+++ b/riscv/insns/vfwcvt_f_xu_v.h
@@ -11,4 +11,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = ui32_to_f64(vs2);
-}, true)
+}, true, (P.VU.vsew >= 8))
diff --git a/riscv/insns/vfwcvt_rtz_x_f_v.h b/riscv/insns/vfwcvt_rtz_x_f_v.h
index 17946f9..62ecb51 100644
--- a/riscv/insns/vfwcvt_rtz_x_f_v.h
+++ b/riscv/insns/vfwcvt_rtz_x_f_v.h
@@ -1,7 +1,7 @@
 // vfwcvt.rtz.x.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
-  require(0);
+  ;
 },
 {
   auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
@@ -10,4 +10,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, softfloat_round_minMag, true);
-}, true)
+}, true, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfwcvt_rtz_xu_f_v.h b/riscv/insns/vfwcvt_rtz_xu_f_v.h
index 9d5e235..69b70d4 100644
--- a/riscv/insns/vfwcvt_rtz_xu_f_v.h
+++ b/riscv/insns/vfwcvt_rtz_xu_f_v.h
@@ -1,7 +1,7 @@
 // vfwcvt.rtz,xu.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
-  require(0);
+  ;
 },
 {
   auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
@@ -10,4 +10,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, softfloat_round_minMag, true);
-}, true)
+}, true, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfwcvt_x_f_v.h b/riscv/insns/vfwcvt_x_f_v.h
index 879f980..6b266b2 100644
--- a/riscv/insns/vfwcvt_x_f_v.h
+++ b/riscv/insns/vfwcvt_x_f_v.h
@@ -1,7 +1,7 @@
 // vfwcvt.x.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
-  require(0);
+  ;
 },
 {
   auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
@@ -10,4 +10,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, STATE.frm, true);
-}, true)
+}, true, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfwcvt_xu_f_v.h b/riscv/insns/vfwcvt_xu_f_v.h
index 70ce696..2b535a9 100644
--- a/riscv/insns/vfwcvt_xu_f_v.h
+++ b/riscv/insns/vfwcvt_xu_f_v.h
@@ -1,7 +1,7 @@
 // vfwcvt.xu.f.v vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
-  require(0);
+  ;
 },
 {
   auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
@@ -10,4 +10,4 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, STATE.frm, true);
-}, true)
+}, true, (P.VU.vsew >= 16))