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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-27 11:11:46 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-27 11:12:13 -0700 |
| commit | 9cff83b2072bb1b6ad65fac4484bfd3d2deb62c6 (patch) | |
| tree | cbd9adcac5467cd5a40e036e8ad34bf9b32b3dbc | |
| parent | 8f5e8712b637198bff7a58aa3bb74470417809c9 (diff) | |
| download | spike-9cff83b2072bb1b6ad65fac4484bfd3d2deb62c6.zip spike-9cff83b2072bb1b6ad65fac4484bfd3d2deb62c6.tar.gz spike-9cff83b2072bb1b6ad65fac4484bfd3d2deb62c6.tar.bz2 | |
rvv: commitlog: fix comparision dst information
Comparison only writes one vector register
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 11 | ||||
| -rw-r--r-- | riscv/insns/vmsgtu_vi.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vmsleu_vi.h | 2 |
3 files changed, 9 insertions, 6 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 91ce537..bf0d143 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -668,6 +668,9 @@ static inline bool is_overlapped(const int astart, const int asize, type_usew_t<x>::type rs1 = (type_usew_t<x>::type)RS1; \ type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); +#define VI_UCMP_PARAMS(x) \ + type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); + #define VV_CMP_PARAMS(x) \ type_sew_t<x>::type vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \ type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); @@ -827,16 +830,16 @@ static inline bool is_overlapped(const int astart, const int asize, VI_CHECK_MSS(false); \ VI_LOOP_CMP_BASE \ if (sew == e8){ \ - VI_U_PARAMS(e8); \ + VI_UCMP_PARAMS(e8); \ BODY; \ }else if(sew == e16){ \ - VI_U_PARAMS(e16); \ + VI_UCMP_PARAMS(e16); \ BODY; \ }else if(sew == e32){ \ - VI_U_PARAMS(e32); \ + VI_UCMP_PARAMS(e32); \ BODY; \ }else if(sew == e64){ \ - VI_U_PARAMS(e64); \ + VI_UCMP_PARAMS(e64); \ BODY; \ } \ VI_LOOP_CMP_END diff --git a/riscv/insns/vmsgtu_vi.h b/riscv/insns/vmsgtu_vi.h index ee47e50..be28fee 100644 --- a/riscv/insns/vmsgtu_vi.h +++ b/riscv/insns/vmsgtu_vi.h @@ -1,4 +1,4 @@ -// vsgtu.vi vd, vd2, simm5 +// vmsgtu.vi vd, vd2, simm5 VI_VI_ULOOP_CMP ({ res = vs2 > (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); diff --git a/riscv/insns/vmsleu_vi.h b/riscv/insns/vmsleu_vi.h index d11ff6a..0e66b78 100644 --- a/riscv/insns/vmsleu_vi.h +++ b/riscv/insns/vmsleu_vi.h @@ -1,4 +1,4 @@ -// vsleu.vi vd, vs2, simm5 +// vmsleu.vi vd, vs2, simm5 VI_VI_ULOOP_CMP ({ res = vs2 <= (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); |