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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-24 00:17:58 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-24 00:44:58 -0700 |
| commit | 8f5e8712b637198bff7a58aa3bb74470417809c9 (patch) | |
| tree | 86ae7460bd0317f8add76b39d74dc1557f3acacf | |
| parent | 292860aa51eedd480e57b5df1085d30ddd46e375 (diff) | |
| download | spike-8f5e8712b637198bff7a58aa3bb74470417809c9.zip spike-8f5e8712b637198bff7a58aa3bb74470417809c9.tar.gz spike-8f5e8712b637198bff7a58aa3bb74470417809c9.tar.bz2 | |
rvv: commitlog: fix missing informaiton for slide1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/insns/vfslide1down_vf.h | 4 | ||||
| -rw-r--r-- | riscv/insns/vfslide1up_vf.h | 4 | ||||
| -rw-r--r-- | riscv/insns/vslide1down_vx.h | 8 | ||||
| -rw-r--r-- | riscv/insns/vslide1up_vx.h | 8 |
4 files changed, 12 insertions, 12 deletions
diff --git a/riscv/insns/vfslide1down_vf.h b/riscv/insns/vfslide1down_vf.h index cfea20d..b2ae345 100644 --- a/riscv/insns/vfslide1down_vf.h +++ b/riscv/insns/vfslide1down_vf.h @@ -26,10 +26,10 @@ if (i != vl - 1) { P.VU.elt<float16_t>(rd_num, vl - 1) = f16(FRS1); break; case e32: - P.VU.elt<float32_t>(rd_num, vl - 1) = f32(FRS1); + P.VU.elt<float32_t>(rd_num, vl - 1, true) = f32(FRS1); break; case e64: - P.VU.elt<float64_t>(rd_num, vl - 1) = f64(FRS1); + P.VU.elt<float64_t>(rd_num, vl - 1, true) = f64(FRS1); break; } } diff --git a/riscv/insns/vfslide1up_vf.h b/riscv/insns/vfslide1up_vf.h index 8a16ea1..7012fc1 100644 --- a/riscv/insns/vfslide1up_vf.h +++ b/riscv/insns/vfslide1up_vf.h @@ -26,10 +26,10 @@ if (i != 0) { P.VU.elt<float16_t>(rd_num, 0) = f16(FRS1); break; case e32: - P.VU.elt<float32_t>(rd_num, 0) = f32(FRS1); + P.VU.elt<float32_t>(rd_num, 0, true) = f32(FRS1); break; case e64: - P.VU.elt<float64_t>(rd_num, 0) = f64(FRS1); + P.VU.elt<float64_t>(rd_num, 0, true) = f64(FRS1); break; } } diff --git a/riscv/insns/vslide1down_vx.h b/riscv/insns/vslide1down_vx.h index 1fe9d04..e867722 100644 --- a/riscv/insns/vslide1down_vx.h +++ b/riscv/insns/vslide1down_vx.h @@ -28,16 +28,16 @@ if (i != vl - 1) { } else { switch (sew) { case e8: - P.VU.elt<uint8_t>(rd_num, vl - 1) = RS1; + P.VU.elt<uint8_t>(rd_num, vl - 1, true) = RS1; break; case e16: - P.VU.elt<uint16_t>(rd_num, vl - 1) = RS1; + P.VU.elt<uint16_t>(rd_num, vl - 1, true) = RS1; break; case e32: - P.VU.elt<uint32_t>(rd_num, vl - 1) = RS1; + P.VU.elt<uint32_t>(rd_num, vl - 1, true) = RS1; break; default: - P.VU.elt<uint64_t>(rd_num, vl - 1) = RS1; + P.VU.elt<uint64_t>(rd_num, vl - 1, true) = RS1; break; } } diff --git a/riscv/insns/vslide1up_vx.h b/riscv/insns/vslide1up_vx.h index 6f12528..33cb9ed 100644 --- a/riscv/insns/vslide1up_vx.h +++ b/riscv/insns/vslide1up_vx.h @@ -18,13 +18,13 @@ if (i != 0) { } } else { if (sew == e8) { - P.VU.elt<uint8_t>(rd_num, 0) = RS1; + P.VU.elt<uint8_t>(rd_num, 0, true) = RS1; } else if(sew == e16) { - P.VU.elt<uint16_t>(rd_num, 0) = RS1; + P.VU.elt<uint16_t>(rd_num, 0, true) = RS1; } else if(sew == e32) { - P.VU.elt<uint32_t>(rd_num, 0) = RS1; + P.VU.elt<uint32_t>(rd_num, 0, true) = RS1; } else if(sew == e64) { - P.VU.elt<uint64_t>(rd_num, 0) = RS1; + P.VU.elt<uint64_t>(rd_num, 0, true) = RS1; } } VI_LOOP_END |