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3 daysMerge patch series "some serial rx buffer patches"Tom Rini1-11/+12
Rasmus Villemoes <ravi@prevas.dk> says: Some small improvements to the serial rx buffer feature. CI seems happy: https://github.com/u-boot/u-boot/pull/674 Link: https://lore.kernel.org/r/20241003141029.920035-1-ravi@prevas.dk
3 daysserial: embed the rx buffer in struct serial_dev_privRasmus Villemoes1-5/+0
The initialization of upriv->buf doesn't check for a NULL return. But there's actually no point in doing a separate, unconditional malloc() in post_probe; we can just make serial_dev_priv contain the rx buffer itself, and let the (larger) allocation be handled by the driver core when it allocates the ->per_device_auto. The total run-time memory used is mostly the same, we reduce the code size a little, and as a bonus, struct serial_dev_priv does not contain the unused members when !SERIAL_RX_BUFFER. Signed-off-by: Rasmus Villemoes <ravi@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
3 daysserial: add build-time sanity check of CONFIG_SERIAL_RX_BUFFER_SIZERasmus Villemoes1-0/+3
The help text says it must be a power of 2, and the implementation does rely on that. Enforce it. A violation gives a wall of text, but the last few lines should be reasonably obvious: drivers/serial/serial-uclass.c:334:9: note: in expansion of macro ‘BUILD_BUG_ON_NOT_POWER_OF_2’ 334 | BUILD_BUG_ON_NOT_POWER_OF_2(CONFIG_SERIAL_RX_BUFFER_SIZE); Signed-off-by: Rasmus Villemoes <ravi@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
3 daysserial: do not overwrite not-consumed characters in rx bufferRasmus Villemoes1-3/+4
Before the previous patch, pasting a string of length x > CONFIG_SERIAL_RX_BUFFER_SIZE results in getting the last (x%CONFIG_SERIAL_RX_BUFFER_SIZE) characters from that string. With the previous patch, one instead gets the last CONFIG_SERIAL_RX_BUFFER_SIZE characters repeatedly until the ->rd_ptr catches up. Both behaviours are counter-intuitive, and happen because the code that checks for a character available from the hardware does not account for whether there is actually room in the software buffer to receive it. Fix that by adding such accounting. This also brings the software buffering more in line with how most hardware FIFOs behave (first received characters are kept, overflowing characters are dropped). Signed-off-by: Rasmus Villemoes <ravi@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
3 daysserial: fix circular rx buffer edge caseRasmus Villemoes1-4/+6
The current implementation of the circular rx buffer falls into a common trap with circular buffers: It keeps the head/tail indices reduced modulo the buffer size. The problem with that is that it makes it impossible to distinguish "buffer full" from "buffer empty", because in both situations one has head==tail. This can easily be demonstrated: Build sandbox with RX_BUFFER enabled, set the RX_BUFFER_SIZE to 32, and try pasting the string 01234567890123456789012345678901 Nothing seems to happen, but in reality, all characters have been read and put into the buffer, but then tstc ends up believing nothing is in the buffer anyway because upriv->rd_ptr == upriv->wr_ptr. A better approach is to let the indices be free-running, and only reduce them modulo the buffer size when accessing the array. Then "empty" is head-tail==0 and "full" is head-tail==size. This does rely on the buffer size being a power-of-two and the free-running indices simply wrapping around to 0 when incremented beyond the maximal positive value. Incidentally, that change from signed to unsigned int also improves code generation quite a bit: In C, (signed int)%(signed int) is defined to have the sign of the dividend (so (-35) % 32 is -3, not 29), and hence despite the modulus being a power-of-two, x % 32 does not actually compile to the same as a simple x & 31 - on x86 with -Os, it seems that gcc ends up emitting an idiv instruction, which is quite expensive. Signed-off-by: Rasmus Villemoes <ravi@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
8 daysMerge patch series "Tidy up use of 'SPL' and CONFIG_SPL_BUILD"Tom Rini7-12/+12
Simon Glass <sjg@chromium.org> says: When the SPL build-phase was first created it was designed to solve a particular problem (the need to init SDRAM so that U-Boot proper could be loaded). It has since expanded to become an important part of U-Boot, with three phases now present: TPL, VPL and SPL Due to this history, the term 'SPL' is used to mean both a particular phase (the one before U-Boot proper) and all the non-proper phases. This has become confusing. For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL' phases, not just SPL. So code which can only be compiled for actual SPL, for example, must use something like this: #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) In Makefiles we have similar issues. SPL_ has been used as a variable which expands to either SPL_ or nothing, to chose between options like CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was updated to support 'VPL_' as well. This series starts a change in terminology and usage to resolve the above issues: - The word 'xPL' is used instead of 'SPL' to mean a non-proper build - A new CONFIG_XPL_BUILD define indicates that the current build is an 'xPL' build - The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now defined for TPL and VPL phases - The existing SPL_ Makefile variable is renamed to SPL_ - The existing SPL_TPL Makefile variable is renamed to PHASE_ It should be noted that xpl_phase() can generally be used instead of the above CONFIGs without a code-space or run-time penalty. This series does not attempt to convert all of U-Boot to use this new terminology but it makes a start. In particular, renaming spl.h and common/spl seems like a bridge too far at this point. The series is fully bisectable. It has also been checked to ensure there are no code-size changes on any commit.
8 daysglobal: Rename SPL_TPL_ to PHASE_Simon Glass1-1/+1
Use PHASE_ as the symbol to select a particular XPL build. This means that SPL_TPL_ is no-longer set. Update the comment in bootstage to refer to this symbol, instead of SPL_ Signed-off-by: Simon Glass <sjg@chromium.org>
8 daysglobal: Rename SPL_ to XPL_Simon Glass1-1/+1
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is no-longer set. Signed-off-by: Simon Glass <sjg@chromium.org>
8 daysdrivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass7-8/+8
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
8 daysxpl: Rename spl_in_proper() to not_xpl()Simon Glass1-2/+2
Give this function a slightly easier name. Signed-off-by: Simon Glass <sjg@chromium.org>
12 daysserial: ns16550: Try get serial clock rate from DT before CLKJonas Karlman1-12/+12
Initializing a clock driver to read a known static clock rate can take some time at U-Boot proper pre-reloc phase. Change to first try and read clock rate from DT to speed up boot time, fall back to getting the clock rate from clock driver. This help reduce boot time by around: - ~35ms on a Radxa ROCK Pi 4 (RK3399) - ~15ms on a Radxa ZERO 3W (RK3566) Time that is wasted getting a static rate known at compile time. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-10-03serial: Support debug UART in TPLSimon Glass1-0/+7
Some boards want to use the debug UART in TPL so add an option for that. Signed-off-by: Simon Glass <sjg@chromium.org>
2024-07-31sandbox: Drop video-sync in serial driverSimon Glass1-2/+0
With sandbox, when U-Boot is waiting for input it syncs the video display, since presumably the user has finished typing. Now that cyclic is used for video syncing, we can drop this. Cyclic will automatically call the video_idle() function when idle. Signed-off-by: Simon Glass <sjg@chromium.org>
2024-07-23arm: ti: Remove omap4 platform supportTom Rini1-2/+1
There are no longer any OMAP4 platforms in U-Boot, remove the related functionality. Signed-off-by: Tom Rini <trini@konsulko.com>
2024-07-22drivers: serial: Remove duplicate newlinesMarek Vasut6-14/+0
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-07-08Merge patch series "mediatek: cumulative trivial fix for OF_UPSTREAM support"Tom Rini1-1/+19
Christian Marangi <ansuelsmth@gmail.com> says: This is an initial series that have all the initial trivial fixes required for usage of OF_UPSTREAM for the mediatek SoC This also contains the pcie-gen3 driver and the required tphy support driver to make it work. Subsequent series will follow with conversion of the mtk-clk to permit usage of OF_UPSTREAM and upstream clk ID. MT7981, MT7986 and MT7988 migration to upstream clock ID is complete and working on MT7623. Series CI tested with PR: https://github.com/u-boot/u-boot/pull/590
2024-07-08serial: mediatek: add special handling for highspeed and linux compatChristian Marangi1-1/+11
Upstream linux serial driver use a different logic to setup serial regs. They have 2 interval: - < 115200 we use lowspeed regs and 16 * baud - >= 115200 we use highspeed We currently use force_highspeed property to force usage of highspeed regs even with low baud rate. Add special handling if the upstream compatible is used where we just apply the same interval with anything >= 115200 in highspeed simulating force_highspeed. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-07-08serial: mediatek: add support for bus clock and enable itChristian Marangi1-0/+8
Upstream linux also provide the additional optional bus clock. Add support for it and also enable the baud and bus clock on probe. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-07-04Merge patch series "xtensa: Enable qemu-xtensa board"Tom Rini3-1/+110
Jiaxun Yang <jiaxun.yang@flygoat.com> says: Hi all, This series enabled qemu-xtensa board. For dc232b CPU it needs to be built with toolchain[1]. This is a side product of me investigating architectures physical address != virtual address in U-Boot. Now we can get it covered under CI and regular tests. VirtIO devices are not working as expected, due to U-Boot's assumption on VA == PA everywhere, I'm going to get this fixed later. My Xtensa knowledge is pretty limited, Xtensa people please feel free to point out if I got anything wrong. Thanks [1]: https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc232b-elf.tar.gz
2024-07-04drivers: serial: Add xtensa semihosting driverJiaxun Yang3-1/+110
Add xtensa semihosting driver. It can't use regular semihosting driver as Xtensa's has it's own semihosting ABI. Tested-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-16serial: ns16550: fix comment to mention schedule instead of watchdog_resetRasmus Villemoes1-4/+4
watchdog_reset() is no more. Make the comments match the code and today's reality. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"WIP/20May2024-nextTom Rini48-46/+232
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini48-232/+46
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07Merge patch series "arm: Add Analog Devices SC5xx Machine Type"WIP/07May2024-nextTom Rini2-0/+226
Greg Malysa <greg.malysa@timesys.com> says: This series adds support for the ADI SC5xx machine type and includes two core drivers that are required for being able to boot any board--a UART driver, the gptimer driver which is used as a clock reference (CNTVCNT is not supported on the armv7 sc5xx SoCs) and the clock tree driver. Our corresponding Linux support relies on u-boot configuring the clocks correctly before booting, so it is not possible to boot any board without the CGU/CDU configuration happening here. There are also no board files, device trees, or defconfigs included here, but some common definitions that will be used to build board files currently are. The sc5xx SoCs themselves include many armv7 families (sc57x, sc58x, and sc594) all using an ARM Cortex-A5, and one armv8 family (sc598) indended to be a drop-in replacement for the SC594 in terms of peripherals, with a Cortex-A55 instead. Some of the configuration code in dmcinit and clkinit is quite scary and causes a lot of checkpatch violations. It is modified from code initially provided by ADI, but it has not been fully rewritten. There's a question of how important it is to clean up this code--it has some quality violations, but it has been in use (including in production) for over two years and is known to work for performing the low level SoC initialization, while a rewrite might introduce timing or sequence bugs that could take a significant amount of time to detect in the future.
2024-05-07drivers: serial: Add in UART for ADI SC5XX-family processorsNathan Barrett-Morrison2-0/+226
Co-developed-by: Greg Malysa <greg.malysa@timesys.com> Signed-off-by: Greg Malysa <greg.malysa@timesys.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
2024-05-07serial: Remove <common.h> and add needed includesTom Rini46-46/+6
Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-23serial_msm: Enable RS232 flow controlSumit Garg1-4/+6
SE HMIBSC board debug console requires RS232 flow control, so enable corresponding support if RS232 gpios are present. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23apq8016: Add support for UART1 clocks and pinmuxSumit Garg1-3/+8
SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks and pinmux support. Along with that update instructions to enable clocks for debug UART support. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial: msm: calculate bit clock dividerCaleb Connolly1-17/+70
The driver currently requires the bit clock divider be hardcoded in devicetree (or use the hardcoded default from apq8016). The bit clock divider is used to derive the baud rate from the core clock: baudrate = clk_rate / csr_div clk_rate is the actual programmed core clock rate which is returned by clk_set_rate(), and this UART driver only supports a baudrate of 115200. We can therefore determine the appropriate value for UARTDM_CSR by iterating over the possible values and finding the one where the equation above holds true for a baudrate of 115200. Implement this logic and drop the non-standard DT bindings for this driver. Tested on dragonboard410c. Tested-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial: msm_serial: remove .clk_rate from debug UARTRobert Marko1-1/+0
MSM serial in DEBUG UART mode is trying to set .clk_rate, but the msm_serial_data structure does not have such property at all, so lets remove it as otherwise it will fail compiling. Fixes: 90023bdfe979 ("serial: msm: add debug UART") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial: allow selecting MSM debug UART with ARCH_IPQ40XXRobert Marko1-1/+1
Currently, DEBUG_UART_MSM depends on ARCH_SNAPDRAGON only, but IPQ40XX devices also use the same UART HW so they can also use the debug UART. So, allow selecting DEBUG_UART_MSM when using ARCH_IPQ40XX as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-15serial: lpuart: use ipg clk for i.MX7ULPPeng Fan1-16/+26
To i.MX7ULP compatible lpuart, there is only ipg clk, no per clk. So add a devtype check for i.MX7ULP. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-04-10Merge tag 'xilinx-for-v2024.07-rc1' of ↵Tom Rini1-1/+1
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2024.07-rc1 xilinx: - Do not call env_get_location when !ENV_IS_NOWHERE - Add FDT_FIXUP_PARTITIONS support - Fix legacy format MAC decoding zynqmp: - Enable semihosting SPL support - DT updates - Kconfig resort/cleanup - Don't describe second image/capsule if !SPL - Add support for dfu/capsule description via MTD - Support JTAG as alternative boot mode - Add support for TEG soc variant zynqmp-kria: - Wire usb4 boot device - Update SDIO tristate pin configuration - Disable SPI_FLASH_BAR to avoid issue with SPI after update mbv: - Enable SPL and binman - Small platform changes zynqmp-nand: - Error out in case of unsupported SW ECC - Clean error path versal-net: - Support multiple locations for variables
2024-04-04serial: msm-geni: support livetreeCaleb Connolly1-0/+13
When using OF_LIVE, the debug UART driver won't be probed if it's a subnode of the geni-se-qup controller. Add a NOP driver for the controller to correctly discover its child nodes. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-04mach-snapdragon: disable power-domains for pre-reloc driversCaleb Connolly1-1/+1
Some devices like the UART and clock controller reference an RPM(h) power domain. We don't support this device in U-Boot, so add DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the power domain. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-03-19Merge tag 'u-boot-socfpga-next-20240319' of ↵WIP/19Mar2024-nextTom Rini1-1/+1
https://source.denx.de/u-boot/custodians/u-boot-socfpga into next - A new driver in the misc to register setting from device tree. This also provides user a clean interface and all register settings are centralized in one place, device tree. - Enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Build-tested on SoC64 boards, boot tested on some of them.
2024-03-12serial: move sbi_dbcn_available to .data sectionHeinrich Schuchardt1-1/+1
U-Boot SPL loads the device-tree directly behind main U-Boot overlapping the .bss section. reserve_fdt() is called in board_init_f() to relocate the device-tree to a safe location. Debug UARTs are enabled before board_init_f(). With sbi_dbcn_available in the .bss section the device-tree is corrupted when _debug_uart_init() is called in the SBI serial driver. Move the variable to the .data section. Link: https://bugs.launchpad.net/ubuntu/+source/u-boot/+bug/2054091 Fixes: dfe08374943c ("risc-v: implement DBCN based debug console") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-11Merge tag 'v2024.04-rc4' into nextTom Rini1-2/+2
Prepare v2024.04-rc4
2024-03-07serial: pl01x: set baudrate when probingYang Xiwen1-3/+8
It is found that when DM is enabled, only generic init function is called in .probe(). Baudrate is never honored. Add a function call to .setbrg() when probing so that we can update the baudrate of the serial device. Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2024-03-02ARM: renesas: Rename ARCH_RMOBILE to ARCH_RENESASMarek Vasut1-2/+2
Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made by Renesas, while only a subset of them is from the R-Mobile line. Use the following command to perform the rename: " $ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {} " Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-01serial: msm: fix clock handling and pinctrlCaleb Connolly1-20/+5
Use the modern helpers to fetch the clock and use the correct property ("clocks" instead of "clock"). Drop the call to pinctrl_select_state() as no boards have a "uart" pinctrl state and this prints confusing errors. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-03-01serial: msm: add debug UARTCaleb Connolly2-0/+45
Introduce support for early debugging. This relies on the previous stage bootloader to initialise the UART clocks, when running with U-Boot as the primary bootloader this feature doesn't work. It will require a way to configure the clocks before the driver model is available. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-03-01riscv: mbv: Moving little_endian variable to data sectionMichal Simek1-1/+1
SPL is cleaning bss after calling board_init_f. Setting up console is done and little_endian global variable is cleared which caused that console stops to work. That's why move it to data seciton now. The patch should be reverted when bss is cleared before board_init_f is called. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/934dc8871c59265eb9d8012193aa97d9b8bd7f33.1707911544.git.michal.simek@amd.com
2024-02-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsungTom Rini1-0/+1
2024-01-29treewide: Remove clk_freeSean Anderson4-5/+0
This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
2024-01-24serial: s5p: Add Exynos850 compatibleSam Protsenko1-0/+1
Enable serial support for Exynos850 SoC by adding the corresponding compatible string. No additional changes needed, the driver works as is on Exynos850. Related USI and PMU configuration is enabled in separate drivers. The only other dependencies are clock and pinctrl drivers, which are already enabled too. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-16serial: msm-geni: handle devm_clk_get() errorsCaleb Connolly1-3/+8
devm_clk_get() returns an ERR_PTR on failure, not null. Fix the check to avoid the board crashing when the clock isn't available. Additionally, add the missing error handling for this function. Fixes: 324df15a292e ("serial: qcom: add support for GENI serial driver") Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16serial: msm-geni: don't rely on parent misc deviceCaleb Connolly2-12/+17
commit 1b15483deb3f ("misc: add Qualcomm GENI SE QUP device driver") introduced support for platform-specific oversampling values, necessary to configure the UART clocks on all platforms at runtime. However it relies in probing a parent device. Despite the DM_FLAG_PRE_RELOC flag, this is not done consistently during boot. Instead, take another approach by relying on ofnode_ helpers to read the serial engine base address and do the read directly. This fixes early UART on boards with a non-default oversampling rate. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2023-12-04Merge tag 'v2024.01-rc4' into nextTom Rini1-36/+43
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2023-11-27serial: s5p: Use dev_read_addr_ptr() to get base addressSam Protsenko1-4/+2
As the address read from device tree is being cast to a pointer, it's better to use dev_read_addr_ptr() API for getting that address. The more detailed explanation can be found in commit a12a73b66476 ("drivers: use dev_read_addr_ptr when cast to pointer"). Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-10-19 22:46:52 +0000