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path: root/drivers/mtd/nand
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9 daysdrivers: mtd: Remove duplicate newlinesMarek Vasut15-24/+0
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-06-24Merge tag 'v2024.07-rc5' into nextTom Rini2-0/+175
Prepare v2024.07-rc5
2024-06-17mtd: nand: pxa3xx: Incorrect bitflip return on page readRavi Minnikanti1-0/+5
Once a page is read with higher bitflips all subsequent reads are returning the same bitflip value even though they have none. max_bitflip variable is not being reset to 0 across page reads. This is causing problems like incorrectly marking erase blocks bad by UBI and causing read failures. Verified the change with both MTD reads and UBI. This change is inline with other NFC drivers. Sample error log where a block is marked bad incorrectly: ubi0: fixable bit-flip detected at PEB 125 ubi0: run torture test for PEB 125 ubi0: fixable bit-flip detected at PEB 125 ubi0 error: torture_peb: read problems on freshly erased PEB 125, must be bad ubi0 error: erase_worker: failed to erase PEB 125, error -5 ubi0: mark PEB 125 as bad Link: https://lore.kernel.org/all/ea0422cd-a8e6-3c36-f551-a0142893301b@marvell.com Signed-off-by: rminnikanti <rminnikanti@marvell.com> Reviewed-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: rminnikanti <rminnikanti@marvell.com> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-06-17mtd: rawnand: macronix: OTP access for MX30LFxG18ACArseniy Krasnov1-0/+170
Support for OTP area access on MX30LFxG18AC chip series. Link: https://lore.kernel.org/all/20231130112405.92196-1-avkrasnov@salutedevices.com Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"WIP/20May2024-nextTom Rini52-52/+18
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini52-18/+52
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07mtd: Remove <common.h> and add needed includesTom Rini52-52/+18
Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-22Merge patch series "Kconfig: some cleanups"Tom Rini1-1/+1
Michal Simek <michal.simek@amd.com> says: I looked as cleaning up some dependencies and I found that qconfig is reporting some issues. This series is fixing some of them. But there are still some other pending. That's why please go and fix them if they are related to your board. UTF-8: I am using uni2ascii -B < file to do conversion. When you run it in a loop you will find some other issue with copyright chars or some issues in files taken from the Linux kernel like DTs. They should be likely fixed in the kernel first. Based on discussion I am ignoring names too.
2024-04-22common: Convert *.c/h from UTF-8 to ASCII enconfingMichal Simek1-1/+1
Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
2024-04-19mtd: rawnand: stm32_fmc2: add MP25 supportChristophe Kerello1-7/+40
FMC2 IP supports up to 4 chip select. On MP1 SoC, only 2 of them are available when on MP25 SoC, the 4 chip select are available. Let's use a platform data structure for parameters that will differ. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-04-14Merge tag 'u-boot-nand-20240414' of ↵Tom Rini8-60/+1582
https://source.denx.de/u-boot/custodians/u-boot-nand-flash The first patch is by Weizhao Ouyang and avoids sf probe crashes. The second patch is by Arseniy Krasnov and adds basic support for Amlogic Meson NAND controller on AXG. The following four patches are by Alexander Dahl and apply some fixes to drivers/mtd/nand/raw/ and port some changes applied in Linux. The following patch is by Bruce Suen and adds support for XTX SPINAND. Finally, the last patch is again by Arseniy Krasnov and adds access to OTP region, supporting info, dump, write and lock operations.
2024-04-14mtd: spinand: Add support for XTX SPINANDBruce Suen3-1/+268
Add support for XTX XT26G0xA and XT26xxxD. The driver is ported from linux-6.7.1. This driver is tested on Banana BPI-R3 with XT26G01A and XT26G12D. Link: https://lore.kernel.org/all/20240312014314.15454-1-bruce_suen@163.com Signed-off-by: Bruce Suen <bruce_suen@163.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-04-14mtd: nand: raw: atmel: Fix comment in timings preparationAlexander Dahl1-1/+1
Introduced with commit 6a8dfd57220d ("nand: atmel: Add DM based NAND driver") when driver was initially ported from Linux. The context around this and especially the code itself suggests 'read' is meant instead of write. The fix is the same as accepted in Linux already with mainline Linux kernel commit 1c60e027ffde ("mtd: nand: raw: atmel: Fix comment in timings preparation"). Link: https://lore.kernel.org/all/20240320090214.40465-6-ada@thorsis.com Link: https://lore.kernel.org/linux-mtd/20240307172835.3453880-1-miquel.raynal@bootlin.com/T/#t Signed-off-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-04-14mtd: nand: raw: Fix (most) Kconfig indentationAlexander Dahl1-53/+53
One tab in general. One tab plus two spaces for help text. Link: https://lore.kernel.org/all/20240320090214.40465-4-ada@thorsis.com Signed-off-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-04-14mtd: nand: raw: Port another option flag from LinuxAlexander Dahl1-2/+0
Introduced in upstream Linux with commit 7a08dbaedd365 for release v5.0. When the new atmel nand driver was backported to U-Boot with commit 6a8dfd57220d ("nand: atmel: Add DM based NAND driver") that definition was added to the driver instead of the header file. Move it over to the other definitions with the same help text it has in Linux. Code actually using this has not been ported over to raw nand base yet. Link: https://lore.kernel.org/all/20240320090214.40465-3-ada@thorsis.com Signed-off-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-04-14mtd: nand: raw: Use macro nand_to_mtd() where appropriateAlexander Dahl1-3/+3
In every other place in this file the macro is used, make it consistent. Link: https://lore.kernel.org/all/20240320090214.40465-2-ada@thorsis.com Fixes: 9d1806fadc24 ("mtd: nand: Get rid of mtd variable in function calls") Signed-off-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-04-14mtd: rawnand: Meson NAND controller supportArseniy Krasnov3-0/+1258
Basic support for Amlogic Meson NAND controller on AXG. This version works at only first EDO mode. Based on Linux version 6.7.0-rc4. Link: https://lore.kernel.org/all/20240210223927.570043-1-avkrasnov@salutedevices.com Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-03-12mtd: nand: arasan: Fix the crash caused by use after freeVenkatesh Yadav Abbarapu1-13/+14
The below exception observed on QEMU, as it doesn't support NAND controller. "Synchronous Abort" handler, esr 0x96000005, far 0x17acfc878 elr: 000000000803ad40 lr : 000000000805f438 (reloc) elr: 000000007fcb4d40 lr : 000000007fcd9438 x0 : 000000007bbfc880 x1 : 00000000ff100000 x2 : 000000007fcf059c x3 : 000000007bbfc870 x4 : 000000007fd9a388 x5 : 000000017acfc870 x6 : 0000000000000000 x7 : 000000007bbfd0e0 x8 : 0000000000003dd4 x9 : 000000007bbeec0c x10: 0000000000000001 x11: 0000000000003f8c x12: 000000007bbeecfc x13: 000000007bbeeeb0 x14: 000000007bbeeeb0 x15: 000000007bbee474 x16: 000000007fcef18c x17: 0000000000000000 x18: 000000007bbf9d70 x19: 000000007bbfc888 x20: 000000007bbfc870 x21: 000000007fd68ddb x22: 00000000ffffffed x23: 000000007bbfc878 x24: 0000000000000000 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 000000007bbeed10 Code: 927ff8c1 924000c6 8b010065 f9400887 (f94004a2) Resetting CPU ... The crash is caused by the use after free. Updating the correct return codes rather than hardcoding. Fixes: 3dd0f8cccd6d ("mtd: nand: Remove hardcoded base address of nand") Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20240306033404.18537-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-03-12mtd: nand: arasan: Print warning for unsupported ecc modesVenkatesh Yadav Abbarapu1-0/+7
Currently only hw ecc is supported in U-Boot. If any other ecc mode is given in DT, it simply through an error. So better print what is being done. Revert this patch once soft ecc support is fixed in future. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20240306032703.17508-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-31Merge tag 'u-boot-at91-2024.04-a' of ↵Tom Rini1-3/+0
https://source.denx.de/u-boot/custodians/u-boot-at91 First set of u-boot-at91 features for the 2024.04 cycle: This set includes some DT alignments and solves a compile issue for custom nand defconfigs.
2024-01-29treewide: Remove clk_freeSean Anderson1-3/+1
This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
2024-01-22mtd: nand: raw: atmel: Remove duplicate definitionsAlexander Dahl1-3/+0
These removed definitions were specific to some sam9 SoCs, but not generic over all at91 SoCs. The correct SoC specific definitions for ATMEL_BASE_PMECC are spread over different header files in arch/arm/mach-at91/include/mach directory. Fixes a build error on a custon board based on SAMA5D2: Building current source for 73 boards (16 threads, 1 job per thread) arm: + vera2 +drivers/mtd/nand/raw/atmel/pmecc.c:819: warning: "ATMEL_BASE_PMECC" redefined + 819 | #define ATMEL_BASE_PMECC 0xffffe000 + | +In file included from include/configs/vera2.h:11, + from include/config.h:3, + from include/linux/mtd/rawnand.h:16, + from drivers/mtd/nand/raw/atmel/pmecc.c:44: +include/asm/arch/sama5d2.h:171: note: this is the location of the previous definition + 171 | #define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70) +drivers/mtd/nand/raw/atmel/pmecc.c:820: warning: "ATMEL_BASE_PMERRLOC" redefined + 820 | #define ATMEL_BASE_PMERRLOC 0xffffe600 +include/asm/arch/sama5d2.h:172: note: this is the location of the previous definition + 172 | #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500) Fixes: a490e1b7c017 ("nand: atmel: Add pmecc driver") Signed-off-by: Alexander Dahl <ada@thorsis.com>
2024-01-15mtd: rawnand: omap_gpmc: fix OF based partition parsing for NANDRoger Quadros1-0/+2
Set NAND chip ofnode and device so OF based partition parsing can work. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://www.mail-archive.com/u-boot@lists.denx.de/msg499178.html Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15mtd: rawnand: omap_gpmc: Use DT provided IO addressRoger Quadros1-5/+14
For DM case we can get the NAND chip's IO address from DT so we don't need to rely on CFG_SYS_NAND_BASE. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://www.mail-archive.com/u-boot@lists.denx.de/msg499177.html Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15mtd: rawnand: omap_elm: Fix elm_init definitionRoger Quadros2-8/+2
The macro ELM_BASE is defined in mach/hardware.h and is not visible at the omap_elm.h header file. Avoid using it in omap_elm.h. Reported-by: Hong Guan <hguan@ti.com> Fixes: 7363cf0581a3 ("mtd: rawnand: omap_elm: u-boot driver model support") Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/all/20231211114600.4414-3-rogerq@kernel.org Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15mtd: nand: omap_gpmc: Fix NAND in SPL for AM335xRoger Quadros1-66/+29
AM335x uses a special driver "am335x_spl_bch.c" as SPL NAND loader. This driver expects 1 sector at a time ECC and doesn't work well with multi-sector ECC that was implemented in commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction") Additionally, the omap_elm driver does not support multi sector ECC and will need more work and tests to get multi sector working correctly on all platforms. Switch back to 1 sector at a time read/ECC. Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction") Signed-off-by: Roger Quadros <rogerq@kernel.org> Tested-by: Enrico Leto <enrico.leto@siemens.com> Tested-by: Heiko Schocher <hs@denx.de> Link: https://lore.kernel.org/all/20231211114600.4414-2-rogerq@kernel.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15mtd: nand: check nand_mtd_to_devnum() argumentDario Binacchi1-1/+4
If the "mtd" parameter is NULL, the search will definitely yield a negative result. In that case, it's better to exit immediately. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20231102113829.58852-1-dario.binacchi@amarulasolutions.com
2024-01-15mtd: nand: complete nand_register() arguments checkDario Binacchi1-1/+1
The patch checks that the "mtd" parameter is accessible before proceeding. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20231102112743.57420-1-dario.binacchi@amarulasolutions.com
2023-12-18Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi ↵Tom Rini3-1/+140
into next - spi_nor_read_sfdp_dma_unsafe (Vaishnav) - w25q01/02 (Jim)
2023-12-14mtd: spinand: add support for ESMT F50x1G41LBIgor Prusov3-1/+140
Adaptation of Linux commit d74c36480a67 This patch adds support for ESMT F50L1G41LB and F50D1G41LB. It seems that ESMT likes to use random JEDEC ID from other vendors. Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from Micron. For this reason, the ESMT entry is named esmt_c8 with explicit JEDEC ID in variable name. Datasheets: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Tested-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-11-28Merge patch series "Import "string" I/O functions from Linux"Tom Rini2-67/+0
To quote the author: This series imports generic versions of ioread_rep/iowrite_rep and reads/writes from Linux. Some cleanup is done to make sure that all platforms have proper defines for implemented functions and there are no redefinitions.
2023-11-28asm-generic: Import functions from LinuxIgor Prusov2-67/+0
Currently {read,write}s{b,w,lq}() functions are available only on some architectures, and there are no io{read,write}{8,16,32,64}_rep() functions in u-boot. This patch adds generic versions that may be used without arch-specific implementation. Since some of added functions were already added locally in some files, remove them to avoid redeclaration errors. Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-17Merge branch '2023-11-16-assorted-updates' into nextTom Rini4-8/+5
- squashfs improvements, remove common.h in some places, assorted code fixes, fix a few CONFIG symbol names in Kconfig files, bring in linux's <linux/time.h> conversion functions, poplar updates, bcb improvements.
2023-11-16treewide: use linux/time.h for time conversion definesIgor Prusov4-8/+5
Now that we have time conversion defines from in time.h there is no need for each driver to define their own version. Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> #at91 Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom geni Reviewed-by: Stefan Bosch <stefan_b@posteo.net> #nanopi2 Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-11-16test: spl: Add a test for NANDSean Anderson2-1/+33
Add a SPL test for the NAND load method. We use some different functions to do the writing from the main test since things like nand_write_skip_bad aren't available in SPL. We disable BBT scanning, since scan_bbt is only populated when not in SPL. We use nand_spl_loaders.c as it seems to be common to at least a few boards already. However, we do not use nand_spl_simple.c because it would require us to implement cmd_ctrl. The various nand load functions are adapted from omap_gpmc. However, they have been modified for simplicity/correctness. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16nand: Add sandbox driverSean Anderson3-0/+693
Add a sandbox NAND flash driver to facilitate testing. This driver supports any number of devices, each using a single chip-select. The OOB data is stored in-band, with the separation enforced through the API. For now, create two devices to test with. The first is a very small device with basic ECC. The second is an 8G device (chosen to be larger than 32 bits). It uses ONFI, with the values copied from the datasheet. It also doesn't need too strong ECC, which speeds things up. Although the nand subsystem determines the parameters of a chip based on the ID, the driver itself requires devicetree properties for each parameter. We do not derive parameters from the ID because parsing the ID is non-trivial. We do not just use the parameters that the nand subsystem has calculated since that is something we should be testing. An exception is made for the ECC layout, since that is difficult to encode in the device tree and is not a property of the device itself. Despite using file I/O to access the backing data, we do not support using external files. In my experience, these are unnecessary for testing since tests can generally be written to write their expected data beforehand. Additionally, we would need to store the "programmed" information somewhere (complicating the format and the programming process) or try to detect whether block are erased at runtime (degrading probe speeds). Information about whether each page has been programmed is stored in an in-memory buffer. To simplify the implementation, we only support a single program per erase. While this is accurate for many larger flashes, some smaller flashes (512 byte) support multiple programs and/or subpage programs. Support for this could be added later as I believe some filesystems expect this. To test ECC, we support error-injection. Surprisingly, only ECC bytes in the OOB area are protected, even though all bytes are equally susceptible to error. Because of this, we take care to only corrupt ECC bytes. Similarly, because ECC covers "steps" and not the whole page, we must take care to corrupt data in the same way. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16nand: Allow reinitializationSean Anderson1-7/+33
NAND devices are destroyed in between unit tests. Provide a function to reinitialize the subsystem at the beginning of each test. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-11-16nand: Add function to unregister NAND devicesSean Anderson1-0/+17
This performs the opposite of nand_register, allowing drivers to unregister nand devices. This is probably unnecessary for most regular drivers, but we expect sandbox drivers to get repeatedly bound/unbound, so this will help avoid dangling pointers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-11-16mtd: Add some fallbacks for add/del_mtd_deviceSean Anderson1-2/+0
This allows using these functions without ifdefs. OneNAND depends on MTD, so this ifdef was redundant in the first place. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-11-16spl: nand: Set bl_len to page sizeSean Anderson11-1/+62
Since commit 34793598c83 ("mtd: nand: mxs_nand_spl: Remove the page aligned access") there are no longer any users of nand_get_mtd. However, it is still important to know what the page size is so we can allocate a large-enough buffer. If the image size is not page-aligned, we will go off the end of the buffer and clobber some memory. Introduce a new function nand_page_size which returns the page size. For most drivers it is easy to determine the page size. However, a few need to be modified since they only keep the page size around temporarily. It's possible that this patch could cause a regression on some platforms if the offset is non-aligned and there is invalid address space immediately before the load address. spl_load_legacy_img does not (except when compressing) respect bl_len, so only boards with SPL_LOAD_FIT (8 boards) or SPL_LOAD_IMX_CONTAINER (none in tree) would be affected. defconfig CONFIG_TEXT_BASE ======================= ================ am335x_evm 0x80800000 am43xx_evm 0x80800000 am43xx_evm_rtconly 0x80800000 am43xx_evm_usbhost_boot 0x80800000 am43xx_hs_evm 0x80800000 dra7xx_evm 0x80800000 gwventana_nand 0x17800000 imx8mn_bsh_smm_s2 0x40200000 All the sitara boards have DDR mapped at 0x80000000. gwventana is an i.MX6Q which has DDR at 0x10000000. I don't have the IMX8MNRM handy, but on the i.MX8M DDR starts at 0x40000000. Therefore all of these boards can handle a little underflow. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16nand: spl_loaders: Only read enough pages to load the imageSean Anderson1-1/+4
All other implementations of nand_spl_load_image only read as many pages as are necessary to load the image. However, nand_spl_loaders.c loads the full block. Align it with other load functions so that it is easier to determine how large of a load buffer we need. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-11-16nand: Calculate SYS_NAND_BLOCK_PAGES (neé SYS_NAND_PAGE_COUNT) automaticallySean Anderson7-17/+14
Contrary to what the help message says, this is the number of pages per block. Calculate it automatically based on SYS_NAND_BLOCK_SIZE and SYS_NAND_PAGE_SIZE. To better reflect its semantics, rename it to SYS_NAND_BLOCK_PAGES. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16nand: Don't dereference NULL manufacturer_descSean Anderson1-5/+2
When no manufacturer is matched, manufacturer_desc is NULL. Avoid dereferencing it in that case. Fixes: 4e67c571252 ("mtd,ubi,ubifs: sync with linux v3.15") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-10-30Kconfig: Remove all default n/no optionsMichal Simek1-1/+0
Similar change was done by commit b4c2c151b14b ("Kconfig: Remove all default n/no options") and again sync is required. default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
2023-10-24mtd: nand: raw: rockchip_nfc: add NAND_SKIP_BBTSCAN optionJohan Jonker2-0/+12
On Rockchip SoCs the first boot stages are written on NAND with help of manufacturer software that uses a different format then the MTD framework. Skip the automatic BBT scan with the NAND_SKIP_BBTSCAN option to be able to pass the driver probe function and to let the original data unchanged. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-13mtd: spinand: winbond: add Winbond W25N02KV flash supportMikhail Kshevetskiy1-0/+76
Add support of Winbond W25N02KV flash Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20221010105110.446674-2-mikhail.kshevetskiy@iopsys.eu Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> (U-Boot port) Link: https://lore.kernel.org/all/20230110115843.391630-5-frieder@fris.de Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-10-13mtd: spinand: winbond: fix flash identificationMikhail Kshevetskiy1-2/+2
Winbond uses 3 bytes to identify flash: vendor_id, dev_id_0, dev_id_1, but current driver uses only first 2 bytes of it for devices identification. As result Winbond W25N02KV flash (id_bytes: EF, AA, 22) is identified as W25N01GV (id_bytes: EF, AA, 21). Fix this by adding missed identification bytes. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20221010105110.446674-1-mikhail.kshevetskiy@iopsys.eu Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> (U-Boot port) Link: https://lore.kernel.org/all/20230110115843.391630-4-frieder@fris.de Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-10-13mtd/spinand: sync supported devices with linux-5.15.43Mikhail Kshevetskiy8-101/+591
This adds more supported spinand devices from the Linux kernel implementation. This does not include the latest kernel implementation as this would require a substantial amount of extra work due to the missing ECC engine abstraction layer in U-Boot. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> (commit message) Link: https://lore.kernel.org/all/20230110115843.391630-3-frieder@fris.de Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-10-13mtd/spinand: sync core spinand code with linux-5.10.118Mikhail Kshevetskiy1-10/+14
This brings us closer to the current Linux kernel implementation of the spinand core and makes backporting features and fixes easier. This does not include the latest kernel implementation as this would require a substantial amount of extra work due to the missing ECC engine abstraction layer in U-Boot. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> (add commit message) Link: https://lore.kernel.org/all/20230110115843.391630-2-frieder@fris.de Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-10-13mtd/spinand: rework detect procedure for different READ_ID operationMikhail Kshevetskiy6-186/+143
Currently there are 3 different variants of read_id implementation: 1. opcode only. Found in GD5FxGQ4xF. 2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E 3. opcode + 1 dummy byte. Found in other currently supported chips. Original implementation was for variant 1 and let detect function of chips with variant 2 and 3 to ignore the first byte. This isn't robust: 1. For chips of variant 2, if SPI master doesn't keep MOSI low during read, chip will get a random id offset, and the entire id buffer will shift by that offset, causing detect failure. 2. For chips of variant 1, if it happens to get a devid that equals to manufacture id of variant 2 or 3 chips, it'll get incorrectly detected. This patch reworks detect procedure to address problems above. New logic do detection for all variants separatedly, in 1-2-3 order. Since all current detect methods do exactly the same id matching procedure, unify them into core.c and remove detect method from manufacture_ops. This is a rework of Chuanhong Guo <gch981213@gmail.com> patch submitted to linux kernel Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/all/20230110115843.391630-1-frieder@fris.de Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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