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2019-05-09riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen2-0/+4
2019-05-09riscv: Introduce CONFIG_XIP to support booting from flashRick Chen6-0/+21
2019-04-12dts: switch spi-flash to jedec, spi-nor compatibleNeil Armstrong2-2/+2
2019-04-08riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failureRick Chen1-0/+2
2019-04-08riscv: dts: ae350 support SMPRick Chen2-44/+118
2019-04-08riscv: ax25: Andes specific cache shall only support in M-modeRick Chen1-0/+1
2019-04-08riscv: ax25: Add platform-specific Kconfig optionsRick Chen1-0/+6
2019-04-08riscv: Add a SYSCON driver for Andestech's PLMTRick Chen5-0/+67
2019-04-08riscv: Add a SYSCON driver for Andestech's PLICRick Chen5-2/+127
2019-04-08riscv: hang if relocation of secondary harts failsLukas Auer1-1/+12
2019-04-08riscv: do not rely on hart ID passed by previous boot stageLukas Auer1-0/+4
2019-04-08riscv: boot images passed to bootm on all hartsLukas Auer1-1/+12
2019-04-08riscv: add support for multi-hart systemsLukas Auer5-2/+147
2019-04-08riscv: save hart ID in register tp instead of s0Lukas Auer1-2/+2
2019-04-08riscv: delay initialization of caches and debug UARTLukas Auer1-8/+8
2019-04-08riscv: implement IPI platform functions using SBILukas Auer3-0/+31
2019-04-08riscv: import the supervisor binary interface header fileLukas Auer1-0/+94
2019-04-08riscv: add infrastructure for calling functions on other hartsLukas Auer5-0/+197
2019-02-27riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrdAnup Patel1-0/+1
2019-02-27riscv: Add SiFive FU540 board supportAnup Patel1-0/+4
2019-02-27riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel1-0/+20
2019-02-27riscv: Add place-holder asm/arch/clk.h for driver compilationAnup Patel1-0/+14
2019-02-27riscv: Add asm/dma-mapping.h for DMA mappingsAnup Patel1-0/+38
2019-02-27riscv: Rename cpu/qemu to cpu/genericAnup Patel5-2/+2
2019-01-15riscv: qemu: define standalone load addressLukas Auer1-1/+1
2019-01-15riscv: remove RISC-V standalone linker scriptLukas Auer1-1/+0
2019-01-15riscv: use invalidate/flush_*cache_range functions in cache.cLukas Auer1-2/+2
2019-01-15riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer2-6/+26
2019-01-15riscv: clarify error message on undefined exceptionsLukas Auer1-1/+2
2018-12-31riscv: bootm: Support booting VxWorksBin Meng1-1/+7
2018-12-18riscv: Remove ae350.dtsBin Meng1-229/+0
2018-12-18riscv: bootm: Change to use boot_hart from global dataBin Meng1-1/+1
2018-12-18riscv: Save boot hart id to the global dataBin Meng3-0/+24
2018-12-18riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng1-32/+30
2018-12-18riscv: Return to previous privilege level after trap handlingBin Meng1-8/+0
2018-12-18riscv: Fix context restore before returning from trap handlerBin Meng1-1/+1
2018-12-18riscv: Move trap handler codes to mtrap.SBin Meng3-90/+112
2018-12-18riscv: Do some basic architecture level cpu initializationBin Meng1-1/+26
2018-12-18riscv: Add indirect stringification to csr_xxx opsBin Meng1-7/+9
2018-12-18riscv: Update supports_extension() to use desc from cpu driverBin Meng1-0/+26
2018-12-18riscv: Add exception codes for xcause registerBin Meng1-0/+15
2018-12-18riscv: Add CSR numbersBin Meng1-0/+221
2018-12-18riscv: Remove non-DM version of print_cpuinfo()Bin Meng1-37/+0
2018-12-18riscv: Probe cpus during bootBin Meng2-0/+27
2018-12-18riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng1-0/+3
2018-12-18riscv: qemu: Add platform-specific Kconfig optionsBin Meng2-0/+12
2018-12-18riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel3-0/+47
2018-12-18riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng5-0/+116
2018-12-18riscv: Introduce a Kconfig option for machine modeAnup Patel1-5/+16
2018-12-18riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng2-11/+18