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| author | Lukas Auer <lukas.auer@aisec.fraunhofer.de> | 2019-03-17 19:28:39 +0100 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-04-08 09:44:26 +0800 |
| commit | e04324025275dee6e3e9a968c8d12e98c9b47567 (patch) | |
| tree | f3cb4c2d3ab49acd16bcf54f9419a32568ba5b73 /arch/riscv | |
| parent | f28ad250e6ef95ca58490b4e8651749d4f7e5c06 (diff) | |
| download | u-boot-e04324025275dee6e3e9a968c8d12e98c9b47567.zip u-boot-e04324025275dee6e3e9a968c8d12e98c9b47567.tar.gz u-boot-e04324025275dee6e3e9a968c8d12e98c9b47567.tar.bz2 | |
riscv: do not rely on hart ID passed by previous boot stage
RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
the previous boot stage. Machine mode firmware such as BBL and OpenSBI
do this when starting their payload (U-Boot) in supervisor mode. If
U-Boot is running in machine mode, this task must be handled by the boot
ROM. Explicitly populate register a0 with the hart ID from the mhartid
CSR to avoid possible problems on RISC-V processors with a boot ROM that
does not handle this task.
Suggested-by: Rick Chen <rick@andestech.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/start.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index f55b8cb..5ac899b 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -36,6 +36,10 @@ .section .text .globl _start _start: +#ifdef CONFIG_RISCV_MMODE + csrr a0, mhartid +#endif + /* save hart id and dtb pointer */ mv tp, a0 mv s1, a1 |