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| author | Lukas Auer <lukas.auer@aisec.fraunhofer.de> | 2019-03-17 19:28:36 +0100 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-04-08 09:44:26 +0800 |
| commit | 1446b26f7652124f0e3e98c348cdbc4fc55eb0cb (patch) | |
| tree | 58ef47a874006860056e4393224ac111ef25571d /arch/riscv | |
| parent | 2503ccc55ff2031ae2ff476fb06f666e6d1c7a64 (diff) | |
| download | u-boot-1446b26f7652124f0e3e98c348cdbc4fc55eb0cb.zip u-boot-1446b26f7652124f0e3e98c348cdbc4fc55eb0cb.tar.gz u-boot-1446b26f7652124f0e3e98c348cdbc4fc55eb0cb.tar.bz2 | |
riscv: save hart ID in register tp instead of s0
The hart ID passed by the previous boot stage is currently stored in
register s0. If we divert the control flow inside a function, which is
required as part of multi-hart support, the function epilog may not be
called, clobbering register s0. Save the hart ID in the unallocatable
register tp instead to protect the hart ID.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/start.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a30f6f7..bcc0ff6 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -36,7 +36,7 @@ .globl _start _start: /* save hart id and dtb pointer */ - mv s0, a0 + mv tp, a0 mv s1, a1 la t0, trap_entry @@ -64,7 +64,7 @@ call_board_init_f_0: jal board_init_f_init_reserve /* save the boot hart id to global_data */ - SREG s0, GD_BOOT_HART(gp) + SREG tp, GD_BOOT_HART(gp) /* Enable cache */ jal icache_enable |