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2020-04-27arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offsetLey Foon Tan1-1/+1
2020-04-22spl: mmc: Rename spl_boot_mode() to spl_mmc_boot_mode()Harald Seiler4-4/+4
2020-04-13arm: socfpga: arria10: Enable cache driver in SPLLey Foon Tan1-0/+1
2020-03-31arm: socfpga: arria10: Add save_boot_params()Ley Foon Tan1-0/+32
2020-03-31arm: socfpga: Add onchip RAM size macroLey Foon Tan2-0/+4
2020-03-03ARM: socfpga: Add initial support for the ABB SECU boardHolger Brunck1-0/+10
2020-02-11Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini2-0/+2
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass2-0/+2
2020-02-05ddr: altera: Add DDR2 support to Gen5 driverMarek Vasut3-32/+80
2020-02-03ARM: socfpga: Drop last use of socfpga_reset_managerMarek Vasut1-4/+1
2020-01-17common: Move hang() to the same header as panic()Simon Glass6-0/+6
2020-01-17common: Move reset_cpu() to the CPU headerSimon Glass1-0/+1
2020-01-07arm: socfpga: stratix10: Enable SMMU accessThor Thayer1-0/+7
2020-01-07arm: socfpga: agilex: Enable Agilex SoC buildLey Foon Tan2-0/+25
2020-01-07arm: socfpga: agilex: Add SPL for Agilex SoCLey Foon Tan2-0/+101
2020-01-07arm: agilex: Add clock handoff offset for AgilexLey Foon Tan2-4/+10
2020-01-07arm: socfpga: agilex: Add clock wrapper functionsLey Foon Tan4-0/+105
2020-01-07clk: agilex: Add clock driver for AgilexLey Foon Tan1-0/+5
2020-01-07arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHzLey Foon Tan1-3/+1
2020-01-07arm: socfpga: Move Stratix10 and Agilex clock manager common codeLey Foon Tan2-13/+26
2020-01-07arm: socfpga: agilex: Add system manager supportLey Foon Tan1-1/+2
2020-01-07arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan11-155/+158
2020-01-07arm: socfpga: agilex: Add reset manager supportLey Foon Tan1-1/+2
2020-01-07arm: socfpga: Move Stratix10 and Agilex reset manager common codeLey Foon Tan4-106/+49
2020-01-07arm: socfpga: Move firewall code to firewall fileLey Foon Tan4-95/+116
2020-01-07arm: socfpga: agilex: Add base address for Intel Agilex SoCLey Foon Tan1-0/+4
2020-01-07arm: socfpga: Convert clock manager from struct to definesLey Foon Tan9-468/+497
2020-01-07arm: socfpga: Convert system manager from struct to definesLey Foon Tan20-400/+254
2020-01-07arm: socfpga: Convert reset manager from struct to definesLey Foon Tan13-149/+150
2019-12-02common: Move some cache and MMU functions out of common.hSimon Glass2-0/+2
2019-12-02common: Move get_ticks() function out of common.hSimon Glass1-0/+1
2019-11-25ARM: socfpga: Unreset NAND in SPL on Gen5Marek Vasut1-0/+7
2019-11-25ARM: socfpga: Add ArriaV ST/SX IDMarek Vasut1-0/+2
2019-11-25ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5Marek Vasut1-0/+3
2019-11-25ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disableMarek Vasut1-1/+1
2019-11-20socfpga: fix include guard in misc.h (arch vs. global)Simon Goldschmidt1-3/+3
2019-11-07arm: socfpga: gen5: fix ERR_PTR_OFFSETSimon Goldschmidt1-0/+3
2019-10-09ARM: socfpga: vining_fpga: Rename VINING|FPGAMarek Vasut1-5/+5
2019-10-08spl: Convert CONFIG_SPL_SIZE_LIMIT to hexSimon Glass1-1/+1
2019-10-08spl: Allow tiny printf() to be controlled in SPL and TPLSimon Glass1-2/+2
2019-08-15arm: socfpga: gen5: don't zero bss in board_init_f()Simon Goldschmidt1-2/+0
2019-08-11env: Move env_set() to env.hSimon Glass2-0/+2
2019-07-21sysreset: add support for socfpga sysresetSimon Goldschmidt2-42/+0
2019-07-21arm: socfpga: rst: add register definition for cold resetSimon Goldschmidt1-0/+1
2019-06-14arm: socfpga: provide default SPL_SIZE_LIMIT for gen5Simon Goldschmidt1-0/+8
2019-05-24ARM: socfpga: Clear PL310 early in SPLMarek Vasut1-0/+1
2019-05-24ARM: socfpga: Pull PL310 clearing into common codeMarek Vasut3-57/+55
2019-05-18CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner1-2/+2
2019-05-14arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] boardWolfgang Grandegger1-0/+7
2019-05-14arm: sofcpga: s10: remove unused ad-hoc reset codeSimon Goldschmidt2-12/+0