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authorSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>2019-06-13 21:50:28 +0200
committerMarek Vasut <marex@denx.de>2019-06-14 12:41:26 +0200
commitd6d383ca27c8121f19cb5fe1b047de330833ce6f (patch)
tree66039bbd94086b15c888eb5421c746d13ad7a1de /arch/arm/mach-socfpga
parentb861cfb53c58e06513c3d4518a0d4e5ca57ec2ee (diff)
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arm: socfpga: provide default SPL_SIZE_LIMIT for gen5
This provides an SPL_SIZE_LIMIT that makes the build check that the SPL binary loaded from flash fits into the SRAM (64 KiB) and leaves enough room for global data, heap and stack (512 bytes assumed stack usage). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga')
-rw-r--r--arch/arm/mach-socfpga/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 48f02f0..1d91464 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -3,6 +3,12 @@ if ARCH_SOCFPGA
config NR_DRAM_BANKS
default 1
+config SPL_SIZE_LIMIT
+ default 65536 if TARGET_SOCFPGA_GEN5
+
+config SPL_SIZE_LIMIT_PROVIDE_STACK
+ default 0x200 if TARGET_SOCFPGA_GEN5
+
config SPL_STACK_R_ADDR
default 0x00800000 if TARGET_SOCFPGA_GEN5
@@ -49,6 +55,8 @@ config TARGET_SOCFPGA_GEN5
bool
select SPL_ALTERA_SDRAM
imply FPGA_SOCFPGA
+ imply SPL_SIZE_LIMIT_SUBTRACT_GD
+ imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
imply SPL_STACK_R
imply SPL_SYS_MALLOC_SIMPLE
imply USE_TINY_PRINTF