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2023-10-24board: rockchip: Add Xunlong Orange Pi 5Jonas Karlman6-0/+795
Xunlong Orange Pi 5 is a single-board computer based on the Rockchip RK3588S SoC. The board provides abundant interfaces, HDMI output, GPIO interface, M.2 PCIe2.0, Type-C, Gigabit LAN port, 2*USB2.0, 1*USB3.0, etc. Features tested on a Orange Pi 5 4GB v1.2: - SD-card boot - SPI Flash boot - PCIe/NVMe - USB 2.0 host - Ethernet Device tree is imported from linux v6.7-rockchip-dts64-1 tag. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24mtd: spi-nor: Add support for XMC XM25QU128CRicardo Pardini1-0/+1
Add support for XMC XM25QU128C (128M-bit) Serial Flash memory. Used on the Xunlong Orange Pi 3B, 5 and 5 Plus boards. Datasheet: https://www.xmcwh.com/uploads/806/XM25QU128C_Ver2.0.pdf Signed-off-by: Ricardo Pardini <ricardo@pardini.net> [jonas@kwiboo.se: update commit message] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24rockchip: rk3588-rock-5b: Sync USB3 nodes from mainline linux patchesJonas Karlman4-157/+99
The device tree for rk3588 and rock-5b contain usb3 nodes that have deviated too much from current state of submitted mainline linux usb3 patches, see [1]. Sync usb3 related nodes from latest patches and collaboras rk3588 tree so that dwc3-generic driver can be updated to include support for the rockchip,rk3588-dwc3 compatible in the future, use rockchip,rk3568-dwc3 compatible until final node is merged in linux maintainer tree. [1] https://lore.kernel.org/lkml/20231009172129.43568-1-sebastian.reichel@collabora.com/ Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24rockchip: rk3588-rock-5b: Enable support for PCIe SATA cardsJonas Karlman1-1/+5
Enable support for PCIe SATA cards and the on-board SATA controller. This also revert use of CONFIG_PCI_INIT_R in order to speed up boot from eMMC or SD-cards. Standard boot will initialize pci after faster boot media have been enumerated. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Tested-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24rockchip: rk3588-rock-5a: Enable support for USB 2.0 portsJonas Karlman1-1/+15
Enable Kconfig options for the two USB 2.0 ports and bottom USB 3.0 port on ROCK 5 Model A. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24rockchip: rk3588: Sync device tree from v6.7-rockchip-dts64-1 tagJonas Karlman9-85/+350
Sync rk3588 device tree from v6.7-rockchip-dts64-1 tag. Adds PCIe, button and led nodes to rk3588-evb1-v10 and rk3588-rock-5b boards. Also remove includes from u-boot.dtsi-files that is no longer needed. Linux commits: 42145b7a8235 ("arm64: dts: rockchip: add PCIe network controller to rock-5b") 199cbd5f195a ("arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b") da447ec38780 ("arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b") 86a2024d95e2 ("arm64: dts: rockchip: add PCIe2 network controller to rk3588-evb1") 46bb398ea1d8 ("arm64: dts: rockchip: add PCIe3 bus to rk3588-evb1") 1c9a53ff7ece ("arm64: dts: rockchip: Add sdio node to rock-5b") 3eaf2abd11aa ("arm64: dts: rockchip: Add sfc node to rk3588s") bf012368bb0a ("arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s") 3d77a3e51b0f ("arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s") 0002c377e862 ("arm64: dts: rockchip: Remove duplicate regulator vcc3v3_wf from rock-5b") a6169ab36923 ("arm64: dts: rockchip: Enable UART6 on rock-5b") dd6dc0c4c126 ("arm64: dts: rockchip: Add AV1 decoder node to rk3588s") afa933c208e5 ("arm64: dts: rockchip: add ADC buttons to rk3588-evb1") 7952cbbda301 ("arm64: dts: rockchip: add status LED to rock-5b") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24dt-bindings: leds: import common led bindings from linux v6.5Tom Fitzhenry1-1/+6
This brings in more colours, e.g. ORANGE needed for the QuartzPro64 DT. Linux commits: 472d7b9e8141 ("dt-bindings: leds: Expand LED_COLOR_ID definitions") Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23rockchip: dts: rk3328: Sync rock64 device tree file from LinuxMatwey V. Kornilov1-12/+2
Sync the rk3328-rock64 dts from v6.6-rc5. See Linux kernel commit for details: 03633c4ef1fb ("arm64: dts: rockchip: fix USB regulator on ROCK64") Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23board: rockchip: add FriendlyElec NanoPC-T6 rk3588 boardJohn Clark11-0/+1192
The NanoPC-T6 is a Rockchip RK3588 based SBC by FriendlyElec. There are four variants depending on the DRAM size: 4G/32GB eMMC, 8G/64GB eMMC, 16G/16MB SPI NOR, and 16G/256GB eMMC/16MB SPI NOR Specifications: CPU: Rockchip RK3588, 4x Cortex-A76 (up to 2.4GHz) + 4x Cortex-A55 (up to 1.8GHz) GPU: Mali-G610 MP4 VPU: 8K@60fps H.265 and VP9 decoder, 8K@30fps H.264 decoder, 4K@60fps AV1 decoder, 8K@30fps H.264 and H.265 encoder NPU: 6TOPs, supports INT4/INT8/INT16/FP16 RAM: 64-bit 4GB/8GB/16GB LPDDR4X at 2133MHz eMMC: 0GB/32GB/64GB/256GB HS400 MicroSD Slot: MicroSD SDR104 PCIe 3.0: M.2 M-Key x1, PCIe 3.0 x4 for NVMe SSDs up to 2,500 MB/s Ethernet: PCIe 2.5G 2x Ethernet (RTL8125BG) PCIe 2.1: M.2 E-Key x1, PCIe 2.1 x1 and USB2.0 Host, supports M.2 WiFi and Bluetooth 4G Module: MiniPCIe x1, MicroSIM Card Slot x1 Audio Out: 3.5mm jack for stereo headphone output Audio In: 2.0mm PH-2A connector for analog microphone input Video Input: standard HDMI input port, up to 4Kp60 2x 4-lane MIPI-CSI, compatible with MIPI V1.2 Video Output: 2x standard HDMI output ports compatible with HDMI2.1, HDMI2.0, and HDMI1.4 2x 4-lane MIPI-DSI, compatible with MIPI DPHY 2.0 or CPHY 1.1 USB-A: USB 3.0, Type A USB-C: Full function USB Type‑C port, DP display up to 4Kp60, USB 3.0 40-pin 2.54mm header connector: up to 2x SPIs, 6x UARTs, 1x I2Cs, 8x PWMs, 2x I2Ss, 28x GPIOs Debug UART: 3 Pin 2.54mm header, 3V level, 1500000bps Onboard IR receiver: 38KHz carrier frequency RTC Battery: 2 Pin 1.27/1.25mm RTC battery connector for low power RTC IC HYM8563TS 5V Fan connector Working Temperature: 0C to 70C Power: 5.5*2.1mm DC Jack, 12VDC input Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case) Kernel commits: 893c17716d0c ("arm64: dts: rockchip: Add NanoPC T6") a721e28dfad2 ("arm64: dts: rockchip: Add NanoPC T6 PCIe Ethernet support") ac76b786cc37 ("arm64: dts: rockchip: Add NanoPC T6 PCIe e-key support") Signed-off-by: John Clark <inindev@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23clk: rockchip: rk3588: fix up the frac pll calculationElaine Zhang1-24/+78
rk3588 frac pll: FFVCO = ((m + k / 65536) * FFIN) / p FFOUT = ((m + k / 65536) * FFIN) / (p * 2s) k is the original code, but the K[15:0] is complement code (6'b1000_0000_0000_0000 <= K[15:0] <= 16'b0111_1111_1111_1111), need to be converted. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parentElaine Zhang1-7/+17
Optimize setting process. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23clk: rockchip: rk3588: support aclk_top_root set 750MElaine Zhang1-2/+8
aclk_top_root choose a parent clock that does not change. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23clk: rk3588: Add 742.5M parameter for PLLGuochun Huang1-0/+1
For a specific frequency. Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23clk: rockchip: rk3568: support dclk_vop select more parent clksElaine Zhang1-2/+8
For dclk_vop to support more frequencies. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23rockchip: rk3568-radxa-e25: Enable pcie3x1 nodeJonas Karlman2-3/+9
Enable mini PCIe slot, pcie3x1 node, now that the PCIe PHY driver support bifurcation. A pinctrl is assigned for reset-gpios or the device may freeze running pci enum and nothing is connected to the mini PCIe slot. Also drop the AHCI_PCI Kconfig option as this option is not required for a functional M.2 SATA drive slot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-20Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini1-0/+1
- kirkwood: Pogo v4: Enable LTO (Tony)
2023-10-20arm: kirkwood: Pogo v4: Enable LTOTony Dinh1-0/+1
Enable building Pogo V4 u-boot image with LTO, which results in about 30K reduction in size. Rebased to latest master and resend. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-19Merge branch 'master_uart_test' of ↵WIP/19Oct2023Tom Rini3-3/+48
https://source.denx.de/u-boot/custodians/u-boot-sh
2023-10-19serial: sh: Add RZ/G2L SCIF supportPaul Barker3-1/+34
Extend the existing driver to support the SCIF serial ports on the Renesas RZ/G2L (R9A07G044) SoC. This also requires us to ensure that if there is a reset signal defined in the device tree, it is de-asserted before we try to talk to the SCIF module. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # R-Car H3 Salvator-XS
2023-10-19serial: sh: Fix error handlingPaul Barker1-2/+14
The current SCIF error handling is broken for the RZ/G2L. After a break condition has been triggered, the current code is unable to clear the error and serial port output never resumes. The RZ/G2L datasheet says that most error conditions are cleared by resetting the relevant error bits in the FSR & LSR registers to zero. To clear framing errors on SCIF ports, the invalid data also needs to be read out of the receive FIFO. After reviewing datasheets for RZ/G2{H,M,N,E}, R-Car Gen4, R-Car Gen3 and even SH7751 SoCs, it's clear that this is the way to clear errors for all of these SoCs. While we're here, annotate the handle_error() function with a couple of comments as the reads and writes themselves don't immediately make it clear what we're doing. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Tested-by: Chris Paterson <chris.paterson2@renesas.com> # HiHope RZ/G2M board Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # R-Car H3 Salvator-XS
2023-10-19Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini19-46/+738
+ riscv: Add Zbb support + riscv: Add preliminary RISC-V falcon mode support + riscv: Remove dram_init_banksize() + andes: rearrange PLICSW scheme + visionfive2: enable bootstage configs
2023-10-19Merge branch 'master' of ↵Tom Rini3-5/+11
https://source.denx.de/u-boot/custodians/u-boot-watchdog - sandbox: watchdog: Avoid an error on startup (Simon) - nuvoton: Fix reset/expire function error (Jim)
2023-10-19riscv: Add Zbb support for building U-BootYu Chien Peter Lin7-1/+392
This patch adds ISA string to the -march to generate zbb instructions for U-Boot binaries, along with optimized string functions introduced from Linux kernel. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19riscv: spl: andes: Move the DTB in front of kernelRandolph1-0/+25
Originally, u-boot SPL will place the DTB directly after the kernel, but the size of the kernel does not include the BSS section, This means that u-boot SPL places the DTB in the kernel BSS section causing the DTB to be cleared by the kernel BSS initialisation. Moving the DTB in front of the kernel can avoid this error. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19andes: config: add riscv falcon mode for ae350 platformRandolph4-0/+242
Fork from ae350_rv[32/64]_spl_[xip]_defconfig and append CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19spl: riscv: add os type for next booting stageRandolph2-3/+9
If SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled, the function spl_invoke_opensbi should change the target OS type to IH_OS_LINUX. OpenSBI will load the Linux image as the next boot stage. The os_takes_devicetree function returns a value of true or false depending on whether or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19Makefile: delete file *.itb when make cleanRandolph1-1/+1
Delete the output file *.itb Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19riscv: dts: binman: add condition for opensbi os bootRandolph1-0/+24
Add condition for OpenSBI OS boot mode, by default it is not enabled. By default, binman creates the output file u-boot.itb. If SPL_OPENSBI_OS_BOOT is enabled, linux.itb will be created after compilation instead of the default u-boot.itb. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbolRandolph1-0/+8
Introduce common Kconfig symbol for riscv architecture. This symbol SPL_LOAD_FIT_OPENSBI_OS_BOOT is like falcon mode on ARM, the Falcon boot is a shortcut boot method for SD/eMMC targets. It skips the loading the RAM version U-Boot. Instead, it will loads the FIT image and boots directly to Linux. When SPL_OPENSBI_OS_BOOT is enabled, linux.itb is created after compilation instead of the default u-boot.itb. It initialises memory with the U-Boot SPL at the first stage, just as a normal boot process does at the beginning. Instead of jumping to the U-Boot proper from OpenSBI before booting the Linux kernel, the RISC-V falcon mode process jumps directly to the Linux kernel to gain shorter booting time. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19spl: riscv: opensbi: change the default os_type as varibleRandolph1-10/+16
In order to introduce the Opensbi OS boot mode, the next stage boot image of OpenSBI should be configurable. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategyRandolph1-13/+11
Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19riscv: binman: Fix compilation errorMayuresh Chitale1-4/+10
Some platforms may not have any DDR memory below 4G and for such platforms the TEXT_BASE and LOAD addresses etc are all 64 bit addresses due to which the u-boot build fails with below error: u-boot/arch/riscv/dts/binman.dtsi:30.14-25 Value out of range for 32-bit array element u-boot/arch/riscv/dts/binman.dtsi:43.14-25 Value out of range for 32-bit array element u-boot/arch/riscv/dts/binman.dtsi:44.15-26 Value out of range for 32-bit array element FATAL ERROR: Syntax error parsing input tree Fix by setting the address-cells property to 2 and converting load addresses to 64 bit values. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19configs: visionfive2: enable bootstage configsChanho Park1-0/+2
Enable BOOTSTAGE configuration and its command for visionfive2 board. The feature can be useful for analyzing the elapsed time between boot stages. TODO: define / reserve memory region for boot stage stash StarFive # bootstage report Timer summary in microseconds (10 records): Mark Elapsed Stage 0 0 reset 3,139,338 3,139,338 board_init_f 3,176,753 37,415 board_init_r 4,036,111 859,358 eth_common_init 4,101,599 65,488 eth_initialize 4,105,799 4,200 main_loop 4,145,207 39,408 usb_start 5,440,963 1,295,756 cli_loop Accumulated time: 10,093 dm_f 15,867 dm_r Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19riscv: remove dram_init_banksize()Heinrich Schuchardt1-16/+0
Remove dram_init_banksize() on the architecture level. Limiting used RAM to under 4 GiB is only necessary for CPUs which have a DMA issue. SoC specific code already exists for FU540, FU740, JH7110. Not all RISC-V boards will have memory below 4 GiB. A weak implementation of dram_init_banksize() exists in common/board_f.c. See the discussion in https://lore.kernel.org/u-boot/545fe813-cb1e-469c-a131-0025c77aeaa2@canonical.com/T/ Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-10-19wdt: nuvoton: Fix reset/expire function errorJim Liu1-2/+8
Fix npcm845 watchdog halt for reset function and expire function. Reset function is restart wdt. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-19sandbox: watchdog: Avoid an error on startupSimon Glass2-3/+3
For some time now running sandbox with -T produces an error: Core: 270 devices, 95 uclasses, devicetree: board WDT: Not starting wdt-gpio-toggle wdt_gpio wdt-gpio-level: Request for wdt gpio failed: -16 WDT: Not starting wdt@0 MMC: mmc2: 2 (SD), mmc1: 1 (SD), mmc0: 0 (SD) Use an unallocated GPIO to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 1fc45d6483d ("watchdog: add pulse support to gpio watchdog driver") Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-18Merge branch '2023-10-17-spl-test-some-load-methods'Tom Rini70-161/+1994
To quote the author: This series adds some tests for various SPL load methods, with the intent of helping debug v6 of [1]. With that in mind, notable omissions include NAND and ROMAPI, which both lack sandbox implementations, and OS_BOOT, which I have deferred due to its complexity. Semihosting is also omitted, but I think we can test that with qemu. In order to test all of these methods, we must first generate suitable images, possibly on filesystems. While other tests have historically generated these images using external tools (e.g. mkimage, mkfs, etc.), I have chosen to generate them on the fly. This is for a few reasons: - By removing external dependencies on pytest to create certain files, the tests become self-contained. This makes them easier to iterate on and debug. - By generating tests at runtime, we can dynamically vary the content. This helps detect test failures, as even if tests are loaded to the same location, the expected content will be different. - We are not testing the image parsers themselves (e.g. spl_load_simple_fit or fs_read) but rather the load methods (e.g. spl_mmc_load_image). It is unnecessary to exercise full functionality or generate 100% correct images. - By reducing functionality to only what is necessary, the complexity of various formats can often be greatly reduced. This series depends on [2-3], which are small fixes identified through this patch set. The organization of patches in this series is as follows: - General fixes for bugs which are unlikely to be triggered outside of this series - Changes to IMX8 container images to facilitate testing - General prep. work, particularly regarding linker issues - The tests themselves Passing CI at [4]. [1] https://lore.kernel.org/all/20230731224304.111081-1-sean.anderson@seco.com/ [2] https://lore.kernel.org/all/20230930204246.515254-1-seanga2@gmail.com/ [3] https://lore.kernel.org/all/20231008014748.1987840-1-seanga2@gmail.com/ [4] https://source.denx.de/u-boot/custodians/u-boot-clk/-/pipelines/18128
2023-10-17test: spl: Add a test for the SPI load methodSean Anderson8-0/+78
Add test for the SPI load method. This one is pretty straightforward. We can't enable FIT_EXTERNAL with LOAD_FIT_FULL because spl_spi_load_image doesn't know the total image size and has to guess from fdt_totalsize. This doesn't include external data, so loading it will fail. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17test: spl: Add a test for the NOR load methodSean Anderson8-6/+316
Add a test for the NOR load method. Since NOR is memory-mapped we can substitute a buffer instead. The only major complication is testing LZMA decompression. It's too complex to implement LZMA compression in a test, and we have no in-tree compressor, so we just include some pre-compressed data. This data was generated through something like generate_data(plain, plain_size, "lzma") cat plain.dat | lzma | hexdump -C and was cleaned up further in my editor. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17test: spl: Add a test for the NET load methodSean Anderson6-1/+272
Add a test for loading U-Boot over TFTP. As with other sandbox net routines, we need to initialize our packets manually since things like net_set_ether and net_set_udp_header always use "our" addresses. We use BOOTP instead of DHCP, since DHCP has a tag/length-based format which is harder to parse. Our TFTP implementation doesn't define as many constants as I'd like, so I create some here. Note that the TFTP block size is one-based, but offsets are zero-based. In order to avoid address errors, we need to set up/define some additional address information settings. dram_init_banksize would be a good candidate for settig up bi_dram, but it gets called too late in board_init_r. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17test: spl: Add a test for the MMC load methodSean Anderson6-5/+137
Add a test for the MMC load method. This shows the general shape of tests to come: The main test function calls do_spl_test_load with an appropriate callback to write the image to the medium. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17test: spl: Add a test for spl_blk_load_imageSean Anderson3-1/+67
Add a test for spl_blk_load_image, currently used only by NVMe. Because there is no sandbox NVMe driver, just use MMC instead. Avoid falling back to raw images to make failures more obvious. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17test: spl: Add functions to create filesystemsSean Anderson5-0/+328
Add some functions for creating fat/ext2 filesystems with a single file and a test for them. Filesystems require block devices, and it is easiest to just use MMC for this. To get an MMC, we must also pull in the test device tree. SPL_TIMER is necessary for SPL_MMC, perhaps because it uses a timeout. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17test: spl: Add functions to create imagesSean Anderson8-3/+493
This add some basic functions to create images, and a test for said functions. This is not intended to be a test of the image parsing functions, but rather a framework for creating minimal images for testing load methods. That said, it does do an OK job at finding bugs in the image parsing directly. Since we have two methods for loading/parsing FIT images, add LOAD_FIT_FULL as a separate CI run. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17test: spl: Fix spl_test_load not failing if fname doesn't existSean Anderson2-4/+3
Returning a negative value from a unit test doesn't automatically fail the test. We have to fail an assertion. Modify the test to do so. This now causes the test to count as a failure on VPL. This is because the fname of SPL (and U-Boot) is generated with make_exec in os_jump_to_image. The original name of SPL is gone, and we can't determine the name of U-Boot from the generated name. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17test: spl: Split tests up and use some configsSean Anderson6-79/+106
In order to make adding new spl unit tests easier, especially when they may have many dependencies, add some Kconfigs for the existing image test. Split it into the parts which are generic (such as callbacks) and the test-specific parts. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17sandbox: Support -T in splSean Anderson1-2/+7
The test devicetree is only compiled for U-Boot proper. When accessing it in SPL we need to go up one directory. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17spl: Use map_sysmem where appropriateSean Anderson11-35/+69
All "physical" addresses in SPL must be converted to virtual addresses before access in order for sandbox to work. Add some calls to map_sysmem in appropriate places. We do not generally call unmap_sysmem, since we need the image memory to still be mapped when we jump to the image. This doesn't matter at the moment since unmap_sysmem is a no-op. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-17spl: Add callbacks to invalidate cached devicesSean Anderson3-1/+34
Several SPL functions try to avoid performing initialization twice by caching devices. This is fine for regular boot, but does not work with UNIT_TEST, since all devices are torn down after each test. Add some functions to invalidate the caches which can be called before testing these load methods. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-10-17net: bootp: Fall back to BOOTP from DHCP when unit testingSean Anderson1-0/+6
If we sent a DHCP packet and get a BOOTP response from the server, we shouldn't try to send a DHCPREQUEST packet, since it won't be DHCPACKed. Transition straight to BIND. This is only enabled for UNIT_TEST to avoid bloat, since I suspect the number of BOOTP servers in the wild is vanishingly small. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-12 00:50:00 +0000