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| author | Elaine Zhang <zhangqing@rock-chips.com> | 2023-10-11 18:29:43 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-10-23 18:21:55 +0800 |
| commit | bdb35a286360c787c0bf9570b41e63e493d5c989 (patch) | |
| tree | 6f7b459558311e6314dc256674c131e073eb3a79 | |
| parent | de7f4bb1f17291dfae1e7f3c7066314321f359c7 (diff) | |
| download | u-boot-bdb35a286360c787c0bf9570b41e63e493d5c989.zip u-boot-bdb35a286360c787c0bf9570b41e63e493d5c989.tar.gz u-boot-bdb35a286360c787c0bf9570b41e63e493d5c989.tar.bz2 | |
clk: rockchip: rk3568: support dclk_vop select more parent clks
For dclk_vop to support more frequencies.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3568.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 599b7b1..68f5bbb 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1838,7 +1838,7 @@ static ulong rk3568_dclk_vop_set_clk(struct rk3568_clk_priv *priv, rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], priv->cru, VPLL, div * rate); } else { - for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) { + for (i = sel; i <= DCLK_VOP_SEL_CPLL; i++) { switch (i) { case DCLK_VOP_SEL_GPLL: pll_rate = priv->gpll_hz; @@ -2785,9 +2785,15 @@ static int rk3568_dclk_vop_set_parent(struct clk *clk, struct clk *parent) if (parent->id == PLL_VPLL) { rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT); - } else { + } else if (parent->id == PLL_HPLL) { rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT); + } else if (parent->id == PLL_CPLL) { + rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, + DCLK_VOP_SEL_CPLL << DCLK0_VOP_SEL_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, + DCLK_VOP_SEL_GPLL << DCLK0_VOP_SEL_SHIFT); } return 0; |