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| author | Guochun Huang <hero.huang@rock-chips.com> | 2023-10-11 18:29:44 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-10-23 18:21:55 +0800 |
| commit | 39fb8acac42652bf7c1388471b7321e6c6ec1859 (patch) | |
| tree | d0234955aa741eedd1c27c1023e9bdfc1b94dae9 | |
| parent | bdb35a286360c787c0bf9570b41e63e493d5c989 (diff) | |
| download | u-boot-39fb8acac42652bf7c1388471b7321e6c6ec1859.zip u-boot-39fb8acac42652bf7c1388471b7321e6c6ec1859.tar.gz u-boot-39fb8acac42652bf7c1388471b7321e6c6ec1859.tar.bz2 | |
clk: rk3588: Add 742.5M parameter for PLL
For a specific frequency.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3588.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 119b133..c861762 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -36,6 +36,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { RK3588_PLL_RATE(816000000, 2, 272, 2, 0), RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), RK3588_PLL_RATE(786000000, 1, 131, 2, 0), + RK3588_PLL_RATE(742500000, 4, 495, 2, 0), RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), RK3588_PLL_RATE(600000000, 2, 200, 2, 0), RK3588_PLL_RATE(594000000, 2, 198, 2, 0), |