| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2025-03-09 | target/mips: Move has_work() from CPUClass to SysemuCPUOps | Philippe Mathieu-Daudé | 1 | -1/+3 |
| 2025-03-06 | target/mips: Set disassemble_info::endian value in disas_set_info() | Philippe Mathieu-Daudé | 1 | -5/+5 |
| 2025-03-06 | accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2025-01-13 | target: Replace DEVICE(object_new) -> qdev_new() | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2024-12-24 | accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core | Richard Henderson | 1 | -0/+1 |
| 2024-12-21 | Merge tag 'exec-20241220' of https://github.com/philmd/qemu into staging | Stefan Hajnoczi | 1 | -6/+2 |
| 2024-12-20 | target/mips: Drop left-over comment about Jazz machine | Philippe Mathieu-Daudé | 1 | -4/+0 |
| 2024-12-20 | include: Rename sysemu/ -> system/ | Philippe Mathieu-Daudé | 1 | -2/+2 |
| 2024-12-19 | include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LIST | Richard Henderson | 1 | -1/+0 |
| 2024-12-15 | target/mips: Constify all Property | Richard Henderson | 1 | -1/+1 |
| 2024-12-10 | target/mips: Replace type_register() with type_register_static() | Zhao Liu | 1 | -1/+1 |
| 2024-11-05 | target/mips: Explicitly set 2-NaN propagation rule | Peter Maydell | 1 | -1/+1 |
| 2024-10-15 | hw/mips: Have mips_cpu_create_with_clock() take an endianness argument | Philippe Mathieu-Daudé | 1 | -1/+4 |
| 2024-10-15 | target/mips: Expose MIPSCPU::is_big_endian property | Philippe Mathieu-Daudé | 1 | -4/+8 |
| 2024-07-11 | target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation | Peter Maydell | 1 | -0/+1 |
| 2024-04-25 | hw, target: Add ResetType argument to hold and exit phase methods | Peter Maydell | 1 | -2/+2 |
| 2024-03-12 | target/mips: Prefer fast cpu_env() over slower CPU QOM cast macro | Philippe Mathieu-Daudé | 1 | -11/+4 |
| 2024-03-12 | target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handler | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2024-02-03 | target/mips: Populate CPUClass.mmu_index | Richard Henderson | 1 | -0/+6 |
| 2024-01-29 | include/qemu: Add TCGCPUOps typedef to typedefs.h | Richard Henderson | 1 | -1/+1 |
| 2023-10-04 | accel/tcg: Remove cpu_set_cpustate_pointers | Richard Henderson | 1 | -1/+0 |
| 2023-10-03 | target/*: Add instance_align to all cpu base classes | Richard Henderson | 1 | -0/+1 |
| 2023-07-10 | target/mips: Implement Loongson CSR instructions | Jiaxun Yang | 1 | -0/+10 |
| 2023-07-10 | target/mips: Rework cp0_timer with clock API | Jiaxun Yang | 1 | -3/+5 |
| 2023-03-22 | *: Add missing includes of qemu/error-report.h | Richard Henderson | 1 | -0/+1 |
| 2023-03-08 | target/mips: Implement CP0.Config7.WII bit support | Marcin Nowakowski | 1 | -1/+3 |
| 2023-01-13 | target/mips: Restrict 'qapi-commands-machine.h' to system emulation | Philippe Mathieu-Daudé | 1 | -29/+0 |
| 2023-01-13 | mips: Always include nanomips disassembler | Paolo Bonzini | 1 | -2/+0 |
| 2023-01-13 | mips: Remove support for trap and emulate KVM | Paolo Bonzini | 1 | -6/+1 |
| 2022-12-16 | target/mips: Convert to 3-phase reset | Peter Maydell | 1 | -4/+8 |
| 2022-11-08 | target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F | Jiaxun Yang | 1 | -0/+6 |
| 2022-10-26 | target/mips: Convert to tcg_ops restore_state_to_opc | Richard Henderson | 1 | -0/+1 |
| 2022-10-04 | hw/core: Add CPUClass.get_pc | Richard Henderson | 1 | -0/+8 |
| 2022-06-11 | target/mips: Fix WatchHi.M handling | Marcin Nowakowski | 1 | -1/+1 |
| 2022-04-06 | Replace TARGET_WORDS_BIGENDIAN | Marc-André Lureau | 1 | -2/+2 |
| 2022-03-07 | target/mips: Remove duplicated MIPSCPU::cp0_count_rate | Philippe Mathieu-Daudé | 1 | -10/+0 |
| 2022-03-07 | target/mips: Fix cycle counter timing calculations | Simon Burge | 1 | -1/+2 |
| 2021-11-02 | target/mips: Make mips_cpu_tlb_fill sysemu only | Richard Henderson | 1 | -1/+1 |
| 2021-09-14 | target/mips: Restrict cpu_exec_interrupt() handler to sysemu | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2021-06-24 | target/mips: Optimize regnames[] arrays | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2021-05-26 | hw/core: Constify TCGCPUOps | Richard Henderson | 1 | -1/+1 |
| 2021-05-26 | cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2021-05-26 | cpu: Move CPUClass::vmsd to SysemuCPUOps | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2021-05-26 | cpu: Introduce SysemuCPUOps structure | Philippe Mathieu-Daudé | 1 | -0/+8 |
| 2021-05-26 | cpu: Rename CPUClass vmsd -> legacy_vmsd | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2021-05-02 | target/mips: Move CP0 helpers to sysemu/cp0.c | Philippe Mathieu-Daudé | 1 | -103/+0 |
| 2021-05-02 | target/mips: Move exception management code to exception.c | Philippe Mathieu-Daudé | 1 | -113/+0 |
| 2021-05-02 | target/mips: Move Special opcodes to tcg/sysemu/special_helper.c | Philippe Mathieu-Daudé | 1 | -17/+0 |
| 2021-05-02 | target/mips: Restrict mmu_init() to TCG | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2021-05-02 | target/mips: Declare mips_env_set_pc() inlined in "internal.h" | Philippe Mathieu-Daudé | 1 | -7/+1 |
