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13 days[RISC-V] Update SpacemiT-X60 Vector Integer latencies (#149207)Mikhail R. Gadelha8-5662/+5662
2025-07-16[RISCV] Pre-commit RVV instructions to the x60 scheduling model and testsMikhail R. Gadelha14-298/+34993
2025-07-09[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructio...Min-Yih Hsu4-0/+344
2025-07-09[RISCV] Add scheduling info for XSfvfnrclipxfqf instructions (#147586)Min-Yih Hsu2-0/+161
2025-06-23[RISCV] Add SiFive X390 scheduling model (#143938)Min-Yih Hsu9-0/+9990
2025-06-23[RISCV] Factor out common SiFive7 scheduling model into an abstraction layer ...Min-Yih Hsu30-367/+367
2025-06-22Revert "Revert "[RISCV] Remove B and Zbc extension from Andes series cpus." (...Jim Lin1-1/+1
2025-06-19[RISCV] Update SpacemiT X60 scheduling latencies based on hardware measuremen...Mikhail R. Gadelha3-105/+105
2025-06-16Revert "[RISCV] Remove B and Zbc extension from Andes series cpus." (#144402)Aaron Ballman1-1/+1
2025-06-15[RISCV] Remove B and Zbc extension from Andes series cpus. (#144022)Jim Lin1-1/+1
2025-06-04[RISCV] Implement base scheduling model for andes 45 series processor. (#141008)Jim Lin2-0/+381
2025-05-20[RISCV] Add scheduling model for SiFive P800 processors (#139316)Min-Yih Hsu18-0/+9871
2025-05-06[RISCV] Add scheduler definitions for SpacemiT-X60 (#137343)Mikhail R. Gadelha3-0/+1077
2025-03-27[RISCV] Update the latency of floating point load in SiFive P500 scheduling m...Min-Yih Hsu1-5/+5
2025-03-25[MCA] Update of RISCV/SiFive7/instruction-tables-tests.s (#132972)Julien Villette1-11/+11
2025-03-25[MCA] Extend -instruction-tables option with verbosity levels (#130574)Julien Villette1-0/+415
2025-03-24[MC] Account for AcquireAtCycle in getReciprocalThroughput (#132653)Min-Yih Hsu25-827/+827
2025-03-17[RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models ...Min-Yih Hsu6-0/+2901
2025-02-28[RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operatio...Min-Yih Hsu2-270/+270
2025-02-28[RISCV] Remove non-portable vsetvli instructions from llvm-mca test. NFC (#12...Craig Topper1-187/+7
2025-02-27[RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also...Craig Topper1-1/+1
2025-02-26[RISCV] Adding missing P600 sched model test for RVV segmented loads/storesMin-Yih Hsu1-0/+4730
2025-02-26[RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (#128786)Min-Yih Hsu3-5/+5
2025-02-14[RISCV] Add a generic OOO CPU (#120712)Pengcheng Wang3-0/+1465
2025-01-31[RISCV] Remove potentially incompatible vtype toggles fro mvlseg-vsseg mca te...Michael Maitland1-2275/+7
2025-01-30[RISCV] Cleanup vlseg-vsseg mca tests (#125099)Michael Maitland1-7431/+4599
2025-01-29[RISCV][SIFIVE] Fix latencies for vector integer arithmetic long latency (#12...Michael Maitland1-67/+67
2025-01-27[RISCV] Add P550 scheduler model. (#124639)Craig Topper3-0/+409
2025-01-22[MCA] Use MCInstrAnalysis to analyse call/return instructions (#123882)Pengcheng Wang1-9/+6
2025-01-22[RISCV] Add precommit test for #123882Wang Pengcheng1-0/+81
2025-01-07[RISCV] Update the latencies of MUL and CPOP in SiFive P400 scheduling model ...Min-Yih Hsu1-0/+60
2025-01-07[RISCV] Add missing SiFive P400 scheduling model test for divisions. NFCMin-Yih Hsu1-0/+1009
2024-12-20[RISC-V] Base scheduling model for tt-ascalon-d8 (#120160)Petr Penzin2-0/+158
2024-12-19Reland "[RISCV] Add scheduling model for mips p8700 CPU" (#120550)Djordje Todorovic1-0/+139
2024-12-19Revert "[RISCV] Add scheduling model for mips p8700 CPU" (#120537)Djordje Todorovic1-143/+0
2024-12-19[RISCV] Add scheduling model for mips p8700 CPU (#119885)Djordje Todorovic1-0/+143
2024-12-19[RISCV][MCA] Move sifive-x280 tests to directory SiFiveX280 (#120522)Pengcheng Wang30-0/+0
2024-12-04[RISCV] Mark vmvNr.v as implicitly using vtype (#118414)Luke Lau2-6/+6
2024-11-21[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models ...Min-Yih Hsu1-7/+12
2024-11-12[RISCV] Update SiFive P600's scheduling model on RVV instructions (#115243)Min-Yih Hsu8-329/+1274
2024-11-06[RISCV] Refine vector division latencies in SiFive P600's scheduling model (#...Min-Yih Hsu1-0/+1012
2024-11-05[RISCV] Update latency of MUL & CPOP in SiFive P600's scheduling model (#115042)Min-Yih Hsu1-0/+63
2024-09-17[RISCV] Add scheduling model for Syntacore SCR7 (#108814)Anton Sidorenko4-0/+268
2024-08-19[RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (#102155)Michael Maitland14-8/+12764
2024-08-14[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909)Anton Sidorenko5-148/+501
2024-06-25[RISCV] Add scheduling model for Syntacore SCR3 (#95427)Anton Sidorenko2-0/+148
2024-05-30[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling mo...Min-Yih Hsu2-0/+120
2024-05-03[RISCV] Add Sched classes for vector crypto instructions (#90068)Michael Maitland7-309/+309
2024-05-03[RISCV][llvm-mca] Add vector crypto llvm-mca tests for P600Michael Maitland7-0/+1272
2024-03-14[RISCV] Model integer min max instructions from Zbb execute in late-B ALUMichael Maitland1-7/+7
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