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path: root/llvm/test/Transforms/InferAddressSpaces/AMDGPU
AgeCommit message (Expand)AuthorFilesLines
2026-02-17[NFC][AMDGPU] Use `zeroinitializer` instead of `null` for `ptr addrspace(2/3/...Shilei Tian4-8/+8
2026-02-05IR: Promote "denormal-fp-math" to a first class attribute (#174293)Matt Arsenault1-1/+1
2026-01-14[InferAddressSpaces] Handle unconverted ptrmask (#140802)Robert Imschweiler1-13/+240
2025-11-14[InferAddressSpaces] Fix bad `addrspacecast` insertion for phinode (#163528)Kerang Mao1-0/+55
2025-11-11InferAddressSpaces: Add more baseline tests for assume handling (#167611)Matt Arsenault1-8/+200
2025-10-20[IR] Replace alignment argument with attribute on masked intrinsics (#163802)Nikita Popov1-6/+6
2025-09-24[AMDGPU] Add the support for 45-bit buffer resource (#159702)Shilei Tian1-7/+7
2025-09-19[InferAddressSpaces] Mark ConstantAggregateZero as safe to cast to a Constant...Wenju He2-4/+2
2025-09-19[InferAddressSpaces] Extend undef pointer operand support to phi inst (#159548)Wenju He1-0/+36
2025-09-12[llvm] Regenerate test checks including TBAA semantics (NFC)Antonio Frighetto1-12/+12
2025-08-08[IR] Remove size argument from lifetime intrinsics (#150248)Nikita Popov1-4/+4
2025-07-23[Tests] Avoid lifetime intrinsics on non-allocas (NFC)Nikita Popov1-7/+5
2025-05-30Reapply "Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer ...Shilei Tian2-12/+26
2025-05-30Revert "Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer k...Shilei Tian2-26/+12
2025-05-30Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel ar...Shilei Tian2-12/+26
2025-05-30Revert "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arg...Shilei Tian2-26/+12
2025-05-30[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arguments (...Shilei Tian2-12/+26
2025-05-29[AMDGPU] Move InferAddressSpacesPass to middle end optimization pipeline (#13...Shilei Tian1-0/+23
2025-05-23[NFC][AMDGPU] Move `flat_atomic.ll` to `llvm/test/CodeGen/AMDGPU/` (#141126)Shilei Tian1-177/+0
2025-05-22[InferAddressSpaces] Handle llvm.lifetime (#141045)QiYue1-0/+22
2025-05-20[AMDGPU] Add make.buffer.rsrc to InferAddressSpaces (#140770)Krzysztof Drewniak1-0/+16
2025-05-19[AMDGPU] Set AS8 address width to 48 bitsAlexander Richardson1-1/+1
2025-05-19[AMDGPU] Add a new amdgcn.load.to.lds intrinsic (#137425)Krzysztof Drewniak1-0/+23
2025-04-30[AMDGPU] Remove explicit datalayout from tests where not neededAlexander Richardson1-2/+0
2025-04-28[NFC][AMDGPU] Auto generate check lines for some codegen tests (#137534)Shilei Tian2-93/+207
2025-03-06InferAddressSpaces: Replace undef with poison in tests (#130083)Matt Arsenault10-42/+58
2025-01-29[IR] Convert from nocapture to captures(none) (#123181)Nikita Popov1-1/+1
2025-01-23AMDGPU: Make vector_shuffle legal for v2i32 with v_pk_mov_b32 (#123684)Matt Arsenault1-2/+1
2025-01-10Revert "[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#119826)"Nikita Popov1-13/+15
2025-01-09[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#119826)Pengcheng Wang1-15/+13
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian1-42/+42
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian1-42/+42
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian1-42/+42
2024-11-06[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)Paul Walker1-1/+1
2024-10-31AMDGPU: Expand flat atomics that may access private memory (#109407)Matt Arsenault1-4/+5
2024-10-09AMDGPU: Remove flat/global fmin/fmax intrinsics (#105642)Matt Arsenault2-281/+6
2024-09-30AMDGPU: Fix assertion on load of vector of pointers (#110436)Matt Arsenault1-0/+45
2024-08-22AMDGPU: Remove global/flat atomic fadd intrinics (#97051)Matt Arsenault2-67/+72
2024-08-16InferAddressSpaces: Convert test to generated checksMatt Arsenault1-53/+98
2024-08-15InferAddressSpaces: Restore non-instruction user checkMatt Arsenault1-0/+8
2024-08-08InferAddressSpaces: Improve handling of instructions with multiple pointer us...Matt Arsenault1-7/+154
2024-08-06InferAddressSpaces: Handle llvm.is.constant (#102010)Matt Arsenault1-0/+56
2024-08-06InferAddressSpaces: Handle masked load and store intrinsics (#102007)Matt Arsenault1-0/+68
2024-08-06InferAddressSpaces: Handle prefetch intrinsic (#101982)Matt Arsenault1-0/+59
2024-08-04InferAddressSpaces: Fix mishandling stores of pointers to themselves (#101877)Matt Arsenault1-0/+71
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault1-25/+25
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung1-25/+25
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault1-25/+25
2024-07-03[DebugInfo][InferAddressSpaces] Fix the missing debug location update for the...Shan Huang1-0/+33
2024-06-18AMDGPU: Flat instructions do not have signed offsets gfx7-gfx11 (#95852)Matt Arsenault1-2/+4
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