| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2025-06-12 | [X86] VPTERNLOG comments - use "mem" just for full width loads and "m32bcst" ... | Shamshura Egor | 1 | -4/+4 |
| 2025-04-29 | [X86] shouldReduceLoadWidth - don't split loads if we can freely reuse full w... | Simon Pilgrim | 1 | -194/+194 |
| 2025-04-01 | [X86] splitVector - split concat_vectors(a,b,c,d) -> concat_vectors(a,b) + co... | Simon Pilgrim | 1 | -82/+82 |
| 2025-03-31 | [DAG] visitEXTRACT_SUBVECTOR - don't return early on failure of EXTRACT_SUBVE... | Simon Pilgrim | 1 | -8/+4 |
| 2025-03-14 | [X86] combineINSERT_SUBVECTOR - peek through bitcasts to find a concatenation... | Simon Pilgrim | 1 | -1686/+1630 |
| 2025-03-11 | [X86] combineConcatVectorOps - add support for AVX1 and/or/xor/andnp concaten... | Simon Pilgrim | 1 | -180/+180 |
| 2025-03-06 | [X86] Extend shuf128(concat(x,y),concat(z,w)) -> shuf128(widen(y),widen(w)) f... | Simon Pilgrim | 1 | -76/+68 |
| 2024-10-23 | [MCP] Optimize copies when src is used during backward propagation (#111130) | Vladimir Radosavljevic | 1 | -25/+17 |
| 2024-10-01 | [X86] Let's improve the expression we dump for vpternlog | David Majnemer | 1 | -160/+160 |
| 2024-09-30 | [X86] Decode VPTERNLOG truth tables when disassembling | David Majnemer | 1 | -148/+160 |
| 2024-07-17 | [X86] Fold blend(pshufb(x,m1),pshufb(y,m2)) -> blend(pshufb(x,blend(m1,m2)),p... | Simon Pilgrim | 1 | -38/+48 |
| 2024-02-02 | [X86] X86FixupVectorConstants - load+sign-extend vector constants that can be... | Simon Pilgrim | 1 | -288/+288 |
| 2024-01-31 | [X86][CodeGen] Support folding memory broadcast in X86InstrInfo::foldMemoryOp... | Shengchen Kan | 1 | -792/+778 |
| 2024-01-29 | [X86][test] Update failed tests in 60dbb2cec1bbf65aacf6752a59b0666a23aaa3ae a... | Shengchen Kan | 1 | -778/+792 |
| 2024-01-29 | [X86][test] Update CHECK prefixes in CodeGen/X86/vector-interleaved-store-*.l... | Shengchen Kan | 1 | -4452/+6382 |
| 2024-01-23 | [MC][X86] Merge lane/element broadcast comment printers. (#79020) | Simon Pilgrim | 1 | -118/+118 |
| 2023-12-11 | [X86] combineConcatVectorOps - constant fold vector load concatenation direct... | Simon Pilgrim | 1 | -137/+139 |
| 2023-12-08 | [X86] canonicalizeBitSelect - always use VPTERNLOGD for sub-32bit types | Simon Pilgrim | 1 | -22/+22 |
| 2023-11-27 | [X86] vector-interleaved tests - add AVX512F/AVX512DQ/AVX512BW/AVX512DQBW-ONL... | Simon Pilgrim | 1 | -8/+12 |
| 2023-11-27 | [X86] X86DAGToDAGISel - attempt to merge XMM/YMM loads with YMM/ZMM loads of ... | Simon Pilgrim | 1 | -572/+573 |
| 2023-11-23 | Revert rG67275263b3b781a "[X86] X86DAGToDAGISel - attempt to merge XMM/YMM lo... | Simon Pilgrim | 1 | -573/+572 |
| 2023-11-23 | [X86] X86DAGToDAGISel - attempt to merge XMM/YMM loads with YMM/ZMM loads of ... | Simon Pilgrim | 1 | -572/+573 |
| 2023-11-20 | [X86] combineLoad - try to reuse existing constant pool entries for smaller v... | Simon Pilgrim | 1 | -18/+16 |
| 2023-11-18 | Revert rGbfbfd1caa4da "[X86] combineLoad - try to reuse existing constant poo... | Simon Pilgrim | 1 | -16/+18 |
| 2023-11-17 | [X86] combineLoad - try to reuse existing constant pool entries for smaller v... | Simon Pilgrim | 1 | -18/+16 |
| 2023-10-09 | Revert "[CodeGen] Really renumber slot indexes before register allocation (#6... | Jay Foad | 1 | -3458/+3454 |
| 2023-10-09 | [CodeGen] Really renumber slot indexes before register allocation (#67038) | Jay Foad | 1 | -3454/+3458 |
| 2023-09-20 | [X86] combineINSERT_SUBVECTOR - attempt to combine concatenated shuffles | Simon Pilgrim | 1 | -905/+853 |
| 2023-09-20 | [X86] vector-interleaved tests - add AVX512-SLOW/AVX512-FAST common prefixes ... | Simon Pilgrim | 1 | -8/+10 |
| 2023-09-19 | [CodeGen] Renumber slot indexes before register allocation (#66334) | Jay Foad | 1 | -3319/+3300 |
| 2023-06-14 | [X86] X86FixupVectorConstantsPass - attempt to replace full width integer vec... | Simon Pilgrim | 1 | -26/+46 |
| 2023-06-06 | Revert rGab4b924832ce26c21b88d7f82fcf4992ea8906bb - [X86] X86FixupVectorConst... | Simon Pilgrim | 1 | -46/+26 |
| 2023-05-30 | [X86] X86FixupVectorConstantsPass - attempt to replace full width integer vec... | Simon Pilgrim | 1 | -26/+46 |
| 2023-02-13 | Revert rG0b0a38a7a229b70d7261771ba0e702843bd34e97 : "[X86] combineX86Shuffles... | Simon Pilgrim | 1 | -860/+864 |
| 2023-02-11 | [X86] combineX86ShufflesRecursively - don't widen shuffle subvector inputs | Simon Pilgrim | 1 | -864/+860 |
| 2023-02-05 | [X86] combineINSERT_SUBVECTOR - fold (insert_subvector X, (insert_subvector u... | Simon Pilgrim | 1 | -278/+270 |
| 2022-12-13 | [NFC][Codegen][X86] Revisit interleaved store codegen tests | Roman Lebedev | 1 | -973/+5338 |
| 2022-09-30 | X86: Stop assigning register costs for longer encodings. | Matthias Braun | 1 | -1325/+1318 |
| 2022-06-22 | [X86] Migrate tests to use opaque pointers (NFC) | Nikita Popov | 1 | -35/+35 |
| 2022-05-06 | [DAG][PowerPC] Combine shuffle(bitcast(X), Mask) to bitcast(shuffle(X, Mask')) | David Green | 1 | -8/+8 |
| 2022-04-20 | [DAG]Introduce llvm::processShuffleMasks and use it for shuffles in DAG Type ... | Alexey Bataev | 1 | -1976/+1619 |
| 2022-04-20 | Revert "[DAG]Introduce llvm::processShuffleMasks and use it for shuffles in D... | Alexey Bataev | 1 | -1619/+1976 |
| 2022-04-20 | [DAG]Introduce llvm::processShuffleMasks and use it for shuffles in DAG Type ... | Alexey Bataev | 1 | -1976/+1619 |
| 2022-03-04 | [X86] SimplifyDemandedVectorElts - adjust X86ISD::ANDNP demanded elts based o... | Simon Pilgrim | 1 | -3/+3 |
| 2022-02-25 | Revert rG87753cebf5f861eee418d6bce155dfa0b00f9878 "[X86] combineX86ShufflesRe... | Simon Pilgrim | 1 | -3/+3 |
| 2022-02-23 | [X86] combineX86ShufflesRecursively - don't both widening inputs before calli... | Simon Pilgrim | 1 | -3/+3 |
| 2022-02-12 | [X86] combineAndnp - if an input has a zero (after inversion for Op0) in a ve... | Simon Pilgrim | 1 | -6/+6 |
| 2021-12-16 | [X86] combineAnd - don't demand operand vector elements if the other operand ... | Simon Pilgrim | 1 | -1/+1 |
| 2021-10-16 | [NFC][X86][Codegen] Add missing interleaving tests after D111546 | Roman Lebedev | 1 | -0/+1289 |
| 2021-10-03 | [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests | Simon Pilgrim | 1 | -3/+704 |
