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path: root/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
AgeCommit message (Expand)AuthorFilesLines
2025-07-03[PHIElimination] Revert #131837 #146320 #146337 (#146850)Guy David1-17/+16
2025-06-29[PHIElimination] Reuse existing COPY in predecessor basic block (#131837)Guy David1-16/+17
2024-12-07Reland "[ARM] Stop gluing ALU nodes to branches / selects" (#118887)Sergei Barannikov1-64/+59
2024-12-02Revert "[ARM] Stop gluing ALU nodes to branches / selects" (#118232)Martin Storsjö1-59/+64
2024-11-30[ARM] Stop gluing ALU nodes to branches / selects (#116970)Sergei Barannikov1-64/+59
2024-09-05[CodeGen] Add generic INIT_UNDEF pseudo (#106744)Nikita Popov1-5/+5
2024-02-26[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add suppor...Jack Styles1-57/+57
2023-10-24BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreadsMatthias Braun1-59/+60
2023-10-18[ARM] Lower i1 concat via MVETRUNCDavid Green1-333/+226
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-278/+277
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-277/+278
2023-07-14[ARM] Adjust strd/ldrd codegen alignment requirementsMaurice Heumann1-68/+68
2023-07-03Revert "[ARM] Adjust strd/ldrd codegen alignment requirements"David Spickett1-68/+68
2023-07-02[ARM] Adjust strd/ldrd codegen alignment requirementsMaurice Heumann1-68/+68
2022-12-19[Thumb2] Convert some tests to opaque pointers (NFC)Nikita Popov1-813/+747
2022-07-19[ARM] Remove VBICimm if no cleared bits are demandedDavid Green1-4/+1
2022-06-19[DAG] SimplifyDemandedBits - add ISD::VSELECT handlingSimon Pilgrim1-98/+78
2021-12-27[ARM] Extend IsCMPZCSINC to handle CMOVDavid Green1-200/+151
2021-12-03[ARM] Make MVE v2i1 predicates legalDavid Green1-304/+325
2021-11-27[ARM] CSINC/CSINV patterns from CMOVDavid Green1-92/+36
2021-11-04[ARM] Move VPTBlock pass after post-ra schedulingDavid Green1-2/+1
2021-08-17[ARM] Enable subreg livenessDavid Green1-11/+11
2021-06-26[ARM] Introduce MVETRUNC ISel loweringDavid Green1-4/+1
2021-04-20[ARM] Create VMOVRRD from adjacent vector extractsDavid Green1-229/+183
2021-03-29[ARM] Extend MVE lane interleaving to handle other non-instruction leavesDavid Green1-260/+103
2021-02-15[ARM] Extend search for increment in load/store optimizerDavid Green1-12/+6
2021-02-02[ARM] Remove DLS lr, lrDavid Green1-37/+0
2021-01-21[DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (REAPPL...Simon Pilgrim1-2/+0
2021-01-20Revert "[DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE"Hans Wennborg1-0/+2
2021-01-20[DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATESimon Pilgrim1-2/+0
2021-01-18[ARM] Don't handle low overhead branches in AnalyzeBranchDavid Green1-2/+4
2021-01-16[ARM] Add low overhead loops terminators to AnalyzeBranchDavid Green1-4/+2
2020-12-18[ARM] Match dual lane vmovs from insert_vector_eltDavid Green1-303/+267
2020-12-18Revert "[ARM] Match dual lane vmovs from insert_vector_elt"David Green1-259/+295
2020-12-15[ARM] Match dual lane vmovs from insert_vector_eltDavid Green1-295/+259
2020-12-10[ARM][RegAlloc] Add t2LoopEndDecDavid Green1-137/+132
2020-11-10[ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LRDavid Green1-72/+72
2020-11-10[ARM] Alter t2DoLoopStart to define lrDavid Green1-67/+67
2020-10-20Revert "[ARM][LowOverheadLoops] Adjust Start insertion."David Green1-7/+7
2020-10-01[ARM][LowOverheadLoops] Adjust Start insertion.Sam Parker1-7/+7
2020-09-28[ARM] Added more patterns to generate SSAT/USAT with shiftMeera Nakrani1-14/+7
2020-09-22[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being ho...Meera Nakrani1-79/+38
2020-09-14[ARM] Selects SSAT/USAT from correct LLVM IRMeera Nakrani1-9/+3
2020-08-27[ARM] Make MachineVerifier more strict about terminatorsSam Parker1-4/+5
2020-08-17Revert "[BPI] Improve static heuristics for integer comparisons"Dávid Bolvanský1-55/+58
2020-08-13[BPI] Improve static heuristics for integer comparisonsDávid Bolvanský1-58/+55
2020-08-13Revert "[BPI] Improve static heuristics for integer comparisons"Dávid Bolvanský1-55/+58
2020-08-13[BPI] Improve static heuristics for integer comparisonsDávid Bolvanský1-58/+55
2020-08-13Revert "[BPI] Improve static heuristics for integer comparisons"Dávid Bolvanský1-55/+58
2020-08-13[BPI] Improve static heuristics for integer comparisonsDávid Bolvanský1-58/+55
generated by cgit v1.1 at 2025-08-04 23:08:25 +0000