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AgeCommit message (Expand)AuthorFilesLines
4 days[Hexagon] Add post-RA live variables analysis (#179531)Fateme Hosseini5-8/+86
5 days[MachinePipelner] Add loop-carried dependencies for global barriers (#174391)Ryotaro Kasuga1-15/+25
6 days[Hexagon] Fix use-after-poison in balanceSubTree (#179239)Brian Cain1-0/+22
6 days[HEXAGON] Extend/Truncate the shift amount into i32 (#179499)Abinaya Saravanan1-0/+24
7 days[Hexagon] Fix a bug in setcc isnan lit test for f16 (#179338)Fateme Hosseini1-3/+5
11 days[test][Hexagon] Remove unsafe-fp-math uses (NFC) (#164788)paperchalice59-68/+68
12 days[InlineSpiller] Hoist spills only when all of its subranges are available (#1...Min-Yih Hsu1-4/+4
12 daysFix insert DBG_VALUE after terminator Failure for Hexagon (#173401)Fateme Hosseini1-0/+38
2026-01-26[SDAG] Remove non-canonical fabs libcall handling (#177967)Nikita Popov2-5/+5
2026-01-21IR: Remove llvm.convert.to.fp16 and llvm.convert.from.fp16 intrinsics (#174484)Matt Arsenault1-23/+23
2026-01-20[Hexagon[ Optimize HVXVectorCombine:Limit Conversion for Unaligned Loads (#17...Fateme Hosseini7-66/+77
2026-01-20[Hexagon] Don't run hexagon-loop-idiom and hexagon-vlcr passes at O0 pipeline...pkarveti1-0/+11
2026-01-19Hexagon: Use -mtriple instead of -march in a couple tests (#176790)Matt Arsenault2-2/+2
2026-01-19[HexagonConstantPropagation] Use getSigned() (#176715)Nikita Popov1-0/+47
2026-01-15[Hexagon] Enable Machine Combiner pass. (#169434)Sumanth Gundapaneni1-0/+65
2026-01-15[MachinePipeliner] Remove cheap check in dependence analysis (#174390)Ryotaro Kasuga2-13/+16
2026-01-13[Hexagon] Fix PIC crash when lowering HVX vector constants (#175413)Fateme Hosseini1-0/+14
2026-01-06llvm: Convert some assorted lit tests to opaque pointers (#174564)Matt Arsenault7-50/+50
2026-01-05Honor alignment for HVX masked loads/stores (incl. loops) (#174419)Fateme Hosseini2-0/+90
2025-12-22[IR][Verifier] Verification for `target-features` attribute (#173119)Stefan Weigl-Bosker2-2/+2
2025-12-11[Hexagon] Add HVX patterns for vector arithmetic (#170704)Fateme Hosseini1-138/+2
2025-12-11[Hexagon] Fix HWBF16 PatLeaf type (#170560)Fateme Hosseini1-15/+8
2025-12-10Revert "[Hexagon] Passes for widening vector operations and shuffle o… (#17...Brian Cain21-1516/+18
2025-12-04[HEXAGON] [MachinePipeliner] Fix the DAG in case of dependent phis. (#135925)Abinaya Saravanan2-6/+100
2025-12-03[Hexagon] Passes for widening vector operations and shuffle opt (#169559)Fateme Hosseini21-18/+1516
2025-12-03[Hexagon] Add an option to use fast FP to int convert for some HVX cases (#16...Fateme Hosseini1-0/+75
2025-11-24Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...hstk30-hw1-1/+0
2025-11-23Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...Aiden Grossman1-0/+1
2025-11-23[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)hstk30-hw1-1/+0
2025-11-19[Hexagon] Enable soft bf16 in hexagon (#167924)Fateme Hosseini2-0/+302
2025-11-17[MachinePipeliner] Detect a cycle in PHI dependencies early on (#167095)Abinaya Saravanan1-0/+23
2025-11-14[Hexagon] Implement isUsedByReturnOnly (#167637)Sudharsan Veeravalli8-110/+113
2025-11-10Hexagon: Enable terminal rule (#165960)Matt Arsenault11-11/+11
2025-11-10[Hexagon] Clean-up Instrprof test (#166990)Fateme Hosseini1-5/+2
2025-11-10[Hexagon] Implement isMaskAndCmp0FoldingBeneficial (#166891)Sudharsan Veeravalli1-0/+68
2025-11-06[Hexagon] Improve QFP Optimizer (#166647)Fateme Hosseini5-3/+732
2025-11-04[SimplifyCFG] Eliminate dead edges of switches according to the domain of con...Yingwei Zheng1-3/+3
2025-10-31[Hexagon] Optimize sfclass/dfclass compares (#165735)Sumanth Gundapaneni1-0/+86
2025-10-31[Hexagon] Handle truncate of v64i32 -> v64i1 when Hvx is enabled (#164931)pkarveti1-0/+18
2025-10-28Bug fixes for ISelLowering for HVX (#164416)Fateme Hosseini1-0/+94
2025-10-24Add HVX vgather/vscatter Support (#164421)Fateme Hosseini6-0/+309
2025-10-22[CodeGen] Remove `-enable-unsafe-fp-math` option (#164559)paperchalice1-1/+1
2025-10-21[Hexagon] Handle bitcast of i64 -> v64i1 when Hvx is enabled (#163332)pkarveti1-0/+33
2025-10-21[Hexagon] Add REQUIRES: asserts to testNikita Popov1-0/+2
2025-10-20[Hexagon] Incorrect MIR after "hexinsert" pass (#164021)Alexey Karyakin1-0/+45
2025-10-20Hexagon QFP Optimizer (#163843)Fateme Hosseini8-0/+337
2025-10-20[IR] Replace alignment argument with attribute on masked intrinsics (#163802)Nikita Popov1-6/+6
2025-10-16[MachinePipeliner] Add test missed in #154940 (NFC) (#163350)Ryotaro Kasuga1-0/+88
2025-10-09[Hexagon] Use fast-math flags (#162274)paperchalice1-5/+3
2025-10-03[Hexagon] Support lowering of setuo & seto for vector types in Hexagon (#158740)Fateme Hosseini1-0/+93
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