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AgeCommit message (Expand)AuthorFilesLines
2022-11-30[mlgo][nfc] Make `LoggedFeatureSpec` an implementation detailMircea Trofin7-155/+145
2022-11-30[FuzzMutate] New InsertPHINode strategy.Peter Rong2-0/+34
2022-11-30Revert "Use-after-return sanitizer binary metadata"Marco Elver5-123/+11
2022-11-30[AArch64] Make sure we don't emit packed unwind for .seh_save_any_reg_pEli Friedman1-0/+15
2022-11-30[InstSimplify] (X && Y) ? X : Y --> YSanjay Patel1-0/+4
2022-11-30[InstCombine] canonicalize trunc + insert as bitcast + shuffle, part 1 (2nd try)Sanjay Patel1-0/+64
2022-11-30Revert "[InstCombine] canonicalize trunc + insert as bitcast + shuffle, part 1"Sanjay Patel1-64/+0
2022-11-30[RISCV][Codegen] Account for LMUL in Vector floating-point instructionsMichael Maitland3-302/+627
2022-11-30[RISCV] Inline RISCVFrameLowering::adjustReg out of existance [nfc]Philip Reames2-27/+19
2022-11-30[FuncSpec] Invalidate analyses when deleting a fully specialised functionMomchil Velikov2-6/+12
2022-11-30[RISCV] Adjust code to fallthrough to a single adjustReg callsite [nfc]Philip Reames1-6/+8
2022-11-30[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.Craig Topper1-9/+15
2022-11-30[InstCombine] canonicalize trunc + insert as bitcast + shuffle, part 1Sanjay Patel1-0/+64
2022-11-30[RISCV] Merge two versions of adjustReg on TRI [nfc]Philip Reames3-65/+46
2022-11-30[AMDGPU] Use s_cmp instead of s_cmpkJay Foad1-1/+1
2022-11-30[RISCV] Reuse and generalize adjustReg from another spot in frame lowering [nfc]Philip Reames3-27/+22
2022-11-30[RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer con...Philip Reames3-23/+13
2022-11-30Recommit "[VPlan] Add VPDerivedIVRecipe, use for VPScalarIVStepsRecipe."Florian Hahn6-65/+163
2022-11-30[AIX][LTO] Enabling Context Sensitive PGO OptionsQiongsi Wu1-1/+12
2022-11-30[RISCV][TTI] Account for constant materialization cost when costing arithmeti...Philip Reames3-40/+74
2022-11-30ConstantFolding: Guard use of getFunctionDavid Stuttard1-1/+1
2022-11-30Use-after-return sanitizer binary metadataDmitry Vyukov5-11/+123
2022-11-30[AArch64] Assembly support for VMSATomas Matheson10-5/+666
2022-11-30[AMDGPU] Remove todo about vector typesSebastian Neubauer1-2/+0
2022-11-30[AArch64] Don't treat SVE scalable extends as free widening instructionsDavid Green1-2/+5
2022-11-30 [RISCV] Add cost model for fixed broadcast shuffleShihPo Hung2-0/+63
2022-11-30[X86] Add missing PFM port mappings for Core2/NehalemSimon Pilgrim1-5/+29
2022-11-30[CodeGen][X86] Crash fixes for "patchable-function" passSylvain Audi2-26/+31
2022-11-30[AMDGPU] Use aperture registers instead of S_GETREGPierre van Houtryve3-45/+44
2022-11-30[AMDGPU][MC][GFX11] Disable non-VGPR src operands for VOP3_DPP variants of fm...Dmitry Preobrazhensky1-2/+2
2022-11-30X86: relax EFLAGS liveness check when generating stack probes.Tim Northover1-3/+6
2022-11-30[AMDGPU] Fix location of line break in VOPC instruction tableJay Foad1-1/+1
2022-11-30AMDGPU: Fixup testsNicolai Hähnle1-9/+0
2022-11-30AMDGPU: Remove ImagePSV and move images to addrspace 7Nicolai Hähnle4-30/+5
2022-11-30[LoongArch] Add codegen support for atomicrmw min/max operation on LA64gonglingqin3-2/+89
2022-11-30Revert "Use-after-return sanitizer binary metadata"Dmitry Vyukov5-123/+11
2022-11-30[RISCV] Remove lmuls argument in Sched classwangpc1-60/+89
2022-11-30Use-after-return sanitizer binary metadataDmitry Vyukov5-11/+123
2022-11-30[AMDGPU] Remove AMDGPUISelDAGToDAG::isKnownNeverNaNThomas Symalla2-13/+1
2022-11-29[IR][NFC] Adds Instruction::insertAt() for inserting at a specific point in t...Vasileios Porpodas1-0/+7
2022-11-30[InstSimplify] Fold (X || Y) ? X : Y --> Xchenglin.bi1-0/+4
2022-11-29[RISCV] Preserve chain output when selecting splat as x0 strided load.Craig Topper1-3/+5
2022-11-29[NFC] Removed call to getInstList() from range loops on BBs.Vasileios Porpodas5-10/+10
2022-11-29[RISCV][CodeGen] Account for LMUL for Vector Fixed-Point Arithmetic InstructionsMichael Maitland3-91/+157
2022-11-29[FuzzMutate] SinkInstructionStrategyPeter Rong1-0/+23
2022-11-29AMDGPU: Fix creating illegal f16 fp_classMatt Arsenault1-3/+4
2022-11-30[Hexagon] Fix unused variable warning in Release builds. NFCBenjamin Kramer1-2/+1
2022-11-29[Hexagon] Further improve code generation for shufflesKrzysztof Parzyszek5-188/+578
2022-11-29[AIX][LTO] Properly respect LDR_CNTRL and set MAXDATA32 to 0xA0000000@DSA.Wael Yehia1-1/+6
2022-11-29[InstCombine] Revert D125845William Huang1-40/+6
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