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| author | Dmitry Preobrazhensky <dmitri.preobrazhenski@gmail.com> | 2022-11-30 14:45:52 +0300 |
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| committer | Dmitry Preobrazhensky <dmitri.preobrazhenski@gmail.com> | 2022-11-30 14:48:00 +0300 |
| commit | f2d589ea46d8907a161f864ad506bb1bb67bfb26 (patch) | |
| tree | f763074c2bc87121872cbea1196712e0629706e5 /llvm/lib | |
| parent | b32280baf9ef46cc0c9f1c700af4fd5c4e1e9acb (diff) | |
| download | llvm-f2d589ea46d8907a161f864ad506bb1bb67bfb26.zip llvm-f2d589ea46d8907a161f864ad506bb1bb67bfb26.tar.gz llvm-f2d589ea46d8907a161f864ad506bb1bb67bfb26.tar.bz2 | |
[AMDGPU][MC][GFX11] Disable non-VGPR src operands for VOP3_DPP variants of fmac instructions
Differential Revision: https://reviews.llvm.org/D138710
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index 4eb0f5e..1ba50d9 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -424,9 +424,9 @@ class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, v dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); let InsDPP16 = !con(InsDPP, (ins FI:$fi)); - let InsVOP3Base = getIns64<Src0VOP3DPP, Src1RC64, RegisterOperand<VGPR_32>, 3, + let InsVOP3Base = getIns64<Src0VOP3DPP, Src1VOP3DPP, RegisterOperand<VGPR_32>, 3, 0, HasModifiers, HasModifiers, HasOMod, - Src0Mod, Src1Mod, Src2Mod>.ret; + Src0ModVOP3DPP, Src1ModVOP3DPP, Src2Mod>.ret; // We need a dummy src2 tied to dst to track the use of that register for s_delay_alu let InsVOPDX = (ins Src0RC32:$src0X, Src1RC32:$vsrc1X, VGPRSrc_32:$src2X); let InsVOPDXDeferred = |