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2024-06-22[X86][MC] Drop optional from LowerMachineOperand (#96338)Alexis Engelke1-21/+22
2024-06-21[MC] emitLabelAtPos: change parameter to MCDataFragment &. NFCFangrui Song1-6/+5
2024-06-21[ARM] Simplify ElfMappingSymbolInfo. NFCFangrui Song1-9/+5
2024-06-22AMDGPU: Materialize bitwise not of inline immediates (#95960)Matt Arsenault1-17/+41
2024-06-21AMDGPU: Start fixing inconsistencies in usage of SubtargetPredicate (#96337)Matt Arsenault1-37/+29
2024-06-21AMDGPU: Fix overriding SubtargetPredicate in MUBUF_Real_gfx90a (#96351)Matt Arsenault1-3/+3
2024-06-21[AMDGPU][GFX12] Add support for new block ls instructions (#96273)Mariusz Sikora3-1/+17
2024-06-21[AArch64] AArch64AsmParser::tryParseImmRange - don't directly dereference poi...Simon Pilgrim1-2/+2
2024-06-21[AArch64] Use ccmn to compare negative immediates between -1 and -31 (#95825)AtariDreams2-3/+12
2024-06-21[X86] SimplifyDemandedVectorEltsForTargetNode - add X86ISD::VPMADDUBSW handlingSimon Pilgrim1-0/+1
2024-06-21[X86] combineConcatVectorOps - add pmaddwd/pmaddubsw handlingSimon Pilgrim1-0/+2
2024-06-21AMDGPU: Legalize v2f16 atomicrmw fadd for buffer fat pointers (#95929)Matt Arsenault1-3/+9
2024-06-21[AArch64] NFCI: More sensible implementation of isLegalMaskedGatherScatter.Sander de Smalen1-1/+1
2024-06-21[AArch64][GlobalISel] Add fp128 and i128 fptosi/fptoui handling. (#95528)David Green1-10/+28
2024-06-21[RISCV] Add Syntacore SCR3 processor definition (#95953)Anton Sidorenko1-0/+21
2024-06-21[AArch64] Fix || Add brackets for || inside of assertDavid Green1-2/+2
2024-06-21[AArch64] Use AArch64ISD::UADDLP over aarch64_neon_uaddlp. NFCDavid Green1-3/+1
2024-06-21[NFC] Fix laod -> load typos. NFCDavid Green1-1/+1
2024-06-21Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"Nikita Popov13-86/+11
2024-06-21Intrinsic: introduce minimumnum and maximumnum (#93841)YunQiang Su13-11/+86
2024-06-21[RISCV] Make M imply Zmmul (#95070)Jianjian Guan6-30/+27
2024-06-20[PowerPC] use r1 as the frame pointer when there is dynamic allocaChen Zheng1-1/+4
2024-06-20[AMDGPU] Introduce a pseudo mnemonic for S_DELAY_ALU in MIR. (#96004)Michael Bedy2-0/+174
2024-06-20[AArch64] Consider runtime mode when deciding to use SVE for fixed-length vec...Sander de Smalen3-35/+50
2024-06-20[llvm][AArch64] SVE2 is an optional feature in ARMv9.0a (#96007)Jon Roelofs2-13/+25
2024-06-20[PPC] Add DwarfRegAlias for VSRPair (#95837)Zaara Syeda1-1/+1
2024-06-20[RISCV][NFC] Cleanup SCR1 sched model (#96088)Anton Sidorenko1-2/+0
2024-06-20[RISCV] Strength reduce mul by 2^N - 2^M (#88983)Philip Reames1-91/+107
2024-06-20[SPIRV] Add trig function lowering (#95973)Farzon Lotfi2-0/+18
2024-06-20[AArch64][TargetParser] Split FMV and extensions (#92882)Tomas Matheson3-159/+147
2024-06-20[X86][CodeGen] Not emit mr_ND if rr_ND is commutableShengchen Kan1-16/+30
2024-06-20[AMDGPU] Preserve chain when selecting llvm.amdgcn.pops.exiting.wave.id (#96167)Jay Foad1-1/+2
2024-06-20[MC] Eliminate two symbol-related hash maps (#95464)aengelke1-2/+2
2024-06-20[X86] Fix indention in X86InstrArithmetic.td, NFCIShengchen Kan1-199/+187
2024-06-20[ARM] CMSE security mitigation on function arguments and returned values (#89...Lucas Duarte Prates2-15/+33
2024-06-20[MC] Remove SectionKind from MCSection (#96067)aengelke5-11/+11
2024-06-20[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets (#93...Roger Ferrer Ibáñez2-0/+28
2024-06-20[PowerPC] Make verifier happy after peephole on MMA COPYs (#94321)Kai Luo1-0/+3
2024-06-19[PowerPC] Remove extraneous ArrayRef (NFC) (#96092)Kazu Hirata1-6/+6
2024-06-19[DirectX] Add trig intrinsics and link them with DXIL backend (#95968)Farzon Lotfi1-0/+19
2024-06-19[InstCombine] Swap out range metadata to range attribute for arm_mve_pred_v2i...Andreas Jonson1-10/+14
2024-06-19[AVR] Let ArrayRef infer the array size (NFC) (#96076)Kazu Hirata1-4/+4
2024-06-19[NFC][SPARC] Fix typos and style mismatchesKoakuma1-1/+1
2024-06-19[GISel][RISCV]Implement indirect parameter passing (#95429)Gábor Spaits1-3/+1
2024-06-19[AMDGPU] Add IsSingle to a few Interp instructions (#95984)Joe Nash1-1/+1
2024-06-19[AMDGPU] Add IsSingle to V_DIV_FMAS* for consistency. (#95983)Joe Nash1-0/+2
2024-06-19[AArch64] Avoid using NEON BSL for streaming[-compatible] functions (#95803)Sander de Smalen1-3/+5
2024-06-19[AArch64] Let patterns for NEON instructions check runtime mode. (#95560)Sander de Smalen4-33/+32
2024-06-19[RISCV] Move RISCVInsertVSETVLI::coalesceVSETVLIs back to before insertReadVL...Luke Lau1-5/+5
2024-06-19[X86] computeKnownBitsForPMADDWD/PMADDUBSW - tidyup line overflow by moving e...Simon Pilgrim1-21/+13
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