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| author | Zaara Syeda <syzaara@ca.ibm.com> | 2024-06-20 11:30:58 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-20 11:30:58 -0400 |
| commit | 898b8a42b5fde2738da46ec9f5b427693bc681a1 (patch) | |
| tree | 50abea2b40fb589a6dc24883d22b08d6d39a8960 /llvm/lib/Target | |
| parent | bed2eb64de05d0e1f5a8494e8c0f44b24d41dd18 (diff) | |
| download | llvm-898b8a42b5fde2738da46ec9f5b427693bc681a1.zip llvm-898b8a42b5fde2738da46ec9f5b427693bc681a1.tar.gz llvm-898b8a42b5fde2738da46ec9f5b427693bc681a1.tar.bz2 | |
[PPC] Add DwarfRegAlias for VSRPair (#95837)
Add DwarfRegAlias for VSRPair as it shares dwarfRegNum with the VR
registers.
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 8a37e40..fdbdc14 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -199,7 +199,7 @@ let SubRegIndices = [sub_vsx0, sub_vsx1] in { def VSRp#!add(!srl(Index, 1), 16) : VSRPair<!add(!srl(Index, 1), 16), "vsp"#!add(Index, 32), [!cast<VR>("V"#Index), !cast<VR>("V"#!add(Index, 1))]>, - DwarfRegNum<[-1, -1]>; + DwarfRegAlias<!cast<VR>("V"#Index)>; } } |