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path: root/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
AgeCommit message (Expand)AuthorFilesLines
9 days[SelectionDAG] Pass SDNodeFlags through getNode instead of setFlags. (#149852)Craig Topper1-5/+4
2025-06-20[LLVM][CodeGen][SVE] Add isel for bfloat unordered reductions. (#143540)Paul Walker1-9/+36
2025-06-09[SDAG] Add partial_reduce_sumla node (#141267)Philip Reames1-0/+2
2025-05-29[SDAG] Split the partial reduce legalize table by opcode [nfc] (#141970)Philip Reames1-2/+3
2025-05-08[DAG/RISCV] Continue mitgrating to getInsertSubvector and getExtractSubvectorPhilip Reames1-4/+2
2025-04-23[AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (#130933)Nicholas Guy1-2/+5
2025-02-28[SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (#128800)Jim Lin1-1/+7
2025-02-18[SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (#125207)James Chesterman1-0/+6
2025-02-11[RTLIB] Rename getFSINCOS() to getSINCOS (NFC) (#126705)Benjamin Maxwell1-1/+1
2025-02-11[IR] Add llvm.sincospi intrinsic (#125873)Benjamin Maxwell1-3/+7
2025-02-07[IR] Add `llvm.modf` intrinsic (#121948)Benjamin Maxwell1-0/+9
2025-01-20[SDAG] Add an ISD node to help lower vector.extract.last.active (#118810)Graham Hunter1-0/+4
2025-01-13[LegalizeVectorOps][RISCV] Use VP_FP_EXTEND/ROUND when promoting VP_FP* opera...Craig Topper1-3/+20
2025-01-08[X86] Combine `uitofp <v x i32> to <v x half>` (#121809)abhishek-kaushik221-0/+25
2025-01-06[DAG] VectorLegalizer::ExpandUINT_TO_FLOAT- pull out repeated getValueType ca...Simon Pilgrim1-23/+19
2025-01-06[X86] Support lowering of FMINIMUMNUM/FMAXIMUMNUM (#121464)Phoebe Wang1-0/+6
2025-01-03[LegalizeVectorOps] Use getBoolConstant instead of getAllOnesConstant in Vect...Craig Topper1-1/+3
2024-11-06[SDAG] Merge multiple-result libcall expansion into DAG.expandMultipleResultF...Benjamin Maxwell1-3/+5
2024-10-31[SDAG] Support expanding `FSINCOS` to vector library calls (#114039)Benjamin Maxwell1-0/+5
2024-10-31[SDAG] Simplify `SDNodeFlags` with bitwise logic (#114061)Yingwei Zheng1-9/+3
2024-10-29[IR] Add `llvm.sincos` intrinsic (#109825)Benjamin Maxwell1-0/+1
2024-10-16[X86][CodeGen] Add base atan2 intrinsic lowering (p4) (#110760)Tex Riddell1-0/+1
2024-10-07[LLVM][CodeGen] Add lowering for scalable vector bfloat operations. (#109803)Paul Walker1-0/+23
2024-09-30[LegalizeVectorOps] Enable ExpandFABS/COPYSIGN to use integer ops for fixed v...Craig Topper1-6/+17
2024-09-18[LegalizeVectorOps][RISCV] Don't scalarize FNEG in ExpandFNEG if FSUB is mark...Craig Topper1-1/+1
2024-09-17Revert "[LegalizeVectorOps] Make the AArch64 hack in ExpandFNEG more specific."Craig Topper1-7/+3
2024-09-17[LegalizeVectorOps] Remove calls to DAG.UnrollVectorsOps from some expansion ...Craig Topper1-45/+56
2024-09-16[LegalizeVectorOps] Make the AArch64 hack in ExpandFNEG more specific.Craig Topper1-3/+7
2024-09-03[LegalizeDAG][RISCV] Don't promote f16 vector ISD::FNEG/FABS/FCOPYSIGN to f32...Craig Topper1-1/+62
2024-09-02[LegalizeVectorOps] Defer UnrollVectorOp in ExpandFNEG to caller. (#106783)Craig Topper1-12/+15
2024-09-01[SDAG] Expand vector [u|s]cmp in VectorLegalizer (#106883)Yingwei Zheng1-0/+4
2024-08-30[LegalizeVectorOps][RISCV] Don't promote VP_FABS/FNEG/FCOPYSIGN. (#106659)Craig Topper1-0/+100
2024-08-29[LegalizeVectorOps][PowerPC] Use xor to expand fneg. (#106595)Craig Topper1-5/+11
2024-08-21Scalarize the vector inputs to llvm.lround intrinsic by default. (#101054)Sumanth Gundapaneni1-0/+2
2024-07-17[LLVM] Add `llvm.experimental.vector.compress` intrinsic (#92289)Lawrence Benson1-0/+4
2024-07-11[X86][CodeGen] Add base trig intrinsic lowerings (#96222)Farzon Lotfi1-0/+6
2024-06-21Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"Nikita Popov1-10/+0
2024-06-21Intrinsic: introduce minimumnum and maximumnum (#93841)YunQiang Su1-0/+10
2024-06-17[SelectionDAG] Add support for the 3-way comparison intrinsics [US]CMP (#91871)Poseydon421-0/+2
2024-06-12[DAG] Add legalization handling for AVGCEIL/AVGFLOOR nodes (#92096)Simon Pilgrim1-0/+13
2024-06-06DAG: Improve fminimum/fmaximum vector expansion logic (#93579)Matt Arsenault1-5/+2
2024-06-05[LegalizeVectorOps] Move VP_STORE legalization from LegalizeDAG to LegalizeVe...Craig Topper1-1/+2
2024-06-05[x86] Add tan intrinsic part 4 (#90503)Farzon Lotfi1-0/+1
2024-05-15[LegalizeVectorOps][X86] Add ISD::ABDS/ABSDU to the list of opcodes handled b...Craig Topper1-0/+2
2024-04-29[SelectionDAG][RISCV] Move VP_REDUCE* legalization to LegalizeDAG.cpp. (#90522)Craig Topper1-68/+5
2024-04-29[Legalizer] Expand fmaximum and fminimum (#67301)Qiu Chaofan1-0/+7
2024-04-24AMDGPU: Fix vector handling of fptrunc_roundMatt Arsenault1-0/+1
2024-04-16[AMDGPU] In VectorLegalizer::Expand, if UnrollVectorOp returns Load, … (#88...choikwa1-2/+8
2024-03-08[LLVM][CodeGen] Teach SelectionDAG how to expand FREM to a vector math call. ...Paul Walker1-0/+128
2024-02-22[SelectionDAG][RISCV] Use FP type for legality query for LRINT/LLRINT in Lega...Craig Topper1-2/+2
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