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path: root/llvm/lib/Analysis/TargetTransformInfo.cpp
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47 hours[VectorCombine][TTI] Prevent extract/ins rewrite to GEP (#150216)Nathan Gauër1-0/+4
10 days[NFC][Clang][FMV] Make FMV priority data type future proof. (#150079)Alexandros Lamprineas1-1/+1
2025-07-08[EarlyCSE,TTI] Don't create new, unused, instructions. (#134534)Florian Hahn1-2/+3
2025-06-21[CostModel] Add a DstTy to getShuffleCost (#141634)David Green1-3/+8
2025-06-19[TTI] Plumb CostKind through getPartialReductionCost (#144953)Philip Reames1-2/+3
2025-06-18[TTI] Remove PPC hasActiveVectorLength impl, simplify interface (NFC). (#142310)Florian Hahn1-3/+2
2025-05-29[Constant] Make Constant::getSplatValue return poison on poison (#141870)Luke Lau1-0/+4
2025-05-12[TTI][LV] Simplify the prototype of preferPredicatedReductionSelect. nfc (#13...Mel Chen1-3/+2
2025-05-01[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)David Green1-1/+1
2025-04-30[SLPVectorizer] Move X86 specific handling into X86TTIImpl. (#137830)Jonas Paulsson1-2/+3
2025-04-26[TTI] Simplify implementation (NFCI) (#136674)Sergei Barannikov1-2/+6
2025-04-22[CostModel] Plumb CostKind into getExtractWithExtendCost (#135523)David Green1-2/+3
2025-04-21[LLVM] Cleanup pass initialization for Analysis passes (#135858)Rahul Joshi1-8/+2
2025-04-07[TTI][LV] Change the prototype of preferInLoopReduction. nfc (#132698)Mel Chen1-2/+2
2025-04-02[TTI] Make isLegalMasked{Load,Store} take an address space (#134006)Krzysztof Drewniak1-6/+6
2025-03-21[llvm:ir] Add support for constant data exceeding 4GiB (#126481)pzzp1-1/+1
2025-03-20[X86][NFCI] Add IsStore parameter to hasConditionalLoadStoreForType (#132153)Phoebe Wang1-2/+3
2025-03-19[TTI] Align optional FMFs in getExtendedReductionCost() to getArithmeticReduc...Elvis Wang1-1/+1
2025-03-12[SLP]Reduce number of alternate instruction, where possibleAlexey Bataev1-0/+4
2025-03-12Revert "[SLP]Reduce number of alternate instruction, where possible"Hans Wennborg1-4/+0
2025-03-11[SLP]Reduce number of alternate instruction, where possibleAlexey Bataev1-0/+4
2025-03-11Revert "[SLP]Reduce number of alternate instruction, where possible"Hans Wennborg1-4/+0
2025-03-10[SLP]Reduce number of alternate instruction, where possibleAlexey Bataev1-0/+4
2025-03-05[LV][TTI] Remove unused ReductionFlags. NFC (#129858)Luke Lau1-6/+6
2025-03-04[TTI] Assert that TargetIRAnalyis is not requested for intrinsicsAlexander Richardson1-0/+1
2025-02-26[CostModel] Handle vector struct results and cost `llvm.sincos` (#123210)Benjamin Maxwell1-9/+8
2025-02-21[TTI][AArch64] Detect OperandInfo from scalable splats. (#122469)David Green1-21/+22
2025-02-17[LV] Add initial support for vectorizing literal struct return values (#109833)Benjamin Maxwell1-0/+10
2025-02-04[TTI][CostModel] Add cost modeling for expandload and compressstore intrinsic...Sergey Kachkov1-0/+9
2025-02-02Revert "[SLP]Reduce number of alternate instruction, where possible"Martin Storsjö1-4/+0
2025-02-01[SLP]Reduce number of alternate instruction, where possibleAlexey Bataev1-0/+4
2025-01-29[KernelInfo] Implement new LLVM IR pass for GPU code analysis (#102944)Joel E. Denny1-0/+6
2025-01-17[FMV][GlobalOpt] Statically resolve calls to versioned functions. (#87939)Alexandros Lamprineas1-0/+8
2025-01-13Reland "[LoopVectorizer] Add support for partial reductions" with non-phi ope...Sam Tebbs1-0/+18
2024-12-27Revert "Reland "[LoopVectorizer] Add support for partial reductions" (#120721)"Zequan Wu1-17/+0
2024-12-24Reland "[LoopVectorizer] Add support for partial reductions" (#120721)Sam Tebbs1-0/+17
2024-12-19Revert "[LoopVectorizer] Add support for partial reductions (#92418)"Florian Hahn1-17/+0
2024-12-19[NFC][TargetTransformInfo][VectorUtils] Consolidate `isVectorIntrinsic...` ap...Finn Plummer1-3/+8
2024-12-19[LoopVectorizer] Add support for partial reductions (#92418)Nicholas Guy1-0/+17
2024-11-29[SLPVectorizer, TargetTransformInfo, SystemZ] Improve SLP getGatherCost(). (...Jonas Paulsson1-2/+2
2024-11-21[NFC][VectorUtils][TargetTransformInfo] Add `isVectorIntrinsicWithOverloadTyp...Finn Plummer1-0/+5
2024-11-20[AArch64][LV] Set MaxInterleaving to 4 for Neoverse V2 and V3 (#100385)Sjoerd Meijer1-0/+4
2024-11-13[CostModel][AArch64] Make extractelement, with fmul user, free whenev… (#11...Sushant Gokhale1-3/+16
2024-11-05[Analysis] Remove unused includes (NFC) (#114936)Kazu Hirata1-1/+0
2024-10-24Recommit: [llvm][ARM][GlobalOpt]Add widen global arrays pass (#113289)Nashe Mncube1-0/+6
2024-10-17Revert "[llvm][ARM]Add widen global arrays pass" (#112701)Nashe Mncube1-6/+0
2024-10-17[llvm][ARM]Add widen global arrays pass (#107120)Nashe Mncube1-0/+6
2024-10-14[SLP]Initial support for interleaved loadsAlexey Bataev1-0/+7
2024-10-12[LLVM] New NoDivergenceSource function attribute (#111832)Tim Renouf1-0/+4
2024-10-11[TTI][AMDGPU] Allow targets to adjust `LastCallToStaticBonus` via `getInlinin...Shilei Tian1-0/+4