diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/shl.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/shl.ll | 59 |
1 files changed, 46 insertions, 13 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/shl.ll b/llvm/test/CodeGen/AMDGPU/shl.ll index 7aa7342..28330bf 100644 --- a/llvm/test/CodeGen/AMDGPU/shl.ll +++ b/llvm/test/CodeGen/AMDGPU/shl.ll @@ -681,30 +681,63 @@ define amdgpu_kernel void @shl_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in ; ; EG-LABEL: shl_v4i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 3, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T8.X, 1 +; EG-NEXT: ALU 42, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T0.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_128 T8.XYZW, T0.X, 0, #1 +; EG-NEXT: VTX_READ_128 T10.XYZW, T0.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: LSHL * T0.W, T0.X, literal.x, +; EG-NEXT: MOV T0.Y, T6.X, +; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, -; EG-NEXT: ALU clause starting at 11: -; EG-NEXT: LSHR T1.W, T8.Z, literal.x, -; EG-NEXT: LSHR * T2.W, T8.X, literal.x, +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: AND_INT * T1.W, T10.Z, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T1.W, T10.X, PV.W, +; EG-NEXT: AND_INT T1.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T2.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T1.W, PS, PV.W, +; EG-NEXT: MOV * T6.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: LSHR T1.W, T10.Z, literal.x, +; EG-NEXT: LSHR * T2.W, T10.X, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: LSHL T0.Y, PS, PV.W, -; EG-NEXT: AND_INT T1.W, T8.Z, literal.x, -; EG-NEXT: AND_INT * T2.W, T8.X, literal.x, +; EG-NEXT: LSHL T1.W, PS, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.X, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: LSHL T0.X, PS, PV.W, +; EG-NEXT: LSHL * T1.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, +; EG-NEXT: MOV T6.X, PV.W, +; EG-NEXT: MOV * T0.X, T7.X, +; EG-NEXT: AND_INT * T1.W, T10.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL T1.W, T10.Y, PV.W, +; EG-NEXT: AND_INT * T2.W, T0.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: AND_INT * T1.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, +; EG-NEXT: MOV * T7.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: LSHR T1.W, T10.W, literal.x, +; EG-NEXT: LSHR * T2.W, T10.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHL * T1.W, PS, PV.W, +; EG-NEXT: AND_INT T0.Z, T0.X, literal.x, +; EG-NEXT: LSHL T1.W, PV.W, literal.y, ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W, -; EG-NEXT: LSHR * T8.X, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: LSHR T0.X, PS, literal.x, +; EG-NEXT: OR_INT * T10.Y, PV.Z, PV.W, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T7.X, PV.Y, +; EG-NEXT: MOV * T10.X, T6.X, %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep = getelementptr inbounds <4 x i16>, ptr addrspace(1) %in, i32 %tid %gep.out = getelementptr inbounds <4 x i16>, ptr addrspace(1) %out, i32 %tid |