diff options
273 files changed, 13917 insertions, 3276 deletions
diff --git a/clang-tools-extra/clang-include-fixer/IncludeFixer.cpp b/clang-tools-extra/clang-include-fixer/IncludeFixer.cpp index 7b0e4ec..30bb313 100644 --- a/clang-tools-extra/clang-include-fixer/IncludeFixer.cpp +++ b/clang-tools-extra/clang-include-fixer/IncludeFixer.cpp @@ -53,7 +53,7 @@ public: Compiler->createSema(getTranslationUnitKind(), CompletionConsumer); SemaSource->setCompilerInstance(Compiler); - Compiler->getSema().addExternalSource(SemaSource.get()); + Compiler->getSema().addExternalSource(SemaSource); clang::ParseAST(Compiler->getSema(), Compiler->getFrontendOpts().ShowStats, Compiler->getFrontendOpts().SkipFunctionBodies); diff --git a/clang-tools-extra/clang-tidy/.clang-tidy b/clang-tools-extra/clang-tidy/.clang-tidy index 0a2ea24..22a4bd7 100644 --- a/clang-tools-extra/clang-tidy/.clang-tidy +++ b/clang-tools-extra/clang-tidy/.clang-tidy @@ -16,7 +16,6 @@ Checks: > -modernize-use-trailing-return-type, performance-*, -performance-enum-size, - -performance-move-const-arg, -performance-no-int-to-ptr, -performance-type-promotion-in-math-fn, -performance-unnecessary-value-param, @@ -38,3 +37,7 @@ Checks: > -readability-static-definition-in-anonymous-namespace, -readability-suspicious-call-argument, -readability-use-anyofallof + +CheckOptions: + - key: performance-move-const-arg.CheckTriviallyCopyableMove + value: false diff --git a/clang-tools-extra/clang-tidy/bugprone/InvalidEnumDefaultInitializationCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/InvalidEnumDefaultInitializationCheck.cpp index 33fcf45..f903e63 100644 --- a/clang-tools-extra/clang-tidy/bugprone/InvalidEnumDefaultInitializationCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/InvalidEnumDefaultInitializationCheck.cpp @@ -22,11 +22,10 @@ bool isCompleteAndHasNoZeroValue(const EnumDecl *D) { const EnumDecl *Definition = D->getDefinition(); return Definition && Definition->isComplete() && !Definition->enumerators().empty() && - std::none_of(Definition->enumerator_begin(), - Definition->enumerator_end(), - [](const EnumConstantDecl *Value) { - return Value->getInitVal().isZero(); - }); + llvm::none_of(Definition->enumerators(), + [](const EnumConstantDecl *Value) { + return Value->getInitVal().isZero(); + }); } AST_MATCHER(EnumDecl, isCompleteAndHasNoZeroValue) { diff --git a/clang-tools-extra/clang-tidy/bugprone/NonZeroEnumToBoolConversionCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/NonZeroEnumToBoolConversionCheck.cpp index e032384..e0b0df9 100644 --- a/clang-tools-extra/clang-tidy/bugprone/NonZeroEnumToBoolConversionCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/NonZeroEnumToBoolConversionCheck.cpp @@ -22,11 +22,10 @@ namespace { AST_MATCHER(EnumDecl, isCompleteAndHasNoZeroValue) { const EnumDecl *Definition = Node.getDefinition(); return Definition && Node.isComplete() && - std::none_of(Definition->enumerator_begin(), - Definition->enumerator_end(), - [](const EnumConstantDecl *Value) { - return Value->getInitVal().isZero(); - }); + llvm::none_of(Definition->enumerators(), + [](const EnumConstantDecl *Value) { + return Value->getInitVal().isZero(); + }); } } // namespace diff --git a/clang-tools-extra/clang-tidy/bugprone/TaggedUnionMemberCountCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/TaggedUnionMemberCountCheck.cpp index c1ea63c..ddbb14e 100644 --- a/clang-tools-extra/clang-tidy/bugprone/TaggedUnionMemberCountCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/TaggedUnionMemberCountCheck.cpp @@ -105,11 +105,15 @@ void TaggedUnionMemberCountCheck::storeOptions( void TaggedUnionMemberCountCheck::registerMatchers(MatchFinder *Finder) { - auto UnionField = fieldDecl(hasType(qualType( - hasCanonicalType(recordType(hasDeclaration(recordDecl(isUnion()))))))); + auto NotFromSystemHeaderOrStdNamespace = + unless(anyOf(isExpansionInSystemHeader(), isInStdNamespace())); - auto EnumField = fieldDecl(hasType( - qualType(hasCanonicalType(enumType(hasDeclaration(enumDecl())))))); + auto UnionField = + fieldDecl(hasType(qualType(hasCanonicalType(recordType(hasDeclaration( + recordDecl(isUnion(), NotFromSystemHeaderOrStdNamespace))))))); + + auto EnumField = fieldDecl(hasType(qualType(hasCanonicalType( + enumType(hasDeclaration(enumDecl(NotFromSystemHeaderOrStdNamespace))))))); auto HasOneUnionField = fieldCountOfKindIsOne(UnionField, UnionMatchBindName); auto HasOneEnumField = fieldCountOfKindIsOne(EnumField, TagMatchBindName); diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp index 82fd331..82d1cf1 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp @@ -132,8 +132,7 @@ void MissingStdForwardCheck::registerMatchers(MatchFinder *Finder) { hasAncestor(functionDecl().bind("func")), hasAncestor(functionDecl( isDefinition(), equalsBoundNode("func"), ToParam, - unless(anyOf(isDeleted(), - hasDescendant(std::move(ForwardCallMatcher))))))), + unless(anyOf(isDeleted(), hasDescendant(ForwardCallMatcher)))))), this); } diff --git a/clang-tools-extra/clang-tidy/modernize/AvoidCArraysCheck.cpp b/clang-tools-extra/clang-tidy/modernize/AvoidCArraysCheck.cpp index 0804aa7..ee70911 100644 --- a/clang-tools-extra/clang-tidy/modernize/AvoidCArraysCheck.cpp +++ b/clang-tools-extra/clang-tidy/modernize/AvoidCArraysCheck.cpp @@ -67,7 +67,7 @@ void AvoidCArraysCheck::registerMatchers(MatchFinder *Finder) { hasParent(fieldDecl( hasParent(recordDecl(isExternCContext())))), hasAncestor(functionDecl(isExternC())))), - std::move(IgnoreStringArrayIfNeededMatcher)) + IgnoreStringArrayIfNeededMatcher) .bind("typeloc"), this); } diff --git a/clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.cpp b/clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.cpp index ff5a302..934cc24 100644 --- a/clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.cpp +++ b/clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.cpp @@ -319,7 +319,7 @@ void UseStdNumbersCheck::registerMatchers(MatchFinder *const Finder) { Finder->addMatcher( expr( - anyOfExhaustive(std::move(ConstantMatchers)), + anyOfExhaustive(ConstantMatchers), unless(hasParent(explicitCastExpr(hasDestinationType(isFloating())))), hasType(qualType(hasCanonicalTypeUnqualified( anyOf(qualType(asString("float")).bind("float"), diff --git a/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py b/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py index a3dca6c..d307b26 100755 --- a/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py +++ b/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py @@ -49,7 +49,7 @@ import tempfile import time import traceback from types import ModuleType -from typing import Any, Awaitable, Callable, List, Optional, TypeVar +from typing import Any, Awaitable, Callable, Dict, List, Optional, Tuple, TypeVar yaml: Optional[ModuleType] = None @@ -105,6 +105,7 @@ def get_tidy_invocation( warnings_as_errors: Optional[str], exclude_header_filter: Optional[str], allow_no_checks: bool, + store_check_profile: Optional[str], ) -> List[str]: """Gets a command line for clang-tidy.""" start = [clang_tidy_binary] @@ -147,6 +148,9 @@ def get_tidy_invocation( start.append(f"--warnings-as-errors={warnings_as_errors}") if allow_no_checks: start.append("--allow-no-checks") + if store_check_profile: + start.append("--enable-check-profile") + start.append(f"--store-check-profile={store_check_profile}") if f: start.append(f) return start @@ -178,6 +182,124 @@ def merge_replacement_files(tmpdir: str, mergefile: str) -> None: open(mergefile, "w").close() +def aggregate_profiles(profile_dir: str) -> Dict[str, float]: + """Aggregate timing data from multiple profile JSON files""" + aggregated: Dict[str, float] = {} + + for profile_file in glob.iglob(os.path.join(profile_dir, "*.json")): + try: + with open(profile_file, "r", encoding="utf-8") as f: + data = json.load(f) + profile_data: Dict[str, float] = data.get("profile", {}) + + for key, value in profile_data.items(): + if key.startswith("time.clang-tidy."): + if key in aggregated: + aggregated[key] += value + else: + aggregated[key] = value + except (json.JSONDecodeError, KeyError, IOError) as e: + print(f"Error: invalid json file {profile_file}: {e}", file=sys.stderr) + continue + + return aggregated + + +def print_profile_data(aggregated_data: Dict[str, float]) -> None: + """Print aggregated checks profile data in the same format as clang-tidy""" + if not aggregated_data: + return + + # Extract checker names and their timing data + checkers: Dict[str, Dict[str, float]] = {} + for key, value in aggregated_data.items(): + parts = key.split(".") + if len(parts) >= 4 and parts[0] == "time" and parts[1] == "clang-tidy": + checker_name = ".".join( + parts[2:-1] + ) # Everything between "clang-tidy" and the timing type + timing_type = parts[-1] # wall, user, or sys + + if checker_name not in checkers: + checkers[checker_name] = {"wall": 0.0, "user": 0.0, "sys": 0.0} + + checkers[checker_name][timing_type] = value + + if not checkers: + return + + total_user = sum(data["user"] for data in checkers.values()) + total_sys = sum(data["sys"] for data in checkers.values()) + total_wall = sum(data["wall"] for data in checkers.values()) + + sorted_checkers: List[Tuple[str, Dict[str, float]]] = sorted( + checkers.items(), key=lambda x: x[1]["user"] + x[1]["sys"], reverse=True + ) + + def print_stderr(*args, **kwargs) -> None: + print(*args, file=sys.stderr, **kwargs) + + print_stderr( + "===-------------------------------------------------------------------------===" + ) + print_stderr(" clang-tidy checks profiling") + print_stderr( + "===-------------------------------------------------------------------------===" + ) + print_stderr( + f" Total Execution Time: {total_user + total_sys:.4f} seconds ({total_wall:.4f} wall clock)\n" + ) + + # Calculate field widths based on the Total line which has the largest values + total_combined = total_user + total_sys + user_width = len(f"{total_user:.4f}") + sys_width = len(f"{total_sys:.4f}") + combined_width = len(f"{total_combined:.4f}") + wall_width = len(f"{total_wall:.4f}") + + # Header with proper alignment + additional_width = 9 # for " (100.0%)" + user_header = "---User Time---".center(user_width + additional_width) + sys_header = "--System Time--".center(sys_width + additional_width) + combined_header = "--User+System--".center(combined_width + additional_width) + wall_header = "---Wall Time---".center(wall_width + additional_width) + + print_stderr( + f" {user_header} {sys_header} {combined_header} {wall_header} --- Name ---" + ) + + for checker_name, data in sorted_checkers: + user_time = data["user"] + sys_time = data["sys"] + wall_time = data["wall"] + combined_time = user_time + sys_time + + user_percent = (user_time / total_user * 100) if total_user > 0 else 0 + sys_percent = (sys_time / total_sys * 100) if total_sys > 0 else 0 + combined_percent = ( + (combined_time / total_combined * 100) if total_combined > 0 else 0 + ) + wall_percent = (wall_time / total_wall * 100) if total_wall > 0 else 0 + + user_str = f"{user_time:{user_width}.4f} ({user_percent:5.1f}%)" + sys_str = f"{sys_time:{sys_width}.4f} ({sys_percent:5.1f}%)" + combined_str = f"{combined_time:{combined_width}.4f} ({combined_percent:5.1f}%)" + wall_str = f"{wall_time:{wall_width}.4f} ({wall_percent:5.1f}%)" + + print_stderr( + f" {user_str} {sys_str} {combined_str} {wall_str} {checker_name}" + ) + + user_total_str = f"{total_user:{user_width}.4f} (100.0%)" + sys_total_str = f"{total_sys:{sys_width}.4f} (100.0%)" + combined_total_str = f"{total_combined:{combined_width}.4f} (100.0%)" + wall_total_str = f"{total_wall:{wall_width}.4f} (100.0%)" + + print_stderr( + f" {user_total_str} {sys_total_str} {combined_total_str} {wall_total_str} Total" + ) + + def find_binary(arg: str, name: str, build_path: str) -> str: """Get the path for a binary or exit""" if arg: @@ -240,6 +362,7 @@ async def run_tidy( clang_tidy_binary: str, tmpdir: str, build_path: str, + store_check_profile: Optional[str], ) -> ClangTidyResult: """ Runs clang-tidy on a single file and returns the result. @@ -263,6 +386,7 @@ async def run_tidy( args.warnings_as_errors, args.exclude_header_filter, args.allow_no_checks, + store_check_profile, ) try: @@ -447,6 +571,11 @@ async def main() -> None: action="store_true", help="Allow empty enabled checks.", ) + parser.add_argument( + "-enable-check-profile", + action="store_true", + help="Enable per-check timing profiles, and print a report", + ) args = parser.parse_args() db_path = "compile_commands.json" @@ -489,6 +618,10 @@ async def main() -> None: export_fixes_dir = tempfile.mkdtemp() delete_fixes_dir = True + profile_dir: Optional[str] = None + if args.enable_check_profile: + profile_dir = tempfile.mkdtemp() + try: invocation = get_tidy_invocation( None, @@ -509,6 +642,7 @@ async def main() -> None: args.warnings_as_errors, args.exclude_header_filter, args.allow_no_checks, + None, # No profiling for the list-checks invocation ) invocation.append("-list-checks") invocation.append("-") @@ -567,6 +701,7 @@ async def main() -> None: clang_tidy_binary, export_fixes_dir, build_path, + profile_dir, ) ) for f in files @@ -593,8 +728,19 @@ async def main() -> None: if delete_fixes_dir: assert export_fixes_dir shutil.rmtree(export_fixes_dir) + if profile_dir: + shutil.rmtree(profile_dir) return + if args.enable_check_profile and profile_dir: + # Ensure all clang-tidy stdout is flushed before printing profiling + sys.stdout.flush() + aggregated_data = aggregate_profiles(profile_dir) + if aggregated_data: + print_profile_data(aggregated_data) + else: + print("No profiling data found.") + if combine_fixes: print(f"Writing fixes to {args.export_fixes} ...") try: @@ -618,6 +764,8 @@ async def main() -> None: if delete_fixes_dir: assert export_fixes_dir shutil.rmtree(export_fixes_dir) + if profile_dir: + shutil.rmtree(profile_dir) sys.exit(returncode) diff --git a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp index dd28806..eaa04fe 100644 --- a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp +++ b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp @@ -432,6 +432,10 @@ RenamerClangTidyCheck::addUsage( if (FixLocation.isInvalid()) return {NamingCheckFailures.end(), false}; + // Skip if in system system header + if (SourceMgr.isInSystemHeader(FixLocation)) + return {NamingCheckFailures.end(), false}; + auto EmplaceResult = NamingCheckFailures.try_emplace(FailureId); NamingCheckFailure &Failure = EmplaceResult.first->second; @@ -455,6 +459,9 @@ RenamerClangTidyCheck::addUsage( void RenamerClangTidyCheck::addUsage(const NamedDecl *Decl, SourceRange UsageRange, const SourceManager &SourceMgr) { + if (SourceMgr.isInSystemHeader(Decl->getLocation())) + return; + if (hasNoName(Decl)) return; diff --git a/clang-tools-extra/clang-tidy/utils/UseRangesCheck.cpp b/clang-tools-extra/clang-tidy/utils/UseRangesCheck.cpp index e421c9f..25601f9 100644 --- a/clang-tools-extra/clang-tidy/utils/UseRangesCheck.cpp +++ b/clang-tools-extra/clang-tidy/utils/UseRangesCheck.cpp @@ -149,7 +149,7 @@ void UseRangesCheck::registerMatchers(MatchFinder *Finder) { } Finder->addMatcher( callExpr( - callee(functionDecl(hasAnyName(std::move(Names))) + callee(functionDecl(hasAnyName(Names)) .bind((FuncDecl + Twine(Replacers.size() - 1).str()))), ast_matchers::internal::DynTypedMatcher::constructVariadic( ast_matchers::internal::DynTypedMatcher::VO_AnyOf, diff --git a/clang-tools-extra/clangd/HeaderSourceSwitch.cpp b/clang-tools-extra/clangd/HeaderSourceSwitch.cpp index d54c366..ee4bea1 100644 --- a/clang-tools-extra/clangd/HeaderSourceSwitch.cpp +++ b/clang-tools-extra/clangd/HeaderSourceSwitch.cpp @@ -20,22 +20,24 @@ namespace clangd { std::optional<Path> getCorrespondingHeaderOrSource( PathRef OriginalFile, llvm::IntrusiveRefCntPtr<llvm::vfs::FileSystem> VFS) { - llvm::StringRef SourceExtensions[] = {".cpp", ".c", ".cc", ".cxx", - ".c++", ".m", ".mm"}; - llvm::StringRef HeaderExtensions[] = {".h", ".hh", ".hpp", ".hxx", - ".inc", ".cppm", ".ccm", ".cxxm", - ".c++m", ".ixx"}; + static constexpr llvm::StringRef SourceExtensions[] = { + ".cpp", ".c", ".cc", ".cxx", ".c++", ".m", ".mm"}; + static constexpr llvm::StringRef HeaderExtensions[] = { + ".h", ".hh", ".hpp", ".hxx", ".inc", + ".cppm", ".ccm", ".cxxm", ".c++m", ".ixx"}; llvm::StringRef PathExt = llvm::sys::path::extension(OriginalFile); // Lookup in a list of known extensions. - bool IsSource = llvm::any_of(SourceExtensions, [&PathExt](PathRef SourceExt) { - return SourceExt.equals_insensitive(PathExt); - }); + const bool IsSource = + llvm::any_of(SourceExtensions, [&PathExt](PathRef SourceExt) { + return SourceExt.equals_insensitive(PathExt); + }); - bool IsHeader = llvm::any_of(HeaderExtensions, [&PathExt](PathRef HeaderExt) { - return HeaderExt.equals_insensitive(PathExt); - }); + const bool IsHeader = + llvm::any_of(HeaderExtensions, [&PathExt](PathRef HeaderExt) { + return HeaderExt.equals_insensitive(PathExt); + }); // We can only switch between the known extensions. if (!IsSource && !IsHeader) @@ -94,7 +96,7 @@ std::optional<Path> getCorrespondingHeaderOrSource(PathRef OriginalFile, // // For each symbol in the original file, we get its target location (decl or // def) from the index, then award that target file. - bool IsHeader = isHeaderFile(OriginalFile, AST.getLangOpts()); + const bool IsHeader = isHeaderFile(OriginalFile, AST.getLangOpts()); Index->lookup(Request, [&](const Symbol &Sym) { if (IsHeader) AwardTarget(Sym.Definition.FileURI); diff --git a/clang-tools-extra/clangd/XRefs.cpp b/clang-tools-extra/clangd/XRefs.cpp index 089f815..5bbc681 100644 --- a/clang-tools-extra/clangd/XRefs.cpp +++ b/clang-tools-extra/clangd/XRefs.cpp @@ -2287,7 +2287,8 @@ prepareCallHierarchy(ParsedAST &AST, Position Pos, PathRef TUPath) { Decl->getKind() != Decl::Kind::FunctionTemplate && !(Decl->getKind() == Decl::Kind::Var && !cast<VarDecl>(Decl)->isLocalVarDecl()) && - Decl->getKind() != Decl::Kind::Field) + Decl->getKind() != Decl::Kind::Field && + Decl->getKind() != Decl::Kind::EnumConstant) continue; if (auto CHI = declToCallHierarchyItem(*Decl, AST.tuPath())) Result.emplace_back(std::move(*CHI)); diff --git a/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp b/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp index eb852ef..08cc80f 100644 --- a/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp +++ b/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp @@ -633,6 +633,35 @@ TEST(CallHierarchy, HierarchyOnVar) { iFromRanges(Source.range("Callee"))))); } +TEST(CallHierarchy, HierarchyOnEnumConstant) { + // Tests that the call hierarchy works on enum constants. + Annotations Source(R"cpp( + enum class Coin { heads$Heads^ , tai$Tails^ls }; + void caller() { + Coin::$CallerH[[heads]]; + Coin::$CallerT[[tails]]; + } + )cpp"); + TestTU TU = TestTU::withCode(Source.code()); + auto AST = TU.build(); + auto Index = TU.index(); + + std::vector<CallHierarchyItem> Items = + prepareCallHierarchy(AST, Source.point("Heads"), testPath(TU.Filename)); + ASSERT_THAT(Items, ElementsAre(withName("heads"))); + auto IncomingLevel1 = incomingCalls(Items[0], Index.get()); + ASSERT_THAT(IncomingLevel1, + ElementsAre(AllOf(from(withName("caller")), + iFromRanges(Source.range("CallerH"))))); + Items = + prepareCallHierarchy(AST, Source.point("Tails"), testPath(TU.Filename)); + ASSERT_THAT(Items, ElementsAre(withName("tails"))); + IncomingLevel1 = incomingCalls(Items[0], Index.get()); + ASSERT_THAT(IncomingLevel1, + ElementsAre(AllOf(from(withName("caller")), + iFromRanges(Source.range("CallerT"))))); +} + TEST(CallHierarchy, CallInDifferentFileThanCaller) { Annotations Header(R"cpp( #define WALDO void caller() { diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index e45f870..85b31bc 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -105,6 +105,10 @@ Improvements to clang-tidy now run checks in parallel by default using all available hardware threads. Both scripts display the number of threads being used in their output. +- Improved :program:`run-clang-tidy.py` by adding a new option + `enable-check-profile` to enable per-check timing profiles and print a + report based on all analyzed files. + New checks ^^^^^^^^^^ @@ -130,10 +134,20 @@ Changes in existing checks <clang-tidy/checks/bugprone/infinite-loop>` check by adding detection for variables introduced by structured bindings. +- Improved :doc:`bugprone-reserved-identifier + <clang-tidy/checks/bugprone/reserved-identifier>` check by ignoring + declarations in system headers. + - Improved :doc:`bugprone-signed-char-misuse <clang-tidy/checks/bugprone/signed-char-misuse>` check by fixing false positives on C23 enums with the fixed underlying type of signed char. +- Improved :doc:`bugprone-tagged-union-member-count + <clang-tidy/checks/bugprone/tagged-union-member-count>` by fixing a false + positive when enums or unions from system header files or the ``std`` + namespace are treated as the tag or the data part of a user-defined + tagged union respectively. + - Improved :doc:`bugprone-unhandled-self-assignment <clang-tidy/checks/bugprone/unhandled-self-assignment>` check by adding an additional matcher that generalizes the copy-and-swap idiom pattern @@ -160,6 +174,10 @@ Changes in existing checks <clang-tidy/checks/portability/template-virtual-member-function>` check to avoid false positives on pure virtual member functions. +- Improved :doc:`readability-identifier-naming + <clang-tidy/checks/readability/identifier-naming>` check by ignoring + declarations in system headers. + - Improved :doc:`readability-qualified-auto <clang-tidy/checks/readability/qualified-auto>` check by adding the option `IgnoreAliasing`, that allows not looking at underlying types of type aliases. diff --git a/clang-tools-extra/docs/clang-tidy/checks/bugprone/tagged-union-member-count.rst b/clang-tools-extra/docs/clang-tidy/checks/bugprone/tagged-union-member-count.rst index 2f1036c..072b5a3 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/bugprone/tagged-union-member-count.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/bugprone/tagged-union-member-count.rst @@ -9,6 +9,8 @@ different from the number of data members inside the union. A struct or a class is considered to be a tagged union if it has exactly one union data member and exactly one enum data member and any number of other data members that are neither unions or enums. +Furthermore, the types of the union and the enum members must +not come from system header files nor the ``std`` namespace. Example: @@ -28,6 +30,25 @@ Example: } Data; }; +The following example illustrates the exception for unions and enums from +system header files and the ``std`` namespace. + +.. code-block:: c++ + + #include <pthread.h> + + struct NotTaggedUnion { + enum MyEnum { MyEnumConstant1, MyEnumConstant2 } En; + pthread_mutex_t Mutex; + }; + +The ``pthread_mutex_t`` type may be defined as a union behind a ``typedef``, +in which case the check could mistake this type as a user-defined tagged union. +After all, it has exactly one enum data member and exactly one union data member. +To avoid false-positive cases originating from this, unions and enums from +system headers and the ``std`` namespace are ignored when pinpointing the +union part and the enum part of a potential user-defined tagged union. + How enum constants are counted ------------------------------ diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/Inputs/tagged-union-member-count/stdnamespace.h b/clang-tools-extra/test/clang-tidy/checkers/bugprone/Inputs/tagged-union-member-count/stdnamespace.h new file mode 100644 index 0000000..4f6eafd --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/Inputs/tagged-union-member-count/stdnamespace.h @@ -0,0 +1,12 @@ +#define __SIZEOF_PTHREAD_MUTEX_T 40 + +namespace std { + typedef union { + struct __pthread_mutex_s { + int __lock; + unsigned int __count; + } __data; + char __size[__SIZEOF_PTHREAD_MUTEX_T]; + long int __align; + } pthread_mutex_t; +}; diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/Inputs/tagged-union-member-count/system/pthread.h b/clang-tools-extra/test/clang-tidy/checkers/bugprone/Inputs/tagged-union-member-count/system/pthread.h new file mode 100644 index 0000000..43aa224 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/Inputs/tagged-union-member-count/system/pthread.h @@ -0,0 +1,10 @@ +#define __SIZEOF_PTHREAD_MUTEX_T 40 + +typedef union { + struct __pthread_mutex_s { + int __lock; + unsigned int __count; + } __data; + char __size[__SIZEOF_PTHREAD_MUTEX_T]; + long int __align; +} pthread_mutex_t; diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.c b/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.c index 60c93c5..f78a05f 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.c +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.c @@ -1,4 +1,5 @@ -// RUN: %check_clang_tidy %s bugprone-tagged-union-member-count %t +// RUN: %check_clang_tidy %s bugprone-tagged-union-member-count %t -- -- \ +// RUN: -isystem %S/Inputs/tagged-union-member-count/system typedef enum Tags3 { tags3_1, @@ -147,3 +148,16 @@ struct Name {\ // CHECK-MESSAGES: :[[@LINE+1]]:44: warning: tagged union has more data members (4) than tags (3) DECLARE_TAGGED_UNION_STRUCT(Tags3, Union4, TaggedUnionStructFromMacro); + +// Unions from system header files should be ignored when +// we are trying to pinpoint the union part in a user-defined tagged union. +#include <pthread.h> + +// This should not be analyzed as a user-defined tagged union, +// even though pthread_mutex_t could be a union. +struct SystemTypedefedUnionDataMemberShouldBeIgnored { + pthread_mutex_t Mutex; + enum { + MyEnum + } EnumField; +}; diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.cpp index 25827e8..c8e36bc 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.cpp @@ -1,4 +1,6 @@ -// RUN: %check_clang_tidy -std=c++98-or-later %s bugprone-tagged-union-member-count %t +// RUN: %check_clang_tidy -std=c++98-or-later %s bugprone-tagged-union-member-count %t -- -- \ +// RUN: -I%S/Inputs/tagged-union-member-count \ +// RUN: -isystem %S/Inputs/tagged-union-member-count/system // Test check with C++ features typedef enum Tags3 { @@ -308,3 +310,26 @@ void DoNotMatchLambdas() { } u; auto L = [e, u] () {}; } + +// Typedefed unions from system header files should be ignored when +// we are trying to pinpoint the union part in a user-defined tagged union. +#include <pthread.h> + +// This should not be analyzed as a user-defined tagged union, +// even though pthread_mutex_t may be declared as a typedefed union. +struct SystemTypedefedUnionDataMemberShouldBeIgnored { + pthread_mutex_t Mutex; + enum { + MyEnum + } EnumField; +}; + +// Filter when union or enum comes from the std namespace but not a system header +#include "stdnamespace.h" + +struct StdNameSpaceUnionDataMemberShouldBeIgnored { + std::pthread_mutex_t Mutex; + enum { + MyEnum + } EnumField; +}; diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.m b/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.m index 60c93c5..79a86cd 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.m +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.m @@ -1,4 +1,5 @@ -// RUN: %check_clang_tidy %s bugprone-tagged-union-member-count %t +// RUN: %check_clang_tidy %s bugprone-tagged-union-member-count %t -- -- \ +// RUN: -isystem %S/Inputs/tagged-union-member-count/system typedef enum Tags3 { tags3_1, @@ -147,3 +148,16 @@ struct Name {\ // CHECK-MESSAGES: :[[@LINE+1]]:44: warning: tagged union has more data members (4) than tags (3) DECLARE_TAGGED_UNION_STRUCT(Tags3, Union4, TaggedUnionStructFromMacro); + +// Typedefed unions from system header files should be ignored when +// we are trying to pinpoint the union part in a user-defined tagged union. +#include <pthread.h> + +// This should not be analyzed as a user-defined tagged union, +// even though pthread_mutex_t may be declared as a typedefed union. +struct SystemTypedefedUnionDataMemberShouldBeIgnored { + pthread_mutex_t Mutex; + enum { + MyEnum + } EnumField; +}; diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.mm b/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.mm index 8b30855..531b10be 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.mm +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/tagged-union-member-count.mm @@ -1,4 +1,5 @@ -// RUN: %check_clang_tidy %s bugprone-tagged-union-member-count %t +// RUN: %check_clang_tidy %s bugprone-tagged-union-member-count %t -- -- \ +// RUN: -isystem %S/Inputs/tagged-union-member-count/system typedef enum Tags3 { tags3_1, @@ -307,3 +308,16 @@ void DoNotMatchLambdas() { } u; auto L = [e, u] () {}; } + +// Typedefed unions from system header files should be ignored when +// we are trying to pinpoint the union part in a user-defined tagged union. +#include <pthread.h> + +// This should not be analyzed as a user-defined tagged union, +// even though pthread_mutex_t may be declared as a typedefed union. +struct SystemTypedefedUnionDataMemberShouldBeIgnored { + pthread_mutex_t Mutex; + enum { + MyEnum + } EnumField; +}; diff --git a/clang-tools-extra/test/clang-tidy/infrastructure/run-clang-tidy-enable-check-profile.cpp b/clang-tools-extra/test/clang-tidy/infrastructure/run-clang-tidy-enable-check-profile.cpp new file mode 100644 index 0000000..9ead09a --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/infrastructure/run-clang-tidy-enable-check-profile.cpp @@ -0,0 +1,56 @@ +// Test profiling functionality with single file +// RUN: rm -rf %t +// RUN: mkdir %t +// RUN: echo "[{\"directory\":\".\",\"command\":\"clang++ -c %/t/test.cpp\",\"file\":\"%/t/test.cpp\"}]" | sed -e 's/\\/\\\\/g' > %t/compile_commands.json +// RUN: echo "Checks: '-*,readability-function-size'" > %t/.clang-tidy +// RUN: cp "%s" "%t/test.cpp" +// RUN: cd "%t" +// RUN: %run_clang_tidy -enable-check-profile "test.cpp" 2>&1 | FileCheck %s --check-prefix=CHECK-SINGLE + +// CHECK-SINGLE: Running clang-tidy in {{[1-9][0-9]*}} threads for 1 files out of 1 in compilation database +// CHECK-SINGLE: ===-------------------------------------------------------------------------=== +// CHECK-SINGLE-NEXT: clang-tidy checks profiling +// CHECK-SINGLE-NEXT: ===-------------------------------------------------------------------------=== +// CHECK-SINGLE-NEXT: Total Execution Time: {{.*}} seconds ({{.*}} wall clock) +// CHECK-SINGLE-EMPTY: +// CHECK-SINGLE-NEXT: ---User Time--- --System Time-- --User+System-- ---Wall Time--- --- Name --- +// CHECK-SINGLE: {{[[:space:]]*[0-9]+\.[0-9]+.*%.*readability-function-size}} +// CHECK-SINGLE: {{[[:space:]]*[0-9]+\.[0-9]+.*100\.0%.*Total}} + +// Test profiling functionality with multiple files and multiple checks +// RUN: rm -rf %t-multi +// RUN: mkdir %t-multi +// RUN: echo "[{\"directory\":\".\",\"command\":\"clang++ -c %/t-multi/test1.cpp\",\"file\":\"%/t-multi/test1.cpp\"},{\"directory\":\".\",\"command\":\"clang++ -c %/t-multi/test2.cpp\",\"file\":\"%/t-multi/test2.cpp\"}]" | sed -e 's/\\/\\\\/g' > %t-multi/compile_commands.json +// RUN: echo "Checks: '-*,readability-function-size,misc-unused-using-decls,llvm-qualified-auto'" > %t-multi/.clang-tidy +// RUN: cp "%s" "%t-multi/test1.cpp" +// RUN: cp "%s" "%t-multi/test2.cpp" +// RUN: cd "%t-multi" +// RUN: %run_clang_tidy -enable-check-profile -j 2 "test1.cpp" "test2.cpp" 2>&1 | FileCheck %s --check-prefix=CHECK-MULTIPLE + +// CHECK-MULTIPLE: Running clang-tidy in 2 threads for 2 files out of 2 in compilation database +// CHECK-MULTIPLE: ===-------------------------------------------------------------------------=== +// CHECK-MULTIPLE-NEXT: clang-tidy checks profiling +// CHECK-MULTIPLE-NEXT: ===-------------------------------------------------------------------------=== +// CHECK-MULTIPLE-NEXT: Total Execution Time: {{.*}} seconds ({{.*}} wall clock) +// CHECK-MULTIPLE-EMPTY: +// CHECK-MULTIPLE-NEXT: ---User Time--- --System Time-- --User+System-- ---Wall Time--- --- Name --- +// CHECK-MULTIPLE-DAG: {{[[:space:]]*[0-9]+\.[0-9]+.*%.*readability-function-size}} +// CHECK-MULTIPLE-DAG: {{[[:space:]]*[0-9]+\.[0-9]+.*%.*misc-unused-using-decls}} +// CHECK-MULTIPLE-DAG: {{[[:space:]]*[0-9]+\.[0-9]+.*%.*llvm-qualified-auto}} +// CHECK-MULTIPLE: {{[[:space:]]*[0-9]+\.[0-9]+.*100\.0%.*Total}} + +// Test profiling functionality with no files (empty database) +// RUN: rm -rf %t-empty +// RUN: mkdir %t-empty +// RUN: echo "[]" > %t-empty/compile_commands.json +// RUN: echo "Checks: '-*'" > %t-empty/.clang-tidy +// RUN: cd "%t-empty" +// RUN: %run_clang_tidy -enable-check-profile -allow-no-checks 2>&1 | FileCheck %s --check-prefix=CHECK-EMPTY + +// CHECK-EMPTY: Running clang-tidy in {{[1-9][0-9]*}} threads for 0 files out of 0 in compilation database +// CHECK-EMPTY: No profiling data found. + +class A { + A() {} + ~A() {} +}; diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 29ef20f..b5bb198 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -2018,7 +2018,7 @@ even if there is no valid ``std::tuple_element`` specialization or suitable Blocks ====== -The syntax and high level language feature description is in +The syntax and high-level language feature description is in :doc:`BlockLanguageSpec<BlockLanguageSpec>`. Implementation and ABI details for the clang implementation are in :doc:`Block-ABI-Apple<Block-ABI-Apple>`. @@ -2088,7 +2088,7 @@ producing an object with the following member functions constexpr size_t size() const; such as ``std::string``, ``std::string_view``, ``std::vector<char>``. -This mechanism follow the same rules as ``static_assert`` messages in +This mechanism follows the same rules as ``static_assert`` messages in C++26, see ``[dcl.pre]/p12``. Query for this feature with ``__has_extension(gnu_asm_constexpr_strings)``. @@ -2335,7 +2335,7 @@ Objective-C Autosynthesis of Properties Clang provides support for autosynthesis of declared properties. Using this feature, clang provides default synthesis of those properties not declared -@dynamic and not having user provided backing getter and setter methods. +@dynamic and not having user-provided backing getter and setter methods. ``__has_feature(objc_default_synthesize_properties)`` checks for availability of this feature in version of clang being used. @@ -2349,7 +2349,7 @@ In Objective-C, functions and methods are generally assumed to follow the <https://developer.apple.com/library/mac/#documentation/Cocoa/Conceptual/MemoryMgmt/Articles/mmRules.html>`_ conventions for ownership of object arguments and return values. However, there are exceptions, and so Clang provides attributes -to allow these exceptions to be documented. This are used by ARC and the +to allow these exceptions to be documented. These are used by ARC and the `static analyzer <https://clang-analyzer.llvm.org>`_ Some exceptions may be better described using the ``objc_method_family`` attribute instead. @@ -2575,7 +2575,7 @@ Such functionality is not conformant and does not guarantee to compile correctly in any circumstances. It can be used if: - the kernel source does not contain call expressions to (member-) function - pointers, or virtual functions. For example this extension can be used in + pointers, or virtual functions. For example, this extension can be used in metaprogramming algorithms to be able to specify/detect types generically. - the generated kernel binary does not contain indirect calls because they @@ -2613,7 +2613,7 @@ functions with variadic prototypes do not get generated in binary e.g. the variadic prototype is used to specify a function type with any number of arguments in metaprogramming algorithms in C++ for OpenCL. -This extensions can also be used when the kernel code is intended for targets +This extension can also be used when the kernel code is intended for targets supporting the variadic arguments e.g. majority of CPU targets. **Example of Use**: @@ -2702,7 +2702,7 @@ address space qualifiers, therefore, other type qualifiers such as Legacy 1.x atomics with generic address space --------------------------------------------- -Clang allows use of atomic functions from the OpenCL 1.x standards +Clang allows the use of atomic functions from the OpenCL 1.x standards with the generic address space pointer in C++ for OpenCL mode. This is a non-portable feature and might not be supported by all @@ -2833,7 +2833,7 @@ to a possibly overlapping destination region. It takes five arguments. The first argument is the destination WebAssembly table, and the second argument is the source WebAssembly table. The third argument is the destination index from where the copy starts, the fourth argument is the -source index from there the copy starts, and the fifth and last argument +source index from where the copy starts, and the fifth and last argument is the number of elements to copy. It returns nothing. .. code-block:: c++ @@ -3133,7 +3133,7 @@ Query for this feature with ``__has_builtin(__builtin_get_vtable_pointer)``. ------------------------------------ ``__builtin_call_with_static_chain`` is used to perform a static call while -setting updating the static chain register. +updating the static chain register. **Syntax**: @@ -3245,7 +3245,7 @@ Query for this feature with ``__has_builtin(__builtin_readsteadycounter)``. The ``__builtin_cpu_supports`` function detects if the run-time CPU supports features specified in string argument. It returns a positive integer if all features are supported and 0 otherwise. Feature names are target specific. On -AArch64 features are combined using ``+`` like this +AArch64, features are combined using ``+`` like this ``__builtin_cpu_supports("flagm+sha3+lse+rcpc2+fcma+memtag+bti+sme2")``. If a feature name is not supported, Clang will issue a warning and replace builtin by the constant 0. @@ -3465,7 +3465,7 @@ Query for this feature with ``__has_builtin(__builtin_convertvector)``. **Description**: The '``__builtin_bitreverse``' family of builtins is used to reverse -the bitpattern of an integer value; for example ``0b10110110`` becomes +the bitpattern of an integer value; for example, ``0b10110110`` becomes ``0b01101101``. These builtins can be used within constant expressions. ``__builtin_rotateleft`` @@ -3970,7 +3970,7 @@ the debugging experience. ``__builtin_allow_runtime_check`` returns true if the check at the current program location should be executed. It is expected to be used to implement -``assert`` like checks which can be safely removed by optimizer. +``assert`` like checks which can be safely removed by the optimizer. **Syntax**: diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 247d784..0bd4857 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -123,6 +123,8 @@ Improvements to Clang's diagnostics Moved the warning for a missing (though implied) attribute on a redeclaration into this group. Added a new warning in this group for the case where the attribute is missing/implicit on an override of a virtual method. +- Fixed fix-it hint for fold expressions. Clang now correctly places the suggested right + parenthesis when diagnosing malformed fold expressions. (#GH151787) Improvements to Clang's time-trace ---------------------------------- diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h index 3b98274a..db86963 100644 --- a/clang/include/clang/AST/ASTContext.h +++ b/clang/include/clang/AST/ASTContext.h @@ -1335,6 +1335,12 @@ public: return ExternalSource.get(); } + /// Retrieve a pointer to the external AST source associated + /// with this AST context, if any. Returns as an IntrusiveRefCntPtr. + IntrusiveRefCntPtr<ExternalASTSource> getExternalSourcePtr() const { + return ExternalSource; + } + /// Attach an AST mutation listener to the AST context. /// /// The AST mutation listener provides the ability to track modifications to diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def b/clang/include/clang/Basic/BuiltinsAMDGPU.def index 0c4a485..ced758c 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.def +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def @@ -716,6 +716,42 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_scale_pk8_bf16_fp4, "V8yUiUiIUi", "nc", "gfx TARGET_BUILTIN(__builtin_amdgcn_cvt_scale_pk8_f32_fp8, "V8fV2UiUiIUi", "nc", "gfx1250-insts") TARGET_BUILTIN(__builtin_amdgcn_cvt_scale_pk8_f32_bf8, "V8fV2UiUiIUi", "nc", "gfx1250-insts") TARGET_BUILTIN(__builtin_amdgcn_cvt_scale_pk8_f32_fp4, "V8fUiUiIUi", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scale_pk16_f16_fp6, "V16hV3UiUiIUi", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scale_pk16_bf16_fp6, "V16yV3UiUiIUi", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scale_pk16_f16_bf6, "V16hV3UiUiIUi", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scale_pk16_bf16_bf6, "V16yV3UiUiIUi", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scale_pk16_f32_fp6, "V16fV3UiUiIUi", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scale_pk16_f32_bf6, "V16fV3UiUiIUi", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk8_fp8_bf16, "V2UiV8yf", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk8_bf8_bf16, "V2UiV8yf", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk8_fp8_f16, "V2UiV8hf", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk8_bf8_f16, "V2UiV8hf", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk8_fp8_f32, "V2UiV8ff", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk8_bf8_f32, "V2UiV8ff", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk8_fp4_f32, "UiV8ff", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk8_fp4_f16, "UiV8hf", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk8_fp4_bf16, "UiV8yf", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk16_fp6_f32, "V3UiV16ff", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk16_bf6_f32, "V3UiV16ff", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk16_fp6_f16, "V3UiV16hf", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk16_bf6_f16, "V3UiV16hf", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk16_fp6_bf16, "V3UiV16yf", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_pk16_bf6_bf16, "V3UiV16yf", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk8_fp8_bf16, "V2UiV8yUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk8_bf8_bf16, "V2UiV8yUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk8_fp8_f16, "V2UiV8hUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk8_bf8_f16, "V2UiV8hUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk8_fp8_f32, "V2UiV8fUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk8_bf8_f32, "V2UiV8fUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk8_fp4_f32, "UiV8fUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk8_fp4_f16, "UiV8hUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk8_fp4_bf16, "UiV8yUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk16_bf6_bf16, "V3UiV16yUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk16_bf6_f16, "V3UiV16hUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk16_bf6_f32, "V3UiV16fUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk16_fp6_bf16, "V3UiV16yUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk16_fp6_f16, "V3UiV16hUif", "nc", "gfx1250-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_scalef32_sr_pk16_fp6_f32, "V3UiV16fUif", "nc", "gfx1250-insts") TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32_e5m3, "iffiIb", "nc", "fp8e5m3-insts") TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32_e5m3, "ifiiIi", "nc", "fp8e5m3-insts") TARGET_BUILTIN(__builtin_amdgcn_sat_pk4_i4_i8, "UsUi", "nc", "gfx1250-insts") @@ -727,6 +763,10 @@ TARGET_BUILTIN(__builtin_amdgcn_permlane_down, "iiii", "nc", "gfx1250-insts,wave TARGET_BUILTIN(__builtin_amdgcn_permlane_xor, "iiii", "nc", "gfx1250-insts,wavefrontsize32") TARGET_BUILTIN(__builtin_amdgcn_permlane_idx_gen, "iii", "nc", "gfx1250-insts,wavefrontsize32") +TARGET_BUILTIN(__builtin_amdgcn_perm_pk16_b4_u4, "V2UiUiUiV2Ui", "nc", "tensor-cvt-lut-insts") +TARGET_BUILTIN(__builtin_amdgcn_perm_pk16_b6_u4, "V3UiUiULiV2Ui", "nc", "tensor-cvt-lut-insts") +TARGET_BUILTIN(__builtin_amdgcn_perm_pk16_b8_u4, "V4UiULiULiV2Ui", "nc", "tensor-cvt-lut-insts") + // GFX1250 WMMA builtins TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x4_f32, "V8fIbV2fIbV2fIsV8fIbIb", "nc", "gfx1250-insts,wavefrontsize32") TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x32_bf16, "V8fIbV16yIbV16yIsV8fIbIb", "nc", "gfx1250-insts,wavefrontsize32") diff --git a/clang/include/clang/Frontend/ASTUnit.h b/clang/include/clang/Frontend/ASTUnit.h index 7dd9aef..ad54016 100644 --- a/clang/include/clang/Frontend/ASTUnit.h +++ b/clang/include/clang/Frontend/ASTUnit.h @@ -451,6 +451,9 @@ public: const SourceManager &getSourceManager() const { return *SourceMgr; } SourceManager &getSourceManager() { return *SourceMgr; } + llvm::IntrusiveRefCntPtr<SourceManager> getSourceManagerPtr() { + return SourceMgr; + } const Preprocessor &getPreprocessor() const { return *PP; } Preprocessor &getPreprocessor() { return *PP; } @@ -458,8 +461,11 @@ public: const ASTContext &getASTContext() const { return *Ctx; } ASTContext &getASTContext() { return *Ctx; } + llvm::IntrusiveRefCntPtr<ASTContext> getASTContextPtr() { return Ctx; } - void setASTContext(ASTContext *ctx) { Ctx = ctx; } + void setASTContext(llvm::IntrusiveRefCntPtr<ASTContext> ctx) { + Ctx = std::move(ctx); + } void setPreprocessor(std::shared_ptr<Preprocessor> pp); /// Enable source-range based diagnostic messages. @@ -495,6 +501,7 @@ public: const FileManager &getFileManager() const { return *FileMgr; } FileManager &getFileManager() { return *FileMgr; } + IntrusiveRefCntPtr<FileManager> getFileManagerPtr() { return FileMgr; } const FileSystemOptions &getFileSystemOpts() const { return FileSystemOpts; } @@ -803,8 +810,8 @@ public: std::shared_ptr<CompilerInvocation> CI, std::shared_ptr<PCHContainerOperations> PCHContainerOps, std::shared_ptr<DiagnosticOptions> DiagOpts, - IntrusiveRefCntPtr<DiagnosticsEngine> Diags, FileManager *FileMgr, - bool OnlyLocalDecls = false, + IntrusiveRefCntPtr<DiagnosticsEngine> Diags, + IntrusiveRefCntPtr<FileManager> FileMgr, bool OnlyLocalDecls = false, CaptureDiagsKind CaptureDiagnostics = CaptureDiagsKind::None, unsigned PrecompilePreambleAfterNParses = 0, TranslationUnitKind TUKind = TU_Complete, @@ -922,8 +929,9 @@ public: CodeCompleteConsumer &Consumer, std::shared_ptr<PCHContainerOperations> PCHContainerOps, llvm::IntrusiveRefCntPtr<DiagnosticsEngine> Diag, - LangOptions &LangOpts, SourceManager &SourceMgr, - FileManager &FileMgr, + LangOptions &LangOpts, + llvm::IntrusiveRefCntPtr<SourceManager> SourceMgr, + llvm::IntrusiveRefCntPtr<FileManager> FileMgr, SmallVectorImpl<StoredDiagnostic> &StoredDiagnostics, SmallVectorImpl<const llvm::MemoryBuffer *> &OwnedBuffers, std::unique_ptr<SyntaxOnlyAction> Act); diff --git a/clang/include/clang/Frontend/CompilerInstance.h b/clang/include/clang/Frontend/CompilerInstance.h index a24decd..64ebb70 100644 --- a/clang/include/clang/Frontend/CompilerInstance.h +++ b/clang/include/clang/Frontend/CompilerInstance.h @@ -446,7 +446,7 @@ public: } /// Replace the current file manager and virtual file system. - void setFileManager(FileManager *Value); + void setFileManager(IntrusiveRefCntPtr<FileManager> Value); /// @} /// @name Source Manager @@ -471,7 +471,7 @@ public: } /// setSourceManager - Replace the current source manager. - void setSourceManager(SourceManager *Value); + void setSourceManager(llvm::IntrusiveRefCntPtr<SourceManager> Value); /// @} /// @name Preprocessor @@ -516,7 +516,7 @@ public: } /// setASTContext - Replace the current AST context. - void setASTContext(ASTContext *Value); + void setASTContext(llvm::IntrusiveRefCntPtr<ASTContext> Value); /// Replace the current Sema; the compiler instance takes ownership /// of S. diff --git a/clang/include/clang/Frontend/Utils.h b/clang/include/clang/Frontend/Utils.h index 604e420..f86c2f5 100644 --- a/clang/include/clang/Frontend/Utils.h +++ b/clang/include/clang/Frontend/Utils.h @@ -189,7 +189,7 @@ void AttachHeaderIncludeGen(Preprocessor &PP, /// memory, mainly for testing. IntrusiveRefCntPtr<ExternalSemaSource> createChainedIncludesSource(CompilerInstance &CI, - IntrusiveRefCntPtr<ExternalSemaSource> &Reader); + IntrusiveRefCntPtr<ASTReader> &OutReader); /// Optional inputs to createInvocation. struct CreateInvocationOptions { diff --git a/clang/include/clang/Sema/MultiplexExternalSemaSource.h b/clang/include/clang/Sema/MultiplexExternalSemaSource.h index 391c217..8bcaa121 100644 --- a/clang/include/clang/Sema/MultiplexExternalSemaSource.h +++ b/clang/include/clang/Sema/MultiplexExternalSemaSource.h @@ -40,7 +40,7 @@ class MultiplexExternalSemaSource : public ExternalSemaSource { static char ID; private: - SmallVector<ExternalSemaSource *, 2> Sources; + SmallVector<llvm::IntrusiveRefCntPtr<ExternalSemaSource>, 2> Sources; public: /// Constructs a new multiplexing external sema source and appends the @@ -49,15 +49,14 @@ public: ///\param[in] S1 - A non-null (old) ExternalSemaSource. ///\param[in] S2 - A non-null (new) ExternalSemaSource. /// - MultiplexExternalSemaSource(ExternalSemaSource *S1, ExternalSemaSource *S2); - - ~MultiplexExternalSemaSource() override; + MultiplexExternalSemaSource(llvm::IntrusiveRefCntPtr<ExternalSemaSource> S1, + llvm::IntrusiveRefCntPtr<ExternalSemaSource> S2); /// Appends new source to the source list. /// ///\param[in] Source - An ExternalSemaSource. /// - void AddSource(ExternalSemaSource *Source); + void AddSource(llvm::IntrusiveRefCntPtr<ExternalSemaSource> Source); //===--------------------------------------------------------------------===// // ExternalASTSource. diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 423dcf9..0b2c027 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -927,7 +927,7 @@ public: /// ///\param[in] E - A non-null external sema source. /// - void addExternalSource(ExternalSemaSource *E); + void addExternalSource(IntrusiveRefCntPtr<ExternalSemaSource> E); /// Print out statistics about the semantic analysis. void PrintStats() const; diff --git a/clang/lib/AST/ByteCode/ByteCodeEmitter.cpp b/clang/lib/AST/ByteCode/ByteCodeEmitter.cpp index 3288585..d474605 100644 --- a/clang/lib/AST/ByteCode/ByteCodeEmitter.cpp +++ b/clang/lib/AST/ByteCode/ByteCodeEmitter.cpp @@ -137,21 +137,21 @@ int32_t ByteCodeEmitter::getOffset(LabelTy Label) { template <typename T> static void emit(Program &P, std::vector<std::byte> &Code, const T &Val, bool &Success) { + size_t ValPos = Code.size(); size_t Size; if constexpr (std::is_pointer_v<T>) - Size = sizeof(uint32_t); + Size = align(sizeof(uint32_t)); else - Size = sizeof(T); + Size = align(sizeof(T)); - if (Code.size() + Size > std::numeric_limits<unsigned>::max()) { + if (ValPos + Size > std::numeric_limits<unsigned>::max()) { Success = false; return; } // Access must be aligned! - size_t ValPos = align(Code.size()); - Size = align(Size); + assert(aligned(ValPos)); assert(aligned(ValPos + Size)); Code.resize(ValPos + Size); @@ -168,17 +168,16 @@ static void emit(Program &P, std::vector<std::byte> &Code, const T &Val, template <typename T> static void emitSerialized(std::vector<std::byte> &Code, const T &Val, bool &Success) { - size_t Size = Val.bytesToSerialize(); + size_t ValPos = Code.size(); + size_t Size = align(Val.bytesToSerialize()); - if (Code.size() + Size > std::numeric_limits<unsigned>::max()) { + if (ValPos + Size > std::numeric_limits<unsigned>::max()) { Success = false; return; } // Access must be aligned! - assert(aligned(Code.size())); - size_t ValPos = Code.size(); - Size = align(Size); + assert(aligned(ValPos)); assert(aligned(ValPos + Size)); Code.resize(ValPos + Size); diff --git a/clang/lib/AST/ByteCode/Compiler.cpp b/clang/lib/AST/ByteCode/Compiler.cpp index 8b9e5e0..6e451ac 100644 --- a/clang/lib/AST/ByteCode/Compiler.cpp +++ b/clang/lib/AST/ByteCode/Compiler.cpp @@ -331,6 +331,8 @@ bool Compiler<Emitter>::VisitCastExpr(const CastExpr *CE) { } case CK_FloatingToIntegral: { + if (!CE->getType()->isIntegralOrEnumerationType()) + return false; if (!this->visit(SubExpr)) return false; PrimType ToT = classifyPrim(CE); @@ -1369,10 +1371,15 @@ bool Compiler<Emitter>::VisitVectorBinOp(const BinaryOperator *E) { // BitAdd/BitOr/BitXor/Shl/Shr doesn't support bool type, we need perform the // integer promotion. bool NeedIntPromot = ElemT == PT_Bool && (E->isBitwiseOp() || E->isShiftOp()); - QualType PromotTy = - Ctx.getASTContext().getPromotedIntegerType(Ctx.getASTContext().BoolTy); - PrimType PromotT = classifyPrim(PromotTy); - PrimType OpT = NeedIntPromot ? PromotT : ElemT; + QualType PromotTy; + PrimType PromotT = PT_Bool; + PrimType OpT = ElemT; + if (NeedIntPromot) { + PromotTy = + Ctx.getASTContext().getPromotedIntegerType(Ctx.getASTContext().BoolTy); + PromotT = classifyPrim(PromotTy); + OpT = PromotT; + } auto getElem = [=](unsigned Offset, PrimType ElemT, unsigned Index) { if (!this->emitGetLocal(PT_Ptr, Offset, E)) diff --git a/clang/lib/AST/ByteCode/Context.cpp b/clang/lib/AST/ByteCode/Context.cpp index aaeb52e..7215e1dd 100644 --- a/clang/lib/AST/ByteCode/Context.cpp +++ b/clang/lib/AST/ByteCode/Context.cpp @@ -15,6 +15,7 @@ #include "InterpStack.h" #include "PrimType.h" #include "Program.h" +#include "clang/AST/ASTLambda.h" #include "clang/AST/Expr.h" #include "clang/Basic/TargetInfo.h" diff --git a/clang/lib/AST/ByteCode/Context.h b/clang/lib/AST/ByteCode/Context.h index 62ef529..1c084ac 100644 --- a/clang/lib/AST/ByteCode/Context.h +++ b/clang/lib/AST/ByteCode/Context.h @@ -17,9 +17,9 @@ #define LLVM_CLANG_AST_INTERP_CONTEXT_H #include "InterpStack.h" +#include "clang/AST/ASTContext.h" namespace clang { -class ASTContext; class LangOptions; class FunctionDecl; class VarDecl; diff --git a/clang/lib/AST/ByteCode/Descriptor.cpp b/clang/lib/AST/ByteCode/Descriptor.cpp index 5b9f445..7403e90 100644 --- a/clang/lib/AST/ByteCode/Descriptor.cpp +++ b/clang/lib/AST/ByteCode/Descriptor.cpp @@ -21,14 +21,31 @@ using namespace clang; using namespace clang::interp; +template <typename T> static constexpr bool needsCtor() { + if constexpr (std::is_same_v<T, Integral<8, true>> || + std::is_same_v<T, Integral<8, false>> || + std::is_same_v<T, Integral<16, true>> || + std::is_same_v<T, Integral<16, false>> || + std::is_same_v<T, Integral<32, true>> || + std::is_same_v<T, Integral<32, false>> || + std::is_same_v<T, Integral<64, true>> || + std::is_same_v<T, Integral<64, false>> || + std::is_same_v<T, Boolean>) + return false; + + return true; +} + template <typename T> static void ctorTy(Block *, std::byte *Ptr, bool, bool, bool, bool, bool, const Descriptor *) { + static_assert(needsCtor<T>()); new (Ptr) T(); } template <typename T> static void dtorTy(Block *, std::byte *Ptr, const Descriptor *) { + static_assert(needsCtor<T>()); reinterpret_cast<T *>(Ptr)->~T(); } @@ -45,9 +62,11 @@ static void ctorArrayTy(Block *, std::byte *Ptr, bool, bool, bool, bool, bool, const Descriptor *D) { new (Ptr) InitMapPtr(std::nullopt); - Ptr += sizeof(InitMapPtr); - for (unsigned I = 0, NE = D->getNumElems(); I < NE; ++I) { - new (&reinterpret_cast<T *>(Ptr)[I]) T(); + if constexpr (needsCtor<T>()) { + Ptr += sizeof(InitMapPtr); + for (unsigned I = 0, NE = D->getNumElems(); I < NE; ++I) { + new (&reinterpret_cast<T *>(Ptr)[I]) T(); + } } } @@ -57,9 +76,12 @@ static void dtorArrayTy(Block *, std::byte *Ptr, const Descriptor *D) { if (IMP) IMP = std::nullopt; - Ptr += sizeof(InitMapPtr); - for (unsigned I = 0, NE = D->getNumElems(); I < NE; ++I) { - reinterpret_cast<T *>(Ptr)[I].~T(); + + if constexpr (needsCtor<T>()) { + Ptr += sizeof(InitMapPtr); + for (unsigned I = 0, NE = D->getNumElems(); I < NE; ++I) { + reinterpret_cast<T *>(Ptr)[I].~T(); + } } } @@ -74,10 +96,14 @@ static void moveArrayTy(Block *, std::byte *Src, std::byte *Dst, } Src += sizeof(InitMapPtr); Dst += sizeof(InitMapPtr); - for (unsigned I = 0, NE = D->getNumElems(); I < NE; ++I) { - auto *SrcPtr = &reinterpret_cast<T *>(Src)[I]; - auto *DstPtr = &reinterpret_cast<T *>(Dst)[I]; - new (DstPtr) T(std::move(*SrcPtr)); + if constexpr (!needsCtor<T>()) { + std::memcpy(Dst, Src, D->getNumElems() * D->getElemSize()); + } else { + for (unsigned I = 0, NE = D->getNumElems(); I < NE; ++I) { + auto *SrcPtr = &reinterpret_cast<T *>(Src)[I]; + auto *DstPtr = &reinterpret_cast<T *>(Dst)[I]; + new (DstPtr) T(std::move(*SrcPtr)); + } } } diff --git a/clang/lib/AST/ByteCode/Function.cpp b/clang/lib/AST/ByteCode/Function.cpp index 0e639df3..a513be5 100644 --- a/clang/lib/AST/ByteCode/Function.cpp +++ b/clang/lib/AST/ByteCode/Function.cpp @@ -8,6 +8,7 @@ #include "Function.h" #include "Program.h" +#include "clang/AST/ASTLambda.h" #include "clang/AST/Decl.h" #include "clang/AST/DeclCXX.h" diff --git a/clang/lib/AST/ByteCode/Function.h b/clang/lib/AST/ByteCode/Function.h index de88f3d..64bffc4 100644 --- a/clang/lib/AST/ByteCode/Function.h +++ b/clang/lib/AST/ByteCode/Function.h @@ -17,9 +17,9 @@ #include "Descriptor.h" #include "Source.h" -#include "clang/AST/ASTLambda.h" #include "clang/AST/Attr.h" #include "clang/AST/Decl.h" +#include "clang/AST/DeclCXX.h" #include "llvm/ADT/PointerUnion.h" #include "llvm/Support/raw_ostream.h" diff --git a/clang/lib/AST/ByteCode/InterpState.cpp b/clang/lib/AST/ByteCode/InterpState.cpp index 3010847..a06b125 100644 --- a/clang/lib/AST/ByteCode/InterpState.cpp +++ b/clang/lib/AST/ByteCode/InterpState.cpp @@ -11,6 +11,8 @@ #include "InterpStack.h" #include "Program.h" #include "State.h" +#include "clang/AST/DeclCXX.h" +#include "clang/AST/DeclTemplate.h" using namespace clang; using namespace clang::interp; @@ -77,27 +79,27 @@ void InterpState::deallocate(Block *B) { const Descriptor *Desc = B->getDescriptor(); assert(Desc); + // The block might have a pointer saved in a field in its data + // that points to the block itself. We call the dtor first, + // which will destroy all the data but leave InlineDescriptors + // intact. If the block THEN still has pointers, we create a + // DeadBlock for it. + if (B->IsInitialized) + B->invokeDtor(); + if (B->hasPointers()) { size_t Size = B->getSize(); - // Allocate a new block, transferring over pointers. char *Memory = reinterpret_cast<char *>(std::malloc(sizeof(DeadBlock) + Size)); auto *D = new (Memory) DeadBlock(DeadBlocks, B); - std::memset(D->B.rawData(), 0, D->B.getSize()); - - // Move data and metadata from the old block to the new (dead)block. - if (B->IsInitialized && Desc->MoveFn) { - Desc->MoveFn(B, B->data(), D->data(), Desc); - if (Desc->getMetadataSize() > 0) - std::memcpy(D->rawData(), B->rawData(), Desc->getMetadataSize()); - } + // Since the block doesn't hold any actual data anymore, we can just + // memcpy() everything over. + std::memcpy(D->rawData(), B->rawData(), Desc->getAllocSize()); D->B.IsInitialized = B->IsInitialized; // We moved the contents over to the DeadBlock. B->IsInitialized = false; - } else if (B->IsInitialized) { - B->invokeDtor(); } } diff --git a/clang/lib/AST/ByteCode/PrimType.h b/clang/lib/AST/ByteCode/PrimType.h index 38c29b9..724da93 100644 --- a/clang/lib/AST/ByteCode/PrimType.h +++ b/clang/lib/AST/ByteCode/PrimType.h @@ -13,7 +13,6 @@ #ifndef LLVM_CLANG_AST_INTERP_TYPE_H #define LLVM_CLANG_AST_INTERP_TYPE_H -#include "clang/Basic/UnsignedOrNone.h" #include "llvm/Support/raw_ostream.h" #include <climits> #include <cstddef> diff --git a/clang/lib/AST/ByteCode/Program.cpp b/clang/lib/AST/ByteCode/Program.cpp index 2421ec4..4daa4ab 100644 --- a/clang/lib/AST/ByteCode/Program.cpp +++ b/clang/lib/AST/ByteCode/Program.cpp @@ -13,6 +13,7 @@ #include "PrimType.h" #include "clang/AST/Decl.h" #include "clang/AST/DeclCXX.h" +#include "clang/AST/DeclTemplate.h" using namespace clang; using namespace clang::interp; diff --git a/clang/lib/AST/MicrosoftMangle.cpp b/clang/lib/AST/MicrosoftMangle.cpp index bc47e05..e6ea0ad 100644 --- a/clang/lib/AST/MicrosoftMangle.cpp +++ b/clang/lib/AST/MicrosoftMangle.cpp @@ -1298,8 +1298,7 @@ void MicrosoftCXXNameMangler::mangleUnqualifiedName(GlobalDecl GD, Name += "<unnamed-type-"; Name += TND->getName(); } else if (isa<EnumDecl>(TD) && - cast<EnumDecl>(TD)->enumerator_begin() != - cast<EnumDecl>(TD)->enumerator_end()) { + !cast<EnumDecl>(TD)->enumerators().empty()) { // Anonymous non-empty enums mangle in the first enumerator. auto *ED = cast<EnumDecl>(TD); Name += "<unnamed-enum-"; diff --git a/clang/lib/CIR/CodeGen/CIRGenDecl.cpp b/clang/lib/CIR/CodeGen/CIRGenDecl.cpp index 9cdbebe..78d375c 100644 --- a/clang/lib/CIR/CodeGen/CIRGenDecl.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenDecl.cpp @@ -158,7 +158,7 @@ void CIRGenFunction::emitAutoVarInit( // out of it while trying to build the expression, mark it as such. mlir::Value val = lv.getAddress().getPointer(); assert(val && "Should have an address"); - auto allocaOp = dyn_cast_or_null<cir::AllocaOp>(val.getDefiningOp()); + auto allocaOp = val.getDefiningOp<cir::AllocaOp>(); assert(allocaOp && "Address should come straight out of the alloca"); if (!allocaOp.use_empty()) @@ -412,7 +412,8 @@ void CIRGenFunction::emitStaticVarDecl(const VarDecl &d, // TODO(cir): we should have a way to represent global ops as values without // having to emit a get global op. Sometimes these emissions are not used. mlir::Value addr = builder.createGetGlobal(globalOp); - auto getAddrOp = mlir::cast<cir::GetGlobalOp>(addr.getDefiningOp()); + auto getAddrOp = addr.getDefiningOp<cir::GetGlobalOp>(); + assert(getAddrOp && "expected cir::GetGlobalOp"); CharUnits alignment = getContext().getDeclAlign(&d); diff --git a/clang/lib/CIR/CodeGen/CIRGenExpr.cpp b/clang/lib/CIR/CodeGen/CIRGenExpr.cpp index 761d8d3..cd37a2b 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExpr.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExpr.cpp @@ -303,8 +303,7 @@ void CIRGenFunction::emitStoreOfScalar(mlir::Value value, Address addr, // Update the alloca with more info on initialization. assert(addr.getPointer() && "expected pointer to exist"); - auto srcAlloca = - dyn_cast_or_null<cir::AllocaOp>(addr.getPointer().getDefiningOp()); + auto srcAlloca = addr.getDefiningOp<cir::AllocaOp>(); if (currVarDecl && srcAlloca) { const VarDecl *vd = currVarDecl; assert(vd && "VarDecl expected"); @@ -635,10 +634,8 @@ LValue CIRGenFunction::emitUnaryOpLValue(const UnaryOperator *e) { // Tag 'load' with deref attribute. // FIXME: This misses some derefence cases and has problematic interactions // with other operators. - if (auto loadOp = - dyn_cast<cir::LoadOp>(addr.getPointer().getDefiningOp())) { + if (auto loadOp = addr.getDefiningOp<cir::LoadOp>()) loadOp.setIsDerefAttr(mlir::UnitAttr::get(&getMLIRContext())); - } LValue lv = makeAddrLValue(addr, t, baseInfo); assert(!cir::MissingFeatures::addressSpace()); @@ -2006,9 +2003,9 @@ cir::AllocaOp CIRGenFunction::createTempAlloca(mlir::Type ty, const Twine &name, mlir::Value arraySize, bool insertIntoFnEntryBlock) { - return cast<cir::AllocaOp>(emitAlloca(name.str(), ty, loc, CharUnits(), - insertIntoFnEntryBlock, arraySize) - .getDefiningOp()); + return mlir::cast<cir::AllocaOp>(emitAlloca(name.str(), ty, loc, CharUnits(), + insertIntoFnEntryBlock, arraySize) + .getDefiningOp()); } /// This creates an alloca and inserts it into the provided insertion point @@ -2018,7 +2015,7 @@ cir::AllocaOp CIRGenFunction::createTempAlloca(mlir::Type ty, mlir::OpBuilder::InsertPoint ip, mlir::Value arraySize) { assert(ip.isSet() && "Insertion point is not set"); - return cast<cir::AllocaOp>( + return mlir::cast<cir::AllocaOp>( emitAlloca(name.str(), ty, loc, CharUnits(), ip, arraySize) .getDefiningOp()); } diff --git a/clang/lib/CIR/CodeGen/CIRGenFunction.cpp b/clang/lib/CIR/CodeGen/CIRGenFunction.cpp index 3ed1e30..f8e7347 100644 --- a/clang/lib/CIR/CodeGen/CIRGenFunction.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenFunction.cpp @@ -219,7 +219,9 @@ void CIRGenFunction::declare(mlir::Value addrVal, const Decl *var, QualType ty, assert(isa<NamedDecl>(var) && "Needs a named decl"); assert(!cir::MissingFeatures::cgfSymbolTable()); - auto allocaOp = cast<cir::AllocaOp>(addrVal.getDefiningOp()); + auto allocaOp = addrVal.getDefiningOp<cir::AllocaOp>(); + assert(allocaOp && "expected cir::AllocaOp"); + if (isParam) allocaOp.setInitAttr(mlir::UnitAttr::get(&getMLIRContext())); if (ty->isReferenceType() || ty.isConstQualified()) diff --git a/clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp b/clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp index 8b01d41a..ecf31a7 100644 --- a/clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp @@ -501,11 +501,7 @@ void CIRRecordLowering::accumulateFields() { fieldEnd = recordDecl->field_end(); field != fieldEnd;) { if (field->isBitField()) { - RecordDecl::field_iterator start = field; - // Iterate to gather the list of bitfields. - for (++field; field != fieldEnd && field->isBitField(); ++field) - ; - field = accumulateBitFields(start, field); + field = accumulateBitFields(field, fieldEnd); assert((field == fieldEnd || !field->isBitField()) && "Failed to accumulate all the bitfields"); } else if (!field->isZeroSize(astContext)) { diff --git a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp index 263ff15..d3fcac1 100644 --- a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp +++ b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp @@ -606,7 +606,7 @@ static Value tryFoldCastChain(cir::CastOp op) { if (!isIntOrBoolCast(op)) break; head = op; - op = dyn_cast_or_null<cir::CastOp>(head.getSrc().getDefiningOp()); + op = head.getSrc().getDefiningOp<cir::CastOp>(); } if (head == tail) @@ -1802,7 +1802,7 @@ OpFoldResult cir::UnaryOp::fold(FoldAdaptor adaptor) { } if (isBoolNot(*this)) - if (auto previous = dyn_cast_or_null<UnaryOp>(getInput().getDefiningOp())) + if (auto previous = getInput().getDefiningOp<cir::UnaryOp>()) if (isBoolNot(previous)) return previous.getInput(); @@ -2184,8 +2184,7 @@ LogicalResult cir::ComplexRealOp::verify() { } OpFoldResult cir::ComplexRealOp::fold(FoldAdaptor adaptor) { - if (auto complexCreateOp = - dyn_cast_or_null<cir::ComplexCreateOp>(getOperand().getDefiningOp())) + if (auto complexCreateOp = getOperand().getDefiningOp<cir::ComplexCreateOp>()) return complexCreateOp.getOperand(0); auto complex = @@ -2206,8 +2205,7 @@ LogicalResult cir::ComplexImagOp::verify() { } OpFoldResult cir::ComplexImagOp::fold(FoldAdaptor adaptor) { - if (auto complexCreateOp = - dyn_cast_or_null<cir::ComplexCreateOp>(getOperand().getDefiningOp())) + if (auto complexCreateOp = getOperand().getDefiningOp<cir::ComplexCreateOp>()) return complexCreateOp.getOperand(1); auto complex = diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp index 895872b..dc6e1b7 100644 --- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp +++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp @@ -821,8 +821,7 @@ mlir::LogicalResult CIRToLLVMPtrStrideOpLowering::matchAndRewrite( // before it. To achieve that, look at unary minus, which already got // lowered to "sub 0, x". const auto sub = dyn_cast<mlir::LLVM::SubOp>(indexOp); - auto unary = dyn_cast_if_present<cir::UnaryOp>( - ptrStrideOp.getStride().getDefiningOp()); + auto unary = ptrStrideOp.getStride().getDefiningOp<cir::UnaryOp>(); bool rewriteSub = unary && unary.getKind() == cir::UnaryOpKind::Minus && sub; if (rewriteSub) @@ -2378,15 +2377,14 @@ mlir::LogicalResult CIRToLLVMVecSplatOpLowering::matchAndRewrite( mlir::Value poison = rewriter.create<mlir::LLVM::PoisonOp>(loc, llvmTy); mlir::Value elementValue = adaptor.getValue(); - if (mlir::isa<mlir::LLVM::PoisonOp>(elementValue.getDefiningOp())) { + if (elementValue.getDefiningOp<mlir::LLVM::PoisonOp>()) { // If the splat value is poison, then we can just use poison value // for the entire vector. rewriter.replaceOp(op, poison); return mlir::success(); } - if (auto constValue = - dyn_cast<mlir::LLVM::ConstantOp>(elementValue.getDefiningOp())) { + if (auto constValue = elementValue.getDefiningOp<mlir::LLVM::ConstantOp>()) { if (auto intAttr = dyn_cast<mlir::IntegerAttr>(constValue.getValue())) { mlir::DenseIntElementsAttr denseVec = mlir::DenseIntElementsAttr::get( mlir::cast<mlir::ShapedType>(llvmTy), intAttr.getValue()); diff --git a/clang/lib/Format/IntegerLiteralSeparatorFixer.cpp b/clang/lib/Format/IntegerLiteralSeparatorFixer.cpp index 7772a56..b51991bf 100644 --- a/clang/lib/Format/IntegerLiteralSeparatorFixer.cpp +++ b/clang/lib/Format/IntegerLiteralSeparatorFixer.cpp @@ -117,7 +117,7 @@ IntegerLiteralSeparatorFixer::process(const Environment &Env, } if (Style.isCpp()) { // Hex alpha digits a-f/A-F must be at the end of the string literal. - StringRef Suffixes = "_himnsuyd"; + static constexpr StringRef Suffixes("_himnsuyd"); if (const auto Pos = Text.find_first_of(IsBase16 ? Suffixes.drop_back() : Suffixes); Pos != StringRef::npos) { diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index d28d2fd..4801d27 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -1939,7 +1939,7 @@ private: Contexts.back().IsExpression = true; next(); if (CurrentToken) - CurrentToken->SpacesRequiredBefore = true; + CurrentToken->SpacesRequiredBefore = 1; parseLine(); break; default: @@ -2639,8 +2639,8 @@ private: if (PreviousNotConst->is(TT_TemplateCloser)) { return PreviousNotConst && PreviousNotConst->MatchingParen && PreviousNotConst->MatchingParen->Previous && - PreviousNotConst->MatchingParen->Previous->isNot(tok::period) && - PreviousNotConst->MatchingParen->Previous->isNot(tok::kw_template); + !PreviousNotConst->MatchingParen->Previous->isOneOf( + tok::period, tok::kw_template); } if ((PreviousNotConst->is(tok::r_paren) && @@ -3369,7 +3369,7 @@ private: Current->isOneOf(Keywords.kw_in, Keywords.kw_as)) { return prec::Relational; } - if (Current->is(TT_BinaryOperator) || Current->is(tok::comma)) + if (Current->isOneOf(TT_BinaryOperator, tok::comma)) return Current->getPrecedence(); if (Current->isOneOf(tok::period, tok::arrow) && Current->isNot(TT_TrailingReturnArrow)) { @@ -4314,8 +4314,8 @@ unsigned TokenAnnotator::splitPenalty(const AnnotatedLine &Line, if (Left.is(tok::coloncolon)) return Style.PenaltyBreakScopeResolution; - if (Right.isOneOf(TT_StartOfName, TT_FunctionDeclarationName) || - Right.is(tok::kw_operator)) { + if (Right.isOneOf(TT_StartOfName, TT_FunctionDeclarationName, + tok::kw_operator)) { if (Line.startsWith(tok::kw_for) && Right.PartOfMultiVariableDeclStmt) return 3; if (Left.is(TT_StartOfName)) @@ -4757,7 +4757,7 @@ bool TokenAnnotator::spaceRequiredBetween(const AnnotatedLine &Line, if (Previous) { if (Previous->endsSequence(tok::kw_operator)) return Style.PointerAlignment != FormatStyle::PAS_Left; - if (Previous->is(tok::kw_const) || Previous->is(tok::kw_volatile)) { + if (Previous->isOneOf(tok::kw_const, tok::kw_volatile)) { return (Style.PointerAlignment != FormatStyle::PAS_Left) || (Style.SpaceAroundPointerQualifiers == FormatStyle::SAPQ_After) || @@ -4931,8 +4931,7 @@ bool TokenAnnotator::spaceRequiredBetween(const AnnotatedLine &Line, } if (Left.is(TT_TemplateCloser) && Left.MatchingParen && Left.MatchingParen->Previous && - (Left.MatchingParen->Previous->is(tok::period) || - Left.MatchingParen->Previous->is(tok::coloncolon))) { + Left.MatchingParen->Previous->isOneOf(tok::period, tok::coloncolon)) { // Java call to generic function with explicit type: // A.<B<C<...>>>DoSomething(); // A::<B<C<...>>>DoSomething(); // With a Java 8 method reference. @@ -5207,8 +5206,7 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, // (e.g. as "const x of y" in a for loop), or after a destructuring // operation (const [x, y] of z, const {a, b} of c). (Left.is(Keywords.kw_of) && BeforeLeft && - (BeforeLeft->is(tok::identifier) || - BeforeLeft->isOneOf(tok::r_square, tok::r_brace)))) && + BeforeLeft->isOneOf(tok::identifier, tok::r_square, tok::r_brace))) && (!BeforeLeft || BeforeLeft->isNot(tok::period))) { return true; } @@ -5516,7 +5514,7 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, return false; } if (Style.isJava() && Right.is(tok::coloncolon) && - (Left.is(tok::identifier) || Left.is(tok::kw_this))) { + Left.isOneOf(tok::identifier, tok::kw_this)) { return false; } if (Right.is(tok::coloncolon) && Left.is(tok::identifier)) { @@ -5587,8 +5585,8 @@ static bool IsFunctionArgument(const FormatToken &Tok) { } static bool -isItAnEmptyLambdaAllowed(const FormatToken &Tok, - FormatStyle::ShortLambdaStyle ShortLambdaOption) { +isEmptyLambdaAllowed(const FormatToken &Tok, + FormatStyle::ShortLambdaStyle ShortLambdaOption) { return Tok.Children.empty() && ShortLambdaOption != FormatStyle::SLS_None; } @@ -5808,8 +5806,8 @@ bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line, } if (Right.is(tok::comment)) { - return Left.isNot(BK_BracedInit) && Left.isNot(TT_CtorInitializerColon) && - (Right.NewlinesBefore > 0 && Right.HasUnescapedNewline); + return !Left.isOneOf(BK_BracedInit, TT_CtorInitializerColon) && + Right.NewlinesBefore > 0 && Right.HasUnescapedNewline; } if (Left.isTrailingComment()) return true; @@ -5977,7 +5975,7 @@ bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line, // Put multiple Java annotation on a new line. if ((Style.isJava() || Style.isJavaScript()) && Left.is(TT_LeadingJavaAnnotation) && - Right.isNot(TT_LeadingJavaAnnotation) && Right.isNot(tok::l_paren) && + !Right.isOneOf(TT_LeadingJavaAnnotation, tok::l_paren) && (Line.Last->is(tok::l_brace) || Style.BreakAfterJavaFieldAnnotations)) { return true; } @@ -6043,7 +6041,7 @@ bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line, ((LBrace->is(tok::l_brace) && (LBrace->is(TT_DictLiteral) || (LBrace->Next && LBrace->Next->is(tok::r_brace)))) || - LBrace->is(TT_ArrayInitializerLSquare) || LBrace->is(tok::less))) { + LBrace->isOneOf(TT_ArrayInitializerLSquare, tok::less))) { // If Left.ParameterCount is 0, then this submessage entry is not the // first in its parent submessage, and we want to break before this entry. // If Left.ParameterCount is greater than 0, then its parent submessage @@ -6257,9 +6255,9 @@ bool TokenAnnotator::canBreakBefore(const AnnotatedLine &Line, } if (Left.is(tok::question) && Right.is(tok::colon)) return false; - if (Right.is(TT_ConditionalExpr) || Right.is(tok::question)) + if (Right.isOneOf(TT_ConditionalExpr, tok::question)) return Style.BreakBeforeTernaryOperators; - if (Left.is(TT_ConditionalExpr) || Left.is(tok::question)) + if (Left.isOneOf(TT_ConditionalExpr, tok::question)) return !Style.BreakBeforeTernaryOperators; if (Left.is(TT_InheritanceColon)) return Style.BreakInheritanceList == FormatStyle::BILS_AfterColon; @@ -6302,7 +6300,7 @@ bool TokenAnnotator::canBreakBefore(const AnnotatedLine &Line, // submessage: { ... } // submessage: < ... > // repeated: [ ... ] - if (((Right.is(tok::l_brace) || Right.is(tok::less)) && + if ((Right.isOneOf(tok::l_brace, tok::less) && Right.is(TT_DictLiteral)) || Right.is(TT_ArrayInitializerLSquare)) { return false; @@ -6352,10 +6350,8 @@ bool TokenAnnotator::canBreakBefore(const AnnotatedLine &Line, Right.getPrecedence() != prec::Assignment)) { return true; } - if (Left.isOneOf(TT_TemplateCloser, TT_UnaryOperator) || - Left.is(tok::kw_operator)) { + if (Left.isOneOf(TT_TemplateCloser, TT_UnaryOperator, tok::kw_operator)) return false; - } if (Left.is(tok::equal) && !Right.isOneOf(tok::kw_default, tok::kw_delete) && Line.Type == LT_VirtualFunctionDecl && Left.NestingLevel == 0) { return false; @@ -6440,9 +6436,9 @@ bool TokenAnnotator::canBreakBefore(const AnnotatedLine &Line, auto ShortLambdaOption = Style.AllowShortLambdasOnASingleLine; if (Style.BraceWrapping.BeforeLambdaBody && Right.is(TT_LambdaLBrace)) { if (isAllmanLambdaBrace(Left)) - return !isItAnEmptyLambdaAllowed(Left, ShortLambdaOption); + return !isEmptyLambdaAllowed(Left, ShortLambdaOption); if (isAllmanLambdaBrace(Right)) - return !isItAnEmptyLambdaAllowed(Right, ShortLambdaOption); + return !isEmptyLambdaAllowed(Right, ShortLambdaOption); } if (Right.is(tok::kw_noexcept) && Right.is(TT_TrailingAnnotation)) { diff --git a/clang/lib/Frontend/ASTUnit.cpp b/clang/lib/Frontend/ASTUnit.cpp index 5711f45..a407825 100644 --- a/clang/lib/Frontend/ASTUnit.cpp +++ b/clang/lib/Frontend/ASTUnit.cpp @@ -831,11 +831,10 @@ std::unique_ptr<ASTUnit> ASTUnit::LoadFromASTFile( AST->CaptureDiagnostics = CaptureDiagnostics; AST->DiagOpts = DiagOpts; AST->Diagnostics = Diags; - AST->FileMgr = new FileManager(FileSystemOpts, VFS); + AST->FileMgr = llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOpts, VFS); AST->UserFilesAreVolatile = UserFilesAreVolatile; - AST->SourceMgr = new SourceManager(AST->getDiagnostics(), - AST->getFileManager(), - UserFilesAreVolatile); + AST->SourceMgr = llvm::makeIntrusiveRefCnt<SourceManager>( + AST->getDiagnostics(), AST->getFileManager(), UserFilesAreVolatile); AST->ModCache = createCrossProcessModuleCache(); AST->HSOpts = std::make_unique<HeaderSearchOptions>(HSOpts); AST->HSOpts->ModuleFormat = std::string(PCHContainerRdr.getFormats().front()); @@ -858,20 +857,20 @@ std::unique_ptr<ASTUnit> ASTUnit::LoadFromASTFile( Preprocessor &PP = *AST->PP; if (ToLoad >= LoadASTOnly) - AST->Ctx = new ASTContext(*AST->LangOpts, AST->getSourceManager(), - PP.getIdentifierTable(), PP.getSelectorTable(), - PP.getBuiltinInfo(), - AST->getTranslationUnitKind()); + AST->Ctx = llvm::makeIntrusiveRefCnt<ASTContext>( + *AST->LangOpts, AST->getSourceManager(), PP.getIdentifierTable(), + PP.getSelectorTable(), PP.getBuiltinInfo(), + AST->getTranslationUnitKind()); DisableValidationForModuleKind disableValid = DisableValidationForModuleKind::None; if (::getenv("LIBCLANG_DISABLE_PCH_VALIDATION")) disableValid = DisableValidationForModuleKind::All; - AST->Reader = new ASTReader(PP, *AST->ModCache, AST->Ctx.get(), - PCHContainerRdr, *AST->CodeGenOpts, {}, - /*isysroot=*/"", - /*DisableValidationKind=*/disableValid, - AllowASTWithCompilerErrors); + AST->Reader = llvm::makeIntrusiveRefCnt<ASTReader>( + PP, *AST->ModCache, AST->Ctx.get(), PCHContainerRdr, *AST->CodeGenOpts, + ArrayRef<std::shared_ptr<ModuleFileExtension>>(), + /*isysroot=*/"", + /*DisableValidationKind=*/disableValid, AllowASTWithCompilerErrors); unsigned Counter = 0; AST->Reader->setListener(std::make_unique<ASTInfoCollector>( @@ -1191,9 +1190,11 @@ bool ASTUnit::Parse(std::shared_ptr<PCHContainerOperations> PCHContainerOps, // changed above in AddImplicitPreamble. If VFS is nullptr, rely on // createFileManager to create one. if (VFS && FileMgr && &FileMgr->getVirtualFileSystem() == VFS) - Clang->setFileManager(&*FileMgr); - else - FileMgr = Clang->createFileManager(std::move(VFS)); + Clang->setFileManager(FileMgr); + else { + Clang->createFileManager(std::move(VFS)); + FileMgr = Clang->getFileManagerPtr(); + } // Recover resources if we crash before exiting this method. llvm::CrashRecoveryContextCleanupRegistrar<CompilerInstance> @@ -1226,15 +1227,15 @@ bool ASTUnit::Parse(std::shared_ptr<PCHContainerOperations> PCHContainerOps, ResetForParse(); - SourceMgr = new SourceManager(getDiagnostics(), *FileMgr, - UserFilesAreVolatile); + SourceMgr = llvm::makeIntrusiveRefCnt<SourceManager>( + getDiagnostics(), *FileMgr, +UserFilesAreVolatile); if (!OverrideMainBuffer) { checkAndRemoveNonDriverDiags(StoredDiagnostics); TopLevelDeclsInPreamble.clear(); } // Create the source manager. - Clang->setSourceManager(&getSourceManager()); + Clang->setSourceManager(getSourceManagerPtr()); // If the main file has been overridden due to the use of a preamble, // make that override happen and introduce the preamble. @@ -1499,13 +1500,13 @@ void ASTUnit::transferASTDataFromCompilerInstance(CompilerInstance &CI) { TheSema = CI.takeSema(); Consumer = CI.takeASTConsumer(); if (CI.hasASTContext()) - Ctx = &CI.getASTContext(); + Ctx = CI.getASTContextPtr(); if (CI.hasPreprocessor()) PP = CI.getPreprocessorPtr(); CI.setSourceManager(nullptr); CI.setFileManager(nullptr); if (CI.hasTarget()) - Target = &CI.getTarget(); + Target = CI.getTargetPtr(); Reader = CI.getASTReader(); HadModuleLoaderFatalFailure = CI.hadModuleLoaderFatalFailure(); if (Invocation != CI.getInvocationPtr()) { @@ -1555,10 +1556,11 @@ ASTUnit::create(std::shared_ptr<CompilerInvocation> CI, AST->Diagnostics = Diags; AST->FileSystemOpts = CI->getFileSystemOpts(); AST->Invocation = std::move(CI); - AST->FileMgr = new FileManager(AST->FileSystemOpts, VFS); + AST->FileMgr = + llvm::makeIntrusiveRefCnt<FileManager>(AST->FileSystemOpts, VFS); AST->UserFilesAreVolatile = UserFilesAreVolatile; - AST->SourceMgr = new SourceManager(AST->getDiagnostics(), *AST->FileMgr, - UserFilesAreVolatile); + AST->SourceMgr = llvm::makeIntrusiveRefCnt<SourceManager>( + AST->getDiagnostics(), *AST->FileMgr, UserFilesAreVolatile); AST->ModCache = createCrossProcessModuleCache(); return AST; @@ -1646,10 +1648,10 @@ ASTUnit *ASTUnit::LoadFromCompilerInvocationAction( AST->Reader = nullptr; // Create a file manager object to provide access to and cache the filesystem. - Clang->setFileManager(&AST->getFileManager()); + Clang->setFileManager(AST->getFileManagerPtr()); // Create the source manager. - Clang->setSourceManager(&AST->getSourceManager()); + Clang->setSourceManager(AST->getSourceManagerPtr()); FrontendAction *Act = Action; @@ -1743,8 +1745,9 @@ std::unique_ptr<ASTUnit> ASTUnit::LoadFromCompilerInvocation( std::shared_ptr<CompilerInvocation> CI, std::shared_ptr<PCHContainerOperations> PCHContainerOps, std::shared_ptr<DiagnosticOptions> DiagOpts, - IntrusiveRefCntPtr<DiagnosticsEngine> Diags, FileManager *FileMgr, - bool OnlyLocalDecls, CaptureDiagsKind CaptureDiagnostics, + IntrusiveRefCntPtr<DiagnosticsEngine> Diags, + IntrusiveRefCntPtr<FileManager> FileMgr, bool OnlyLocalDecls, + CaptureDiagsKind CaptureDiagnostics, unsigned PrecompilePreambleAfterNParses, TranslationUnitKind TUKind, bool CacheCodeCompletionResults, bool IncludeBriefCommentsInCodeCompletion, bool UserFilesAreVolatile) { @@ -1849,7 +1852,8 @@ std::unique_ptr<ASTUnit> ASTUnit::LoadFromCommandLine( AST->FileSystemOpts = CI->getFileSystemOpts(); AST->CodeGenOpts = std::make_unique<CodeGenOptions>(CI->getCodeGenOpts()); VFS = createVFSFromCompilerInvocation(*CI, *Diags, VFS); - AST->FileMgr = new FileManager(AST->FileSystemOpts, VFS); + AST->FileMgr = + llvm::makeIntrusiveRefCnt<FileManager>(AST->FileSystemOpts, VFS); AST->StorePreamblesInMemory = StorePreamblesInMemory; AST->PreambleStoragePath = PreambleStoragePath; AST->ModCache = createCrossProcessModuleCache(); @@ -2210,7 +2214,8 @@ void ASTUnit::CodeComplete( CodeCompleteConsumer &Consumer, std::shared_ptr<PCHContainerOperations> PCHContainerOps, llvm::IntrusiveRefCntPtr<DiagnosticsEngine> Diag, LangOptions &LangOpts, - SourceManager &SourceMgr, FileManager &FileMgr, + llvm::IntrusiveRefCntPtr<SourceManager> SourceMgr, + llvm::IntrusiveRefCntPtr<FileManager> FileMgr, SmallVectorImpl<StoredDiagnostic> &StoredDiagnostics, SmallVectorImpl<const llvm::MemoryBuffer *> &OwnedBuffers, std::unique_ptr<SyntaxOnlyAction> Act) { @@ -2265,7 +2270,7 @@ void ASTUnit::CodeComplete( Clang->getDiagnostics(), &StoredDiagnostics, nullptr); ProcessWarningOptions(*Diag, Inv.getDiagnosticOpts(), - FileMgr.getVirtualFileSystem()); + FileMgr->getVirtualFileSystem()); // Create the target instance. if (!Clang->createTarget()) { @@ -2282,8 +2287,8 @@ void ASTUnit::CodeComplete( "IR inputs not support here!"); // Use the source and file managers that we were given. - Clang->setFileManager(&FileMgr); - Clang->setSourceManager(&SourceMgr); + Clang->setFileManager(FileMgr); + Clang->setSourceManager(SourceMgr); // Remap files. PreprocessorOpts.clearRemappedFiles(); @@ -2301,7 +2306,7 @@ void ASTUnit::CodeComplete( auto getUniqueID = [&FileMgr](StringRef Filename) -> std::optional<llvm::sys::fs::UniqueID> { - if (auto Status = FileMgr.getVirtualFileSystem().status(Filename)) + if (auto Status = FileMgr->getVirtualFileSystem().status(Filename)) return Status->getUniqueID(); return std::nullopt; }; @@ -2322,7 +2327,7 @@ void ASTUnit::CodeComplete( std::unique_ptr<llvm::MemoryBuffer> OverrideMainBuffer; if (Preamble && Line > 1 && hasSameUniqueID(File, OriginalSourceFile)) { OverrideMainBuffer = getMainBufferWithPrecompiledPreamble( - PCHContainerOps, Inv, FileMgr.getVirtualFileSystemPtr(), false, + PCHContainerOps, Inv, FileMgr->getVirtualFileSystemPtr(), false, Line - 1); } @@ -2333,7 +2338,7 @@ void ASTUnit::CodeComplete( "No preamble was built, but OverrideMainBuffer is not null"); IntrusiveRefCntPtr<llvm::vfs::FileSystem> VFS = - FileMgr.getVirtualFileSystemPtr(); + FileMgr->getVirtualFileSystemPtr(); Preamble->AddImplicitPreamble(Clang->getInvocation(), VFS, OverrideMainBuffer.get()); // FIXME: there is no way to update VFS if it was changed by diff --git a/clang/lib/Frontend/ChainedIncludesSource.cpp b/clang/lib/Frontend/ChainedIncludesSource.cpp index 88b1076..013814a 100644 --- a/clang/lib/Frontend/ChainedIncludesSource.cpp +++ b/clang/lib/Frontend/ChainedIncludesSource.cpp @@ -53,17 +53,17 @@ private: }; } // end anonymous namespace -static ASTReader * +static llvm::IntrusiveRefCntPtr<ASTReader> createASTReader(CompilerInstance &CI, StringRef pchFile, SmallVectorImpl<std::unique_ptr<llvm::MemoryBuffer>> &MemBufs, SmallVectorImpl<std::string> &bufNames, ASTDeserializationListener *deserialListener = nullptr) { Preprocessor &PP = CI.getPreprocessor(); - std::unique_ptr<ASTReader> Reader; - Reader.reset(new ASTReader( + auto Reader = llvm::makeIntrusiveRefCnt<ASTReader>( PP, CI.getModuleCache(), &CI.getASTContext(), CI.getPCHContainerReader(), - CI.getCodeGenOpts(), /*Extensions=*/{}, - /*isysroot=*/"", DisableValidationForModuleKind::PCH)); + CI.getCodeGenOpts(), + /*Extensions=*/ArrayRef<std::shared_ptr<ModuleFileExtension>>(), + /*isysroot=*/"", DisableValidationForModuleKind::PCH); for (unsigned ti = 0; ti < bufNames.size(); ++ti) { StringRef sr(bufNames[ti]); Reader->addInMemoryBuffer(sr, std::move(MemBufs[ti])); @@ -74,7 +74,7 @@ createASTReader(CompilerInstance &CI, StringRef pchFile, case ASTReader::Success: // Set the predefines buffer as suggested by the PCH reader. PP.setPredefines(Reader->getSuggestedPredefines()); - return Reader.release(); + return Reader; case ASTReader::Failure: case ASTReader::Missing: @@ -87,8 +87,9 @@ createASTReader(CompilerInstance &CI, StringRef pchFile, return nullptr; } -IntrusiveRefCntPtr<ExternalSemaSource> clang::createChainedIncludesSource( - CompilerInstance &CI, IntrusiveRefCntPtr<ExternalSemaSource> &Reader) { +IntrusiveRefCntPtr<ExternalSemaSource> +clang::createChainedIncludesSource(CompilerInstance &CI, + IntrusiveRefCntPtr<ASTReader> &OutReader) { std::vector<std::string> &includes = CI.getPreprocessorOpts().ChainedIncludes; assert(!includes.empty() && "No '-chain-include' in options!"); @@ -186,12 +187,12 @@ IntrusiveRefCntPtr<ExternalSemaSource> clang::createChainedIncludesSource( assert(!SerialBufs.empty()); std::string pchName = includes.back() + ".pch-final"; serialBufNames.push_back(pchName); - Reader = createASTReader(CI, pchName, SerialBufs, serialBufNames); - if (!Reader) + OutReader = createASTReader(CI, pchName, SerialBufs, serialBufNames); + if (!OutReader) return nullptr; auto ChainedSrc = llvm::makeIntrusiveRefCnt<ChainedIncludesSource>(std::move(CIs)); return llvm::makeIntrusiveRefCnt<MultiplexExternalSemaSource>( - ChainedSrc.get(), Reader.get()); + std::move(ChainedSrc), OutReader); } diff --git a/clang/lib/Frontend/CompilerInstance.cpp b/clang/lib/Frontend/CompilerInstance.cpp index ed6a651..d64290f 100644 --- a/clang/lib/Frontend/CompilerInstance.cpp +++ b/clang/lib/Frontend/CompilerInstance.cpp @@ -166,20 +166,23 @@ CompilerInstance::getVirtualFileSystemPtr() const { return getFileManager().getVirtualFileSystemPtr(); } -void CompilerInstance::setFileManager(FileManager *Value) { - FileMgr = Value; +void CompilerInstance::setFileManager( + llvm::IntrusiveRefCntPtr<FileManager> Value) { + FileMgr = std::move(Value); } -void CompilerInstance::setSourceManager(SourceManager *Value) { - SourceMgr = Value; +void CompilerInstance::setSourceManager( + llvm::IntrusiveRefCntPtr<SourceManager> Value) { + SourceMgr = std::move(Value); } void CompilerInstance::setPreprocessor(std::shared_ptr<Preprocessor> Value) { PP = std::move(Value); } -void CompilerInstance::setASTContext(ASTContext *Value) { - Context = Value; +void CompilerInstance::setASTContext( + llvm::IntrusiveRefCntPtr<ASTContext> Value) { + Context = std::move(Value); if (Context && Consumer) getASTConsumer().Initialize(getASTContext()); @@ -387,14 +390,16 @@ FileManager *CompilerInstance::createFileManager( if (getFrontendOpts().ShowStats) VFS = llvm::makeIntrusiveRefCnt<llvm::vfs::TracingFileSystem>(std::move(VFS)); - FileMgr = new FileManager(getFileSystemOpts(), std::move(VFS)); + FileMgr = llvm::makeIntrusiveRefCnt<FileManager>(getFileSystemOpts(), + std::move(VFS)); return FileMgr.get(); } // Source Manager void CompilerInstance::createSourceManager(FileManager &FileMgr) { - SourceMgr = new SourceManager(getDiagnostics(), FileMgr); + SourceMgr = + llvm::makeIntrusiveRefCnt<SourceManager>(getDiagnostics(), FileMgr); } // Initialize the remapping of files to alternative contents, e.g., @@ -554,11 +559,11 @@ std::string CompilerInstance::getSpecificModuleCachePath(StringRef ModuleHash) { void CompilerInstance::createASTContext() { Preprocessor &PP = getPreprocessor(); - auto *Context = new ASTContext(getLangOpts(), PP.getSourceManager(), - PP.getIdentifierTable(), PP.getSelectorTable(), - PP.getBuiltinInfo(), PP.TUKind); + auto Context = llvm::makeIntrusiveRefCnt<ASTContext>( + getLangOpts(), PP.getSourceManager(), PP.getIdentifierTable(), + PP.getSelectorTable(), PP.getBuiltinInfo(), PP.TUKind); Context->InitBuiltinTypes(getTarget(), getAuxTarget()); - setASTContext(Context); + setASTContext(std::move(Context)); } // ExternalASTSource @@ -638,17 +643,17 @@ IntrusiveRefCntPtr<ASTReader> CompilerInstance::createPCHExternalASTSource( const HeaderSearchOptions &HSOpts = PP.getHeaderSearchInfo().getHeaderSearchOpts(); - IntrusiveRefCntPtr<ASTReader> Reader(new ASTReader( + auto Reader = llvm::makeIntrusiveRefCnt<ASTReader>( PP, ModCache, &Context, PCHContainerRdr, CodeGenOpts, Extensions, Sysroot.empty() ? "" : Sysroot.data(), DisableValidation, AllowPCHWithCompilerErrors, /*AllowConfigurationMismatch*/ false, HSOpts.ModulesValidateSystemHeaders, HSOpts.ModulesForceValidateUserHeaders, - HSOpts.ValidateASTInputFilesContent, UseGlobalModuleIndex)); + HSOpts.ValidateASTInputFilesContent, UseGlobalModuleIndex); // We need the external source to be set up before we read the AST, because // eagerly-deserialized declarations may use it. - Context.setExternalSource(Reader.get()); + Context.setExternalSource(Reader); Reader->setDeserializationListener( static_cast<ASTDeserializationListener *>(DeserializationListener), @@ -755,7 +760,7 @@ void CompilerInstance::createSema(TranslationUnitKind TUKind, // Attach the external sema source if there is any. if (ExternalSemaSrc) { - TheSema->addExternalSource(ExternalSemaSrc.get()); + TheSema->addExternalSource(ExternalSemaSrc); ExternalSemaSrc->InitializeSema(*TheSema); } @@ -1221,7 +1226,7 @@ std::unique_ptr<CompilerInstance> CompilerInstance::cloneForModuleCompileImpl( if (ThreadSafeConfig) { Instance.createFileManager(ThreadSafeConfig->getVFS()); } else if (FrontendOpts.ModulesShareFileManager) { - Instance.setFileManager(&getFileManager()); + Instance.setFileManager(getFileManagerPtr()); } else { Instance.createFileManager(getVirtualFileSystemPtr()); } @@ -1750,17 +1755,18 @@ void CompilerInstance::createASTReader() { if (timerGroup) ReadTimer = std::make_unique<llvm::Timer>("reading_modules", "Reading modules", *timerGroup); - TheASTReader = new ASTReader( + TheASTReader = llvm::makeIntrusiveRefCnt<ASTReader>( getPreprocessor(), getModuleCache(), &getASTContext(), getPCHContainerReader(), getCodeGenOpts(), getFrontendOpts().ModuleFileExtensions, Sysroot.empty() ? "" : Sysroot.c_str(), PPOpts.DisablePCHOrModuleValidation, /*AllowASTWithCompilerErrors=*/FEOpts.AllowPCMWithCompilerErrors, - /*AllowConfigurationMismatch=*/false, HSOpts.ModulesValidateSystemHeaders, - HSOpts.ModulesForceValidateUserHeaders, - HSOpts.ValidateASTInputFilesContent, - getFrontendOpts().UseGlobalModuleIndex, std::move(ReadTimer)); + /*AllowConfigurationMismatch=*/false, + +HSOpts.ModulesValidateSystemHeaders, + +HSOpts.ModulesForceValidateUserHeaders, + +HSOpts.ValidateASTInputFilesContent, + +getFrontendOpts().UseGlobalModuleIndex, std::move(ReadTimer)); if (hasASTConsumer()) { TheASTReader->setDeserializationListener( getASTConsumer().GetASTDeserializationListener()); diff --git a/clang/lib/Frontend/FrontendAction.cpp b/clang/lib/Frontend/FrontendAction.cpp index 87cc2fc..2d69f8c 100644 --- a/clang/lib/Frontend/FrontendAction.cpp +++ b/clang/lib/Frontend/FrontendAction.cpp @@ -845,7 +845,7 @@ bool FrontendAction::BeginSourceFile(CompilerInstance &CI, // Set the shared objects, these are reset when we finish processing the // file, otherwise the CompilerInstance will happily destroy them. - CI.setFileManager(&AST->getFileManager()); + CI.setFileManager(AST->getFileManagerPtr()); CI.createSourceManager(CI.getFileManager()); CI.getSourceManager().initializeForReplay(AST->getSourceManager()); @@ -912,13 +912,13 @@ bool FrontendAction::BeginSourceFile(CompilerInstance &CI, // Set the shared objects, these are reset when we finish processing the // file, otherwise the CompilerInstance will happily destroy them. - CI.setFileManager(&AST->getFileManager()); - CI.setSourceManager(&AST->getSourceManager()); + CI.setFileManager(AST->getFileManagerPtr()); + CI.setSourceManager(AST->getSourceManagerPtr()); CI.setPreprocessor(AST->getPreprocessorPtr()); Preprocessor &PP = CI.getPreprocessor(); PP.getBuiltinInfo().initializeBuiltins(PP.getIdentifierTable(), PP.getLangOpts()); - CI.setASTContext(&AST->getASTContext()); + CI.setASTContext(AST->getASTContextPtr()); setCurrentInput(Input, std::move(AST)); @@ -1172,11 +1172,12 @@ bool FrontendAction::BeginSourceFile(CompilerInstance &CI, if (!CI.getPreprocessorOpts().ChainedIncludes.empty()) { // Convert headers to PCH and chain them. - IntrusiveRefCntPtr<ExternalSemaSource> source, FinalReader; + IntrusiveRefCntPtr<ExternalSemaSource> source; + IntrusiveRefCntPtr<ASTReader> FinalReader; source = createChainedIncludesSource(CI, FinalReader); if (!source) return false; - CI.setASTReader(static_cast<ASTReader *>(FinalReader.get())); + CI.setASTReader(FinalReader); CI.getASTContext().setExternalSource(source); } else if (CI.getLangOpts().Modules || !CI.getPreprocessorOpts().ImplicitPCHInclude.empty()) { @@ -1252,23 +1253,21 @@ bool FrontendAction::BeginSourceFile(CompilerInstance &CI, // provides the layouts from that file. if (!CI.getFrontendOpts().OverrideRecordLayoutsFile.empty() && CI.hasASTContext() && !CI.getASTContext().getExternalSource()) { - IntrusiveRefCntPtr<ExternalASTSource> - Override(new LayoutOverrideSource( - CI.getFrontendOpts().OverrideRecordLayoutsFile)); + auto Override = llvm::makeIntrusiveRefCnt<LayoutOverrideSource>( + CI.getFrontendOpts().OverrideRecordLayoutsFile); CI.getASTContext().setExternalSource(Override); } // Setup HLSL External Sema Source if (CI.getLangOpts().HLSL && CI.hasASTContext()) { - IntrusiveRefCntPtr<ExternalSemaSource> HLSLSema( - new HLSLExternalSemaSource()); - if (auto *SemaSource = dyn_cast_if_present<ExternalSemaSource>( - CI.getASTContext().getExternalSource())) { - IntrusiveRefCntPtr<ExternalSemaSource> MultiSema( - new MultiplexExternalSemaSource(SemaSource, HLSLSema.get())); - CI.getASTContext().setExternalSource(MultiSema); + auto HLSLSema = llvm::makeIntrusiveRefCnt<HLSLExternalSemaSource>(); + if (auto SemaSource = dyn_cast_if_present<ExternalSemaSource>( + CI.getASTContext().getExternalSourcePtr())) { + auto MultiSema = llvm::makeIntrusiveRefCnt<MultiplexExternalSemaSource>( + std::move(SemaSource), std::move(HLSLSema)); + CI.getASTContext().setExternalSource(std::move(MultiSema)); } else - CI.getASTContext().setExternalSource(HLSLSema); + CI.getASTContext().setExternalSource(std::move(HLSLSema)); } FailureCleanup.release(); diff --git a/clang/lib/Frontend/PrecompiledPreamble.cpp b/clang/lib/Frontend/PrecompiledPreamble.cpp index 7fc1d87..03f70b7 100644 --- a/clang/lib/Frontend/PrecompiledPreamble.cpp +++ b/clang/lib/Frontend/PrecompiledPreamble.cpp @@ -483,11 +483,12 @@ llvm::ErrorOr<PrecompiledPreamble> PrecompiledPreamble::Build( VFS); // Create a file manager object to provide access to and cache the filesystem. - Clang->setFileManager(new FileManager(Clang->getFileSystemOpts(), VFS)); + Clang->setFileManager( + llvm::makeIntrusiveRefCnt<FileManager>(Clang->getFileSystemOpts(), VFS)); // Create the source manager. - Clang->setSourceManager( - new SourceManager(*Diagnostics, Clang->getFileManager())); + Clang->setSourceManager(llvm::makeIntrusiveRefCnt<SourceManager>( + *Diagnostics, Clang->getFileManager())); auto PreambleDepCollector = std::make_shared<PreambleDependencyCollector>(); Clang->addDependencyCollector(PreambleDepCollector); diff --git a/clang/lib/Interpreter/CodeCompletion.cpp b/clang/lib/Interpreter/CodeCompletion.cpp index ecdf489..dc7030c 100644 --- a/clang/lib/Interpreter/CodeCompletion.cpp +++ b/clang/lib/Interpreter/CodeCompletion.cpp @@ -238,11 +238,9 @@ public: // compiler instance before the super `ExecuteAction` triggers parsing void IncrementalSyntaxOnlyAction::ExecuteAction() { CompilerInstance &CI = getCompilerInstance(); - ExternalSource *myExternalSource = - new ExternalSource(CI.getASTContext(), CI.getFileManager(), - ParentCI->getASTContext(), ParentCI->getFileManager()); - llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> astContextExternalSource( - myExternalSource); + auto astContextExternalSource = llvm::makeIntrusiveRefCnt<ExternalSource>( + CI.getASTContext(), CI.getFileManager(), ParentCI->getASTContext(), + ParentCI->getFileManager()); CI.getASTContext().setExternalSource(astContextExternalSource); CI.getASTContext().getTranslationUnitDecl()->setHasExternalVisibleStorage( true); @@ -381,8 +379,8 @@ void ReplCodeCompleter::codeComplete(CompilerInstance *InterpCI, AU->CodeComplete(CodeCompletionFileName, 1, Col, RemappedFiles, false, false, false, consumer, std::make_shared<clang::PCHContainerOperations>(), diag, - InterpCI->getLangOpts(), AU->getSourceManager(), - AU->getFileManager(), sd, tb, std::move(Act)); + InterpCI->getLangOpts(), AU->getSourceManagerPtr(), + AU->getFileManagerPtr(), sd, tb, std::move(Act)); } } // namespace clang diff --git a/clang/lib/Sema/MultiplexExternalSemaSource.cpp b/clang/lib/Sema/MultiplexExternalSemaSource.cpp index fbfb242..1f040c8 100644 --- a/clang/lib/Sema/MultiplexExternalSemaSource.cpp +++ b/clang/lib/Sema/MultiplexExternalSemaSource.cpp @@ -20,26 +20,19 @@ char MultiplexExternalSemaSource::ID; /// given element to it. /// MultiplexExternalSemaSource::MultiplexExternalSemaSource( - ExternalSemaSource *S1, ExternalSemaSource *S2) { - S1->Retain(); - S2->Retain(); - Sources.push_back(S1); - Sources.push_back(S2); -} - -// pin the vtable here. -MultiplexExternalSemaSource::~MultiplexExternalSemaSource() { - for (auto *S : Sources) - S->Release(); + llvm::IntrusiveRefCntPtr<ExternalSemaSource> S1, + llvm::IntrusiveRefCntPtr<ExternalSemaSource> S2) { + Sources.push_back(std::move(S1)); + Sources.push_back(std::move(S2)); } /// Appends new source to the source list. /// ///\param[in] source - An ExternalSemaSource. /// -void MultiplexExternalSemaSource::AddSource(ExternalSemaSource *Source) { - Source->Retain(); - Sources.push_back(Source); +void MultiplexExternalSemaSource::AddSource( + llvm::IntrusiveRefCntPtr<ExternalSemaSource> Source) { + Sources.push_back(std::move(Source)); } //===----------------------------------------------------------------------===// @@ -92,7 +85,7 @@ CXXBaseSpecifier *MultiplexExternalSemaSource::GetExternalCXXBaseSpecifiers( CXXCtorInitializer ** MultiplexExternalSemaSource::GetExternalCXXCtorInitializers(uint64_t Offset) { - for (auto *S : Sources) + for (auto &S : Sources) if (auto *R = S->GetExternalCXXCtorInitializers(Offset)) return R; return nullptr; @@ -371,6 +364,6 @@ bool MultiplexExternalSemaSource::MaybeDiagnoseMissingCompleteType( void MultiplexExternalSemaSource::AssignedLambdaNumbering( CXXRecordDecl *Lambda) { - for (auto *Source : Sources) + for (auto &Source : Sources) Source->AssignedLambdaNumbering(Lambda); } diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index 43a7f9e..924becf 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -656,18 +656,19 @@ ASTMutationListener *Sema::getASTMutationListener() const { return getASTConsumer().GetASTMutationListener(); } -void Sema::addExternalSource(ExternalSemaSource *E) { +void Sema::addExternalSource(IntrusiveRefCntPtr<ExternalSemaSource> E) { assert(E && "Cannot use with NULL ptr"); if (!ExternalSource) { - ExternalSource = E; + ExternalSource = std::move(E); return; } - if (auto *Ex = dyn_cast<MultiplexExternalSemaSource>(ExternalSource)) - Ex->AddSource(E); + if (auto *Ex = dyn_cast<MultiplexExternalSemaSource>(ExternalSource.get())) + Ex->AddSource(std::move(E)); else - ExternalSource = new MultiplexExternalSemaSource(ExternalSource.get(), E); + ExternalSource = llvm::makeIntrusiveRefCnt<MultiplexExternalSemaSource>( + ExternalSource, std::move(E)); } void Sema::PrintStats() const { diff --git a/clang/lib/Sema/SemaAMDGPU.cpp b/clang/lib/Sema/SemaAMDGPU.cpp index 8580de2..a5fbd70 100644 --- a/clang/lib/Sema/SemaAMDGPU.cpp +++ b/clang/lib/Sema/SemaAMDGPU.cpp @@ -93,6 +93,12 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_f32_fp8: case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_f32_bf8: case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk8_f32_fp4: + case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_f16_fp6: + case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_bf16_fp6: + case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_f16_bf6: + case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_bf16_bf6: + case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_f32_fp6: + case AMDGPU::BI__builtin_amdgcn_cvt_scale_pk16_f32_bf6: return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 7); } default: diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index 20fdf2d..e2ac648 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -14724,7 +14724,6 @@ void Sema::CheckCompleteVariableDeclaration(VarDecl *var) { type->isIntegralOrEnumerationType()) { // In C++98, in-class initialization for a static data member must // be an integer constant expression. - // SourceLocation Loc; if (!Init->isIntegerConstantExpr(Context)) { Diag(Init->getExprLoc(), diag::ext_in_class_initializer_non_constant) diff --git a/clang/lib/Sema/SemaTemplateVariadic.cpp b/clang/lib/Sema/SemaTemplateVariadic.cpp index 572dbf2..b0a673d 100644 --- a/clang/lib/Sema/SemaTemplateVariadic.cpp +++ b/clang/lib/Sema/SemaTemplateVariadic.cpp @@ -1387,7 +1387,8 @@ static void CheckFoldOperand(Sema &S, Expr *E) { S.Diag(E->getExprLoc(), diag::err_fold_expression_bad_operand) << E->getSourceRange() << FixItHint::CreateInsertion(E->getBeginLoc(), "(") - << FixItHint::CreateInsertion(E->getEndLoc(), ")"); + << FixItHint::CreateInsertion(S.getLocForEndOfToken(E->getEndLoc()), + ")"); } } diff --git a/clang/lib/StaticAnalyzer/Frontend/ModelInjector.cpp b/clang/lib/StaticAnalyzer/Frontend/ModelInjector.cpp index 5d392af..7bc34f6 100644 --- a/clang/lib/StaticAnalyzer/Frontend/ModelInjector.cpp +++ b/clang/lib/StaticAnalyzer/Frontend/ModelInjector.cpp @@ -43,8 +43,8 @@ void ModelInjector::onBodySynthesis(const NamedDecl *D) { if (Bodies.count(D->getName()) != 0) return; - SourceManager &SM = CI.getSourceManager(); - FileID mainFileID = SM.getMainFileID(); + llvm::IntrusiveRefCntPtr<SourceManager> SM = CI.getSourceManagerPtr(); + FileID mainFileID = SM->getMainFileID(); llvm::StringRef modelPath = CI.getAnalyzerOpts().ModelPath; @@ -80,14 +80,14 @@ void ModelInjector::onBodySynthesis(const NamedDecl *D) { new ForwardingDiagnosticConsumer(CI.getDiagnosticClient()), /*ShouldOwnClient=*/true); - Instance.getDiagnostics().setSourceManager(&SM); + Instance.getDiagnostics().setSourceManager(SM.get()); // The instance wants to take ownership, however DisableFree frontend option // is set to true to avoid double free issues - Instance.setFileManager(&CI.getFileManager()); - Instance.setSourceManager(&SM); + Instance.setFileManager(CI.getFileManagerPtr()); + Instance.setSourceManager(SM); Instance.setPreprocessor(CI.getPreprocessorPtr()); - Instance.setASTContext(&CI.getASTContext()); + Instance.setASTContext(CI.getASTContextPtr()); Instance.getPreprocessor().InitializeForModelFile(); @@ -108,5 +108,5 @@ void ModelInjector::onBodySynthesis(const NamedDecl *D) { // the main file id is changed to the model file during parsing and it needs // to be reset to the former main file id after parsing of the model file // is done. - SM.setMainFileID(mainFileID); + SM->setMainFileID(mainFileID); } diff --git a/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp b/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp index 2b5a293..e11319e 100644 --- a/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp +++ b/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp @@ -74,13 +74,24 @@ void skipComments(Lexer &Lex, Token &Tok) { return; } -// Returns the offset after header guard directives and any comments -// before/after header guards (e.g. #ifndef/#define pair, #pragma once). If no -// header guard is present in the code, this will return the offset after -// skipping all comments from the start of the code. -unsigned getOffsetAfterHeaderGuardsAndComments(StringRef FileName, - StringRef Code, - const IncludeStyle &Style) { +bool checkAndConsumeModuleDecl(const SourceManager &SM, Lexer &Lex, + Token &Tok) { + bool Matched = Tok.is(tok::raw_identifier) && + Tok.getRawIdentifier() == "module" && + !Lex.LexFromRawLexer(Tok) && Tok.is(tok::semi) && + !Lex.LexFromRawLexer(Tok); + return Matched; +} + +// Determines the minimum offset into the file where we want to insert header +// includes. This will be put (when available): +// - after `#pragma once` +// - after header guards (`#ifdef` and `#define`) +// - after opening global module (`module;`) +// - after any comments at the start of the file or immediately following one of +// the above constructs +unsigned getMinHeaderInsertionOffset(StringRef FileName, StringRef Code, + const IncludeStyle &Style) { // \p Consume returns location after header guard or 0 if no header guard is // found. auto ConsumeHeaderGuardAndComment = @@ -95,7 +106,17 @@ unsigned getOffsetAfterHeaderGuardsAndComments(StringRef FileName, return std::max(InitialOffset, Consume(SM, Lex, Tok)); }); }; - return std::max( + + auto ModuleDecl = ConsumeHeaderGuardAndComment( + [](const SourceManager &SM, Lexer &Lex, Token Tok) -> unsigned { + if (checkAndConsumeModuleDecl(SM, Lex, Tok)) { + skipComments(Lex, Tok); + return SM.getFileOffset(Tok.getLocation()); + } + return 0; + }); + + auto HeaderAndPPOffset = std::max( // #ifndef/#define ConsumeHeaderGuardAndComment( [](const SourceManager &SM, Lexer &Lex, Token Tok) -> unsigned { @@ -115,6 +136,7 @@ unsigned getOffsetAfterHeaderGuardsAndComments(StringRef FileName, return SM.getFileOffset(Tok.getLocation()); return 0; })); + return std::max(HeaderAndPPOffset, ModuleDecl); } // Check if a sequence of tokens is like @@ -280,8 +302,7 @@ const llvm::Regex HeaderIncludes::IncludeRegex(IncludeRegexPattern); HeaderIncludes::HeaderIncludes(StringRef FileName, StringRef Code, const IncludeStyle &Style) : FileName(FileName), Code(Code), FirstIncludeOffset(-1), - MinInsertOffset( - getOffsetAfterHeaderGuardsAndComments(FileName, Code, Style)), + MinInsertOffset(getMinHeaderInsertionOffset(FileName, Code, Style)), MaxInsertOffset(MinInsertOffset + getMaxHeaderInsertionOffset( FileName, Code.drop_front(MinInsertOffset), Style)), diff --git a/clang/lib/Tooling/Tooling.cpp b/clang/lib/Tooling/Tooling.cpp index ecafe26..45dfdf4 100644 --- a/clang/lib/Tooling/Tooling.cpp +++ b/clang/lib/Tooling/Tooling.cpp @@ -212,8 +212,8 @@ bool runToolOnCodeWithArgs( SmallString<16> FileNameStorage; StringRef FileNameRef = FileName.toNullTerminatedStringRef(FileNameStorage); - llvm::IntrusiveRefCntPtr<FileManager> Files( - new FileManager(FileSystemOptions(), VFS)); + llvm::IntrusiveRefCntPtr<FileManager> Files = + llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), VFS); ArgumentsAdjuster Adjuster = getClangStripDependencyFileAdjuster(); ToolInvocation Invocation( getSyntaxOnlyToolArgs(ToolName, Adjuster(Args, FileNameRef), FileNameRef), @@ -479,7 +479,8 @@ ClangTool::ClangTool(const CompilationDatabase &Compilations, InMemoryFileSystem( llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>()), Files(Files ? Files - : new FileManager(FileSystemOptions(), OverlayFileSystem)) { + : llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), + OverlayFileSystem)) { OverlayFileSystem->pushOverlay(InMemoryFileSystem); appendArgumentsAdjuster(getClangStripOutputAdjuster()); appendArgumentsAdjuster(getClangSyntaxOnlyAdjuster()); @@ -701,8 +702,9 @@ std::unique_ptr<ASTUnit> buildASTFromCodeWithArgs( auto InMemoryFileSystem = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); OverlayFileSystem->pushOverlay(InMemoryFileSystem); - llvm::IntrusiveRefCntPtr<FileManager> Files( - new FileManager(FileSystemOptions(), OverlayFileSystem)); + llvm::IntrusiveRefCntPtr<FileManager> Files = + llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), + OverlayFileSystem); ToolInvocation Invocation( getSyntaxOnlyToolArgs(ToolName, Adjuster(Args, FileName), FileName), diff --git a/clang/test/AST/ByteCode/hlsl.hlsl b/clang/test/AST/ByteCode/hlsl.hlsl index 073e430..60a7f44 100644 --- a/clang/test/AST/ByteCode/hlsl.hlsl +++ b/clang/test/AST/ByteCode/hlsl.hlsl @@ -29,3 +29,11 @@ export void fn() { // smaller vector, then truncated to a float as a constant expression. _Static_assert(((float2)float4(6, 5, 4, 3)).x == 6, "Woo!"); } + +int4 test_D3DCOLORtoUBYTE4(float4 p1) { + return D3DCOLORtoUBYTE4(p1); +} + +int4 test_constant_inputs() { + return D3DCOLORtoUBYTE4(float4(0, 11.11, -50.5, 100)); +} diff --git a/clang/test/Analysis/undef-call.c b/clang/test/Analysis/undef-call.c index 3afdb67..23bfe17 100644 --- a/clang/test/Analysis/undef-call.c +++ b/clang/test/Analysis/undef-call.c @@ -1,6 +1,6 @@ -// RUN: rm -rf %T/ctudir -// RUN: mkdir %T/ctudir -// RUN: %clang_analyze_cc1 -analyzer-checker=debug.ExprInspection -analyzer-config experimental-enable-naive-ctu-analysis=true -analyzer-config ctu-dir=%T/ctudir -verify %s +// RUN: rm -rf %t.dir/ctudir +// RUN: mkdir -p %t.dir/ctudir +// RUN: %clang_analyze_cc1 -analyzer-checker=debug.ExprInspection -analyzer-config experimental-enable-naive-ctu-analysis=true -analyzer-config ctu-dir=%t.dir/ctudir -verify %s // expected-no-diagnostics struct S { diff --git a/clang/test/CIR/CodeGen/bitfields.c b/clang/test/CIR/CodeGen/bitfields.c index 869a7c9..b2c7d1c 100644 --- a/clang/test/CIR/CodeGen/bitfields.c +++ b/clang/test/CIR/CodeGen/bitfields.c @@ -71,12 +71,23 @@ typedef struct { // LLVM-DAG: %struct.U = type <{ i8, i8, i8, i8, i64 }> // OGCG-DAG: %struct.U = type <{ i8, i8, i8, i8, i64 }> +typedef struct{ + int a : 24; + char b; + int c: 30; +} Clip; + +// CIR-DAG: !rec_Clip = !cir.record<struct "Clip" {!cir.array<!u8i x 3>, !s8i, !u32i}> +// LLVM-DAG: %struct.Clip = type { [3 x i8], i8, i32 } +// OGCG-DAG: %struct.Clip = type { [3 x i8], i8, i32 } + void def() { A a; D d; S s; T t; U u; + Clip c; } int load_field(S* s) { diff --git a/clang/test/CodeGen/thinlto_backend.ll b/clang/test/CodeGen/thinlto_backend.ll index dea1a8a..1864fb4 100644 --- a/clang/test/CodeGen/thinlto_backend.ll +++ b/clang/test/CodeGen/thinlto_backend.ll @@ -29,16 +29,16 @@ ; Ensure f2 was imported. Check for all 3 flavors of -save-temps[=cwd|obj]. ; RUN: %clang -target x86_64-unknown-linux-gnu -O2 -o %t3.o -x ir %t1.o -c -fthinlto-index=%t.thinlto.bc -save-temps=obj ; RUN: llvm-dis %t1.s.3.import.bc -o - | FileCheck --check-prefix=CHECK-IMPORT %s -; RUN: mkdir -p %T/dir1 -; RUN: cd %T/dir1 +; RUN: mkdir -p %t.dir/dir1 +; RUN: cd %t.dir/dir1 ; RUN: %clang -target x86_64-unknown-linux-gnu -O2 -o %t3.o -x ir %t1.o -c -fthinlto-index=%t.thinlto.bc -save-temps=cwd ; RUN: cd ../.. -; RUN: llvm-dis %T/dir1/*1.s.3.import.bc -o - | FileCheck --check-prefix=CHECK-IMPORT %s -; RUN: mkdir -p %T/dir2 -; RUN: cd %T/dir2 +; RUN: llvm-dis %t.dir/dir1/*1.s.3.import.bc -o - | FileCheck --check-prefix=CHECK-IMPORT %s +; RUN: mkdir -p %t.dir/dir2 +; RUN: cd %t.dir/dir2 ; RUN: %clang -target x86_64-unknown-linux-gnu -O2 -o %t3.o -x ir %t1.o -c -fthinlto-index=%t.thinlto.bc -save-temps ; RUN: cd ../.. -; RUN: llvm-dis %T/dir2/*1.s.3.import.bc -o - | FileCheck --check-prefix=CHECK-IMPORT %s +; RUN: llvm-dis %t.dir/dir2/*1.s.3.import.bc -o - | FileCheck --check-prefix=CHECK-IMPORT %s ; CHECK-IMPORT: define available_externally void @f2() ; RUN: llvm-nm %t3.o | FileCheck --check-prefix=CHECK-OBJ %s ; CHECK-OBJ: T f1 diff --git a/clang/test/CodeGenCXX/module-intializer-pmf.cpp b/clang/test/CodeGenCXX/module-intializer-pmf.cpp index b553839..3a2d163 100644 --- a/clang/test/CodeGenCXX/module-intializer-pmf.cpp +++ b/clang/test/CodeGenCXX/module-intializer-pmf.cpp @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++20 %s \ -// RUN: -emit-module-interface -o %T/HasPMF.pcm -// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++20 %T/HasPMF.pcm \ +// RUN: -emit-module-interface -o %t.HasPMF.pcm +// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++20 %t.HasPMF.pcm \ // RUN: -emit-llvm -o - | FileCheck %s module; diff --git a/clang/test/CodeGenCXX/profile-remap.cpp b/clang/test/CodeGenCXX/profile-remap.cpp index b27f67d..4bce6df 100644 --- a/clang/test/CodeGenCXX/profile-remap.cpp +++ b/clang/test/CodeGenCXX/profile-remap.cpp @@ -1,10 +1,10 @@ // REQUIRES: x86-registered-target // // RUN: %clang_cc1 -triple x86_64-linux-gnu -fprofile-sample-use=%S/Inputs/profile-remap.samples -fprofile-remapping-file=%S/Inputs/profile-remap.map -O2 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SAMPLES -// RUN: llvm-profdata merge -output %T.profdata %S/Inputs/profile-remap.proftext -// RUN: %clang_cc1 -triple x86_64-linux-gnu -fprofile-instrument-use-path=%T.profdata -fprofile-remapping-file=%S/Inputs/profile-remap.map -O2 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-INSTR -// RUN: llvm-profdata merge -output %T.profdata %S/Inputs/profile-remap_entry.proftext -// RUN: %clang_cc1 -triple x86_64-linux-gnu -fprofile-instrument-use-path=%T.profdata -fprofile-remapping-file=%S/Inputs/profile-remap.map -O2 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-INSTR +// RUN: llvm-profdata merge -output %t.profdata %S/Inputs/profile-remap.proftext +// RUN: %clang_cc1 -triple x86_64-linux-gnu -fprofile-instrument-use-path=%t.profdata -fprofile-remapping-file=%S/Inputs/profile-remap.map -O2 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-INSTR +// RUN: llvm-profdata merge -output %t.profdata %S/Inputs/profile-remap_entry.proftext +// RUN: %clang_cc1 -triple x86_64-linux-gnu -fprofile-instrument-use-path=%t.profdata -fprofile-remapping-file=%S/Inputs/profile-remap.map -O2 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-INSTR namespace Foo { struct X {}; diff --git a/clang/test/CodeGenOpenCL/amdgpu-features.cl b/clang/test/CodeGenOpenCL/amdgpu-features.cl index df71ead..9ae9479 100644 --- a/clang/test/CodeGenOpenCL/amdgpu-features.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-features.cl @@ -108,7 +108,7 @@ // GFX1153: "target-features"="+16-bit-insts,+atomic-fadd-rtn-insts,+ci-insts,+dl-insts,+dot10-insts,+dot12-insts,+dot5-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx8-insts,+gfx9-insts,+wavefrontsize32" // GFX1200: "target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+ci-insts,+dl-insts,+dot10-insts,+dot11-insts,+dot12-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+fp8-conversion-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx8-insts,+gfx9-insts,+wavefrontsize32" // GFX1201: "target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+ci-insts,+dl-insts,+dot10-insts,+dot11-insts,+dot12-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+fp8-conversion-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx8-insts,+gfx9-insts,+wavefrontsize32" -// GFX1250: "target-features"="+16-bit-insts,+ashr-pk-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+bf16-cvt-insts,+bf16-trans-insts,+bitop3-insts,+ci-insts,+dl-insts,+dot7-insts,+dot8-insts,+dpp,+fp8-conversion-insts,+fp8e5m3-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx1250-insts,+gfx8-insts,+gfx9-insts,+permlane16-swap,+prng-inst,+setprio-inc-wg-inst,+tanh-insts,+transpose-load-f4f6-insts,+vmem-pref-insts,+wavefrontsize32" +// GFX1250: "target-features"="+16-bit-insts,+ashr-pk-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+bf16-cvt-insts,+bf16-trans-insts,+bitop3-insts,+ci-insts,+dl-insts,+dot7-insts,+dot8-insts,+dpp,+fp8-conversion-insts,+fp8e5m3-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx1250-insts,+gfx8-insts,+gfx9-insts,+permlane16-swap,+prng-inst,+setprio-inc-wg-inst,+tanh-insts,+tensor-cvt-lut-insts,+transpose-load-f4f6-insts,+vmem-pref-insts,+wavefrontsize32" // GFX1103-W64: "target-features"="+16-bit-insts,+atomic-fadd-rtn-insts,+ci-insts,+dl-insts,+dot10-insts,+dot12-insts,+dot5-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx8-insts,+gfx9-insts,+wavefrontsize64" diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl index 2fd816c..4ff0571 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl @@ -655,6 +655,36 @@ void test_cvt_sr_fp8_f16(global int* out, half a, short sr, int old) // CHECK-NEXT: [[TMP34:%.*]] = call <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.fp4(i32 [[TMP32]], i32 [[TMP33]], i32 7) // CHECK-NEXT: [[TMP35:%.*]] = load ptr addrspace(1), ptr [[OUTF8_ADDR_ASCAST]], align 8 // CHECK-NEXT: store <8 x float> [[TMP34]], ptr addrspace(1) [[TMP35]], align 32 +// CHECK-NEXT: [[TMP36:%.*]] = load <3 x i32>, ptr [[SRC3_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP38:%.*]] = call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.fp6(<3 x i32> [[TMP36]], i32 [[TMP37]], i32 0) +// CHECK-NEXT: [[TMP39:%.*]] = load ptr addrspace(1), ptr [[OUTH16_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <16 x half> [[TMP38]], ptr addrspace(1) [[TMP39]], align 32 +// CHECK-NEXT: [[TMP40:%.*]] = load <3 x i32>, ptr [[SRC3_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = call <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.fp6(<3 x i32> [[TMP40]], i32 [[TMP41]], i32 1) +// CHECK-NEXT: [[TMP43:%.*]] = load ptr addrspace(1), ptr [[OUTY16_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <16 x bfloat> [[TMP42]], ptr addrspace(1) [[TMP43]], align 32 +// CHECK-NEXT: [[TMP44:%.*]] = load <3 x i32>, ptr [[SRC3_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP46:%.*]] = call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.bf6(<3 x i32> [[TMP44]], i32 [[TMP45]], i32 2) +// CHECK-NEXT: [[TMP47:%.*]] = load ptr addrspace(1), ptr [[OUTH16_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <16 x half> [[TMP46]], ptr addrspace(1) [[TMP47]], align 32 +// CHECK-NEXT: [[TMP48:%.*]] = load <3 x i32>, ptr [[SRC3_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = call <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.bf6(<3 x i32> [[TMP48]], i32 [[TMP49]], i32 3) +// CHECK-NEXT: [[TMP51:%.*]] = load ptr addrspace(1), ptr [[OUTY16_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <16 x bfloat> [[TMP50]], ptr addrspace(1) [[TMP51]], align 32 +// CHECK-NEXT: [[TMP52:%.*]] = load <3 x i32>, ptr [[SRC3_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP54:%.*]] = call <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.fp6(<3 x i32> [[TMP52]], i32 [[TMP53]], i32 3) +// CHECK-NEXT: [[TMP55:%.*]] = load ptr addrspace(1), ptr [[OUTF16_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <16 x float> [[TMP54]], ptr addrspace(1) [[TMP55]], align 64 +// CHECK-NEXT: [[TMP56:%.*]] = load <3 x i32>, ptr [[SRC3_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = call <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.bf6(<3 x i32> [[TMP56]], i32 [[TMP57]], i32 4) +// CHECK-NEXT: [[TMP59:%.*]] = load ptr addrspace(1), ptr [[OUTF16_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <16 x float> [[TMP58]], ptr addrspace(1) [[TMP59]], align 64 // CHECK-NEXT: ret void // void test_cvt_scale_pk(global half8 *outh8, global bfloat8 *outy8, uint2 src2, @@ -672,6 +702,290 @@ void test_cvt_scale_pk(global half8 *outh8, global bfloat8 *outy8, uint2 src2, *outf8 = __builtin_amdgcn_cvt_scale_pk8_f32_fp8(src2, scale, 5); *outf8 = __builtin_amdgcn_cvt_scale_pk8_f32_bf8(src2, scale, 6); *outf8 = __builtin_amdgcn_cvt_scale_pk8_f32_fp4(src1, scale, 7); + *outh16 = __builtin_amdgcn_cvt_scale_pk16_f16_fp6(src3, scale, 0); + *outy16 = __builtin_amdgcn_cvt_scale_pk16_bf16_fp6(src3, scale, 1); + *outh16 = __builtin_amdgcn_cvt_scale_pk16_f16_bf6(src3, scale, 2); + *outy16 = __builtin_amdgcn_cvt_scale_pk16_bf16_bf6(src3, scale, 3); + *outf16 = __builtin_amdgcn_cvt_scale_pk16_f32_fp6(src3, scale, 3); + *outf16 = __builtin_amdgcn_cvt_scale_pk16_f32_bf6(src3, scale, 4); +} + +// CHECK-LABEL: @test_cvt_scalef32_pk( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5) +// CHECK-NEXT: [[SRCBF8_ADDR:%.*]] = alloca <8 x bfloat>, align 16, addrspace(5) +// CHECK-NEXT: [[SRCH8_ADDR:%.*]] = alloca <8 x half>, align 16, addrspace(5) +// CHECK-NEXT: [[SRCF8_ADDR:%.*]] = alloca <8 x float>, align 32, addrspace(5) +// CHECK-NEXT: [[OUT3_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5) +// CHECK-NEXT: [[SRCBF16_ADDR:%.*]] = alloca <16 x bfloat>, align 32, addrspace(5) +// CHECK-NEXT: [[SRCH16_ADDR:%.*]] = alloca <16 x half>, align 32, addrspace(5) +// CHECK-NEXT: [[SRCF16_ADDR:%.*]] = alloca <16 x float>, align 64, addrspace(5) +// CHECK-NEXT: [[OUT1_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5) +// CHECK-NEXT: [[SCALE_ADDR:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[OUT2_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT2_ADDR]] to ptr +// CHECK-NEXT: [[SRCBF8_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCBF8_ADDR]] to ptr +// CHECK-NEXT: [[SRCH8_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCH8_ADDR]] to ptr +// CHECK-NEXT: [[SRCF8_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCF8_ADDR]] to ptr +// CHECK-NEXT: [[OUT3_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT3_ADDR]] to ptr +// CHECK-NEXT: [[SRCBF16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCBF16_ADDR]] to ptr +// CHECK-NEXT: [[SRCH16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCH16_ADDR]] to ptr +// CHECK-NEXT: [[SRCF16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCF16_ADDR]] to ptr +// CHECK-NEXT: [[OUT1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT1_ADDR]] to ptr +// CHECK-NEXT: [[SCALE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SCALE_ADDR]] to ptr +// CHECK-NEXT: store ptr addrspace(1) [[OUT2:%.*]], ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <8 x bfloat> [[SRCBF8:%.*]], ptr [[SRCBF8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: store <8 x half> [[SRCH8:%.*]], ptr [[SRCH8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: store <8 x float> [[SRCF8:%.*]], ptr [[SRCF8_ADDR_ASCAST]], align 32 +// CHECK-NEXT: store ptr addrspace(1) [[OUT3:%.*]], ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <16 x bfloat> [[SRCBF16:%.*]], ptr [[SRCBF16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: store <16 x half> [[SRCH16:%.*]], ptr [[SRCH16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: store <16 x float> [[SRCF16:%.*]], ptr [[SRCF16_ADDR_ASCAST]], align 64 +// CHECK-NEXT: store ptr addrspace(1) [[OUT1:%.*]], ptr [[OUT1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store float [[SCALE:%.*]], ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <8 x bfloat>, ptr [[SRCBF8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> [[TMP0]], float [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP2]], ptr addrspace(1) [[TMP3]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load <8 x bfloat>, ptr [[SRCBF8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> [[TMP4]], float [[TMP5]]) +// CHECK-NEXT: [[TMP7:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP6]], ptr addrspace(1) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr [[SRCH8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP9:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> [[TMP8]], float [[TMP9]]) +// CHECK-NEXT: [[TMP11:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP10]], ptr addrspace(1) [[TMP11]], align 8 +// CHECK-NEXT: [[TMP12:%.*]] = load <8 x half>, ptr [[SRCH8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP13:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> [[TMP12]], float [[TMP13]]) +// CHECK-NEXT: [[TMP15:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP14]], ptr addrspace(1) [[TMP15]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = load <8 x float>, ptr [[SRCF8_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> [[TMP16]], float [[TMP17]]) +// CHECK-NEXT: [[TMP19:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP18]], ptr addrspace(1) [[TMP19]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = load <8 x float>, ptr [[SRCF8_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP21:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> [[TMP20]], float [[TMP21]]) +// CHECK-NEXT: [[TMP23:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP22]], ptr addrspace(1) [[TMP23]], align 8 +// CHECK-NEXT: [[TMP24:%.*]] = load <8 x float>, ptr [[SRCF8_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP25:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> [[TMP24]], float [[TMP25]]) +// CHECK-NEXT: [[TMP27:%.*]] = load ptr addrspace(1), ptr [[OUT1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP26]], ptr addrspace(1) [[TMP27]], align 4 +// CHECK-NEXT: [[TMP28:%.*]] = load <8 x half>, ptr [[SRCH8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP30:%.*]] = call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> [[TMP28]], float [[TMP29]]) +// CHECK-NEXT: [[TMP31:%.*]] = load ptr addrspace(1), ptr [[OUT1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP30]], ptr addrspace(1) [[TMP31]], align 4 +// CHECK-NEXT: [[TMP32:%.*]] = load <8 x bfloat>, ptr [[SRCBF8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP33:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP34:%.*]] = call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> [[TMP32]], float [[TMP33]]) +// CHECK-NEXT: [[TMP35:%.*]] = load ptr addrspace(1), ptr [[OUT1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP34]], ptr addrspace(1) [[TMP35]], align 4 +// CHECK-NEXT: [[TMP36:%.*]] = load <16 x bfloat>, ptr [[SRCBF16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP37:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP38:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> [[TMP36]], float [[TMP37]]) +// CHECK-NEXT: [[TMP39:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP38]], ptr addrspace(1) [[TMP39]], align 16 +// CHECK-NEXT: [[TMP40:%.*]] = load <16 x half>, ptr [[SRCH16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP41:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> [[TMP40]], float [[TMP41]]) +// CHECK-NEXT: [[TMP43:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP42]], ptr addrspace(1) [[TMP43]], align 16 +// CHECK-NEXT: [[TMP44:%.*]] = load <16 x bfloat>, ptr [[SRCBF16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP45:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP46:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> [[TMP44]], float [[TMP45]]) +// CHECK-NEXT: [[TMP47:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP46]], ptr addrspace(1) [[TMP47]], align 16 +// CHECK-NEXT: [[TMP48:%.*]] = load <16 x half>, ptr [[SRCH16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP49:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> [[TMP48]], float [[TMP49]]) +// CHECK-NEXT: [[TMP51:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP50]], ptr addrspace(1) [[TMP51]], align 16 +// CHECK-NEXT: [[TMP52:%.*]] = load <16 x float>, ptr [[SRCF16_ADDR_ASCAST]], align 64 +// CHECK-NEXT: [[TMP53:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP54:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> [[TMP52]], float [[TMP53]]) +// CHECK-NEXT: [[TMP55:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP54]], ptr addrspace(1) [[TMP55]], align 16 +// CHECK-NEXT: [[TMP56:%.*]] = load <16 x float>, ptr [[SRCF16_ADDR_ASCAST]], align 64 +// CHECK-NEXT: [[TMP57:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> [[TMP56]], float [[TMP57]]) +// CHECK-NEXT: [[TMP59:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP58]], ptr addrspace(1) [[TMP59]], align 16 +// CHECK-NEXT: ret void +// +void test_cvt_scalef32_pk(global uint2 *out2, bfloat8 srcbf8, half8 srch8, float8 srcf8, + global uint3 *out3, bfloat16 srcbf16, half16 srch16, float16 srcf16, + global uint *out1, float scale) +{ + *out2 = __builtin_amdgcn_cvt_scalef32_pk8_fp8_bf16(srcbf8, scale); + *out2 = __builtin_amdgcn_cvt_scalef32_pk8_bf8_bf16(srcbf8, scale); + *out2 = __builtin_amdgcn_cvt_scalef32_pk8_fp8_f16(srch8, scale); + *out2 = __builtin_amdgcn_cvt_scalef32_pk8_bf8_f16(srch8, scale); + *out2 = __builtin_amdgcn_cvt_scalef32_pk8_fp8_f32(srcf8, scale); + *out2 = __builtin_amdgcn_cvt_scalef32_pk8_bf8_f32(srcf8, scale); + *out1 = __builtin_amdgcn_cvt_scalef32_pk8_fp4_f32(srcf8, scale); + *out1 = __builtin_amdgcn_cvt_scalef32_pk8_fp4_f16(srch8, scale); + *out1 = __builtin_amdgcn_cvt_scalef32_pk8_fp4_bf16(srcbf8, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_pk16_bf6_bf16(srcbf16, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_pk16_bf6_f16(srch16, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_pk16_fp6_bf16(srcbf16, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_pk16_fp6_f16(srch16, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_pk16_bf6_f32(srcf16, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_pk16_fp6_f32(srcf16, scale); +} + +// CHECK-LABEL: @test_cvt_scalef32_sr_pk( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5) +// CHECK-NEXT: [[SRCBF8_ADDR:%.*]] = alloca <8 x bfloat>, align 16, addrspace(5) +// CHECK-NEXT: [[SRCH8_ADDR:%.*]] = alloca <8 x half>, align 16, addrspace(5) +// CHECK-NEXT: [[SRCF8_ADDR:%.*]] = alloca <8 x float>, align 32, addrspace(5) +// CHECK-NEXT: [[OUT3_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5) +// CHECK-NEXT: [[SRCBF16_ADDR:%.*]] = alloca <16 x bfloat>, align 32, addrspace(5) +// CHECK-NEXT: [[SRCH16_ADDR:%.*]] = alloca <16 x half>, align 32, addrspace(5) +// CHECK-NEXT: [[SRCF16_ADDR:%.*]] = alloca <16 x float>, align 64, addrspace(5) +// CHECK-NEXT: [[OUT1_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5) +// CHECK-NEXT: [[SR_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SCALE_ADDR:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[OUT2_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT2_ADDR]] to ptr +// CHECK-NEXT: [[SRCBF8_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCBF8_ADDR]] to ptr +// CHECK-NEXT: [[SRCH8_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCH8_ADDR]] to ptr +// CHECK-NEXT: [[SRCF8_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCF8_ADDR]] to ptr +// CHECK-NEXT: [[OUT3_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT3_ADDR]] to ptr +// CHECK-NEXT: [[SRCBF16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCBF16_ADDR]] to ptr +// CHECK-NEXT: [[SRCH16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCH16_ADDR]] to ptr +// CHECK-NEXT: [[SRCF16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRCF16_ADDR]] to ptr +// CHECK-NEXT: [[OUT1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT1_ADDR]] to ptr +// CHECK-NEXT: [[SR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SR_ADDR]] to ptr +// CHECK-NEXT: [[SCALE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SCALE_ADDR]] to ptr +// CHECK-NEXT: store ptr addrspace(1) [[OUT2:%.*]], ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <8 x bfloat> [[SRCBF8:%.*]], ptr [[SRCBF8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: store <8 x half> [[SRCH8:%.*]], ptr [[SRCH8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: store <8 x float> [[SRCF8:%.*]], ptr [[SRCF8_ADDR_ASCAST]], align 32 +// CHECK-NEXT: store ptr addrspace(1) [[OUT3:%.*]], ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <16 x bfloat> [[SRCBF16:%.*]], ptr [[SRCBF16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: store <16 x half> [[SRCH16:%.*]], ptr [[SRCH16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: store <16 x float> [[SRCF16:%.*]], ptr [[SRCF16_ADDR_ASCAST]], align 64 +// CHECK-NEXT: store ptr addrspace(1) [[OUT1:%.*]], ptr [[OUT1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[SR:%.*]], ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store float [[SCALE:%.*]], ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <8 x bfloat>, ptr [[SRCBF8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.bf16(<8 x bfloat> [[TMP0]], i32 [[TMP1]], float [[TMP2]]) +// CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP3]], ptr addrspace(1) [[TMP4]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load <8 x bfloat>, ptr [[SRCBF8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.bf16(<8 x bfloat> [[TMP5]], i32 [[TMP6]], float [[TMP7]]) +// CHECK-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP8]], ptr addrspace(1) [[TMP9]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr [[SRCH8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f16(<8 x half> [[TMP10]], i32 [[TMP11]], float [[TMP12]]) +// CHECK-NEXT: [[TMP14:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP13]], ptr addrspace(1) [[TMP14]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = load <8 x half>, ptr [[SRCH8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f16(<8 x half> [[TMP15]], i32 [[TMP16]], float [[TMP17]]) +// CHECK-NEXT: [[TMP19:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP18]], ptr addrspace(1) [[TMP19]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = load <8 x float>, ptr [[SRCF8_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f32(<8 x float> [[TMP20]], i32 [[TMP21]], float [[TMP22]]) +// CHECK-NEXT: [[TMP24:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP23]], ptr addrspace(1) [[TMP24]], align 8 +// CHECK-NEXT: [[TMP25:%.*]] = load <8 x float>, ptr [[SRCF8_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP27:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP28:%.*]] = call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f32(<8 x float> [[TMP25]], i32 [[TMP26]], float [[TMP27]]) +// CHECK-NEXT: [[TMP29:%.*]] = load ptr addrspace(1), ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP28]], ptr addrspace(1) [[TMP29]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load <8 x float>, ptr [[SRCF8_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP32:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f32(<8 x float> [[TMP30]], i32 [[TMP31]], float [[TMP32]]) +// CHECK-NEXT: [[TMP34:%.*]] = load ptr addrspace(1), ptr [[OUT1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP33]], ptr addrspace(1) [[TMP34]], align 4 +// CHECK-NEXT: [[TMP35:%.*]] = load <8 x half>, ptr [[SRCH8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP38:%.*]] = call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f16(<8 x half> [[TMP35]], i32 [[TMP36]], float [[TMP37]]) +// CHECK-NEXT: [[TMP39:%.*]] = load ptr addrspace(1), ptr [[OUT1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP38]], ptr addrspace(1) [[TMP39]], align 4 +// CHECK-NEXT: [[TMP40:%.*]] = load <8 x bfloat>, ptr [[SRCBF8_ADDR_ASCAST]], align 16 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP43:%.*]] = call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.bf16(<8 x bfloat> [[TMP40]], i32 [[TMP41]], float [[TMP42]]) +// CHECK-NEXT: [[TMP44:%.*]] = load ptr addrspace(1), ptr [[OUT1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP43]], ptr addrspace(1) [[TMP44]], align 4 +// CHECK-NEXT: [[TMP45:%.*]] = load <16 x bfloat>, ptr [[SRCBF16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP47:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> [[TMP45]], i32 [[TMP46]], float [[TMP47]]) +// CHECK-NEXT: [[TMP49:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP48]], ptr addrspace(1) [[TMP49]], align 16 +// CHECK-NEXT: [[TMP50:%.*]] = load <16 x half>, ptr [[SRCH16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP51:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP52:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP53:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> [[TMP50]], i32 [[TMP51]], float [[TMP52]]) +// CHECK-NEXT: [[TMP54:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP53]], ptr addrspace(1) [[TMP54]], align 16 +// CHECK-NEXT: [[TMP55:%.*]] = load <16 x bfloat>, ptr [[SRCBF16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP57:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> [[TMP55]], i32 [[TMP56]], float [[TMP57]]) +// CHECK-NEXT: [[TMP59:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP58]], ptr addrspace(1) [[TMP59]], align 16 +// CHECK-NEXT: [[TMP60:%.*]] = load <16 x half>, ptr [[SRCH16_ADDR_ASCAST]], align 32 +// CHECK-NEXT: [[TMP61:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP62:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP63:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> [[TMP60]], i32 [[TMP61]], float [[TMP62]]) +// CHECK-NEXT: [[TMP64:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP63]], ptr addrspace(1) [[TMP64]], align 16 +// CHECK-NEXT: [[TMP65:%.*]] = load <16 x float>, ptr [[SRCF16_ADDR_ASCAST]], align 64 +// CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP67:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP68:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> [[TMP65]], i32 [[TMP66]], float [[TMP67]]) +// CHECK-NEXT: [[TMP69:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP68]], ptr addrspace(1) [[TMP69]], align 16 +// CHECK-NEXT: [[TMP70:%.*]] = load <16 x float>, ptr [[SRCF16_ADDR_ASCAST]], align 64 +// CHECK-NEXT: [[TMP71:%.*]] = load i32, ptr [[SR_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP72:%.*]] = load float, ptr [[SCALE_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP73:%.*]] = call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> [[TMP70]], i32 [[TMP71]], float [[TMP72]]) +// CHECK-NEXT: [[TMP74:%.*]] = load ptr addrspace(1), ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP73]], ptr addrspace(1) [[TMP74]], align 16 +// CHECK-NEXT: ret void +// +void test_cvt_scalef32_sr_pk(global uint2 *out2, bfloat8 srcbf8, half8 srch8, float8 srcf8, + global uint3 *out3, bfloat16 srcbf16, half16 srch16, float16 srcf16, + global uint *out1, uint sr, float scale) +{ + *out2 = __builtin_amdgcn_cvt_scalef32_sr_pk8_fp8_bf16(srcbf8, sr, scale); + *out2 = __builtin_amdgcn_cvt_scalef32_sr_pk8_bf8_bf16(srcbf8, sr, scale); + *out2 = __builtin_amdgcn_cvt_scalef32_sr_pk8_fp8_f16(srch8, sr, scale); + *out2 = __builtin_amdgcn_cvt_scalef32_sr_pk8_bf8_f16(srch8, sr, scale); + *out2 = __builtin_amdgcn_cvt_scalef32_sr_pk8_fp8_f32(srcf8, sr, scale); + *out2 = __builtin_amdgcn_cvt_scalef32_sr_pk8_bf8_f32(srcf8, sr, scale); + *out1 = __builtin_amdgcn_cvt_scalef32_sr_pk8_fp4_f32(srcf8, sr, scale); + *out1 = __builtin_amdgcn_cvt_scalef32_sr_pk8_fp4_f16(srch8, sr, scale); + *out1 = __builtin_amdgcn_cvt_scalef32_sr_pk8_fp4_bf16(srcbf8, sr, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_sr_pk16_bf6_bf16(srcbf16, sr, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_sr_pk16_bf6_f16(srch16, sr, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_sr_pk16_fp6_bf16(srcbf16, sr, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_sr_pk16_fp6_f16(srch16, sr, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_sr_pk16_bf6_f32(srcf16, sr, scale); + *out3 = __builtin_amdgcn_cvt_scalef32_sr_pk16_fp6_f32(srcf16, sr, scale); } // CHECK-LABEL: @test_sat_pk4_i4_i8( @@ -870,6 +1184,61 @@ void test_permlane_idx_gen(global uint* out, uint src0, uint src1) { *out = __builtin_amdgcn_permlane_idx_gen(src0, src1); } +// CHECK-LABEL: @test_perm_pk( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[A32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[A64_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[B32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[B64_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[C_ADDR:%.*]] = alloca <2 x i32>, align 8, addrspace(5) +// CHECK-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[OUT3_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[OUT4_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A32_ADDR]] to ptr +// CHECK-NEXT: [[A64_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A64_ADDR]] to ptr +// CHECK-NEXT: [[B32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B32_ADDR]] to ptr +// CHECK-NEXT: [[B64_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B64_ADDR]] to ptr +// CHECK-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-NEXT: [[OUT2_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT2_ADDR]] to ptr +// CHECK-NEXT: [[OUT3_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT3_ADDR]] to ptr +// CHECK-NEXT: [[OUT4_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT4_ADDR]] to ptr +// CHECK-NEXT: store i32 [[A32:%.*]], ptr [[A32_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[A64:%.*]], ptr [[A64_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[B32:%.*]], ptr [[B32_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[B64:%.*]], ptr [[B64_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store <2 x i32> [[C:%.*]], ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[OUT2:%.*]], ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[OUT3:%.*]], ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[OUT4:%.*]], ptr [[OUT4_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A32_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B32_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.amdgcn.perm.pk16.b4.u4(i32 [[TMP0]], i32 [[TMP1]], <2 x i32> [[TMP2]]) +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <2 x i32> [[TMP3]], ptr [[TMP4]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[A32_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[B64_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[CONV:%.*]] = zext i32 [[TMP6]] to i64 +// CHECK-NEXT: [[TMP7:%.*]] = load <2 x i32>, ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = call <3 x i32> @llvm.amdgcn.perm.pk16.b6.u4(i32 [[TMP5]], i64 [[CONV]], <2 x i32> [[TMP7]]) +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OUT3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <3 x i32> [[TMP8]], ptr [[TMP9]], align 16 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[A64_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[CONV1:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[B64_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[CONV2:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK-NEXT: [[TMP12:%.*]] = load <2 x i32>, ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = call <4 x i32> @llvm.amdgcn.perm.pk16.b8.u4(i64 [[CONV1]], i64 [[CONV2]], <2 x i32> [[TMP12]]) +// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[OUT4_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP14]], align 16 +// CHECK-NEXT: ret void +// +void test_perm_pk(uint a32, uint a64, uint b32, uint b64, uint2 c, uint2 *out2, uint3 *out3, uint4 *out4) { + *out2 = __builtin_amdgcn_perm_pk16_b4_u4(a32, b32, c); + *out3 = __builtin_amdgcn_perm_pk16_b6_u4(a32, b64, c); + *out4 = __builtin_amdgcn_perm_pk16_b8_u4(a64, b64, c); +} + // CHECK-LABEL: @test_prefetch( // CHECK-NEXT: entry: // CHECK-NEXT: [[FPTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) diff --git a/clang/test/Driver/HLSL/metal-converter.hlsl b/clang/test/Driver/HLSL/metal-converter.hlsl index 3c4257b..5c139c6 100644 --- a/clang/test/Driver/HLSL/metal-converter.hlsl +++ b/clang/test/Driver/HLSL/metal-converter.hlsl @@ -1,14 +1,15 @@ -// RUN: echo "dxv" > %T/dxv && chmod 754 %T/dxv +// RUN: mkdir -p %t.dir +// RUN: echo "dxv" > %t.dir/dxv && chmod 754 %t.dir/dxv // RUN: env PATH="" %clang_dxc -T cs_6_0 %s -metal -Fo %t.mtl -### 2>&1 | FileCheck --check-prefix=NO_DXV %s // RUN: env PATH="" %clang_dxc -T cs_6_0 %s -metal -Vd -Fo %t.mtl -### 2>&1 | FileCheck --check-prefix=NO_DXV %s -// RUN: env PATH="" %clang_dxc -T cs_6_0 %s --dxv-path=%T -metal -Vd -Fo %t.mtl -### 2>&1 | FileCheck --check-prefix=NO_DXV %s +// RUN: env PATH="" %clang_dxc -T cs_6_0 %s --dxv-path=%t.dir -metal -Vd -Fo %t.mtl -### 2>&1 | FileCheck --check-prefix=NO_DXV %s // NO_DXV: "{{.*}}metal-shaderconverter{{(.exe)?}}" "{{.*}}.obj" "-o" "{{.*}}.mtl" // RUN: %clang_dxc -T cs_6_0 %s -metal -### 2>&1 | FileCheck --check-prefix=NO_MTL %s // NO_MTL-NOT: metal-shaderconverter -// RUN: %clang_dxc -T cs_6_0 %s --dxv-path=%T -metal -Fo %t.mtl -### 2>&1 | FileCheck --check-prefix=DXV %s +// RUN: %clang_dxc -T cs_6_0 %s --dxv-path=%t.dir -metal -Fo %t.mtl -### 2>&1 | FileCheck --check-prefix=DXV %s // DXV: "{{.*}}dxv{{(.exe)?}}" "{{.*}}.obj" "-o" "{{.*}}.dxo" // DXV: "{{.*}}metal-shaderconverter{{(.exe)?}}" "{{.*}}.dxo" "-o" "{{.*}}.mtl" diff --git a/clang/test/Driver/baremetal-sysroot.cpp b/clang/test/Driver/baremetal-sysroot.cpp index 47f0616..4c062e2 100644 --- a/clang/test/Driver/baremetal-sysroot.cpp +++ b/clang/test/Driver/baremetal-sysroot.cpp @@ -4,12 +4,12 @@ // Test that when a --sysroot is not provided, driver picks the default // location correctly if available. -// RUN: rm -rf %T/baremetal_default_sysroot -// RUN: mkdir -p %T/baremetal_default_sysroot/bin -// RUN: mkdir -p %T/baremetal_default_sysroot/lib/clang-runtimes/armv6m-none-eabi -// RUN: ln -s %clang %T/baremetal_default_sysroot/bin/clang +// RUN: rm -rf %t.dir/baremetal_default_sysroot +// RUN: mkdir -p %t.dir/baremetal_default_sysroot/bin +// RUN: mkdir -p %t.dir/baremetal_default_sysroot/lib/clang-runtimes/armv6m-none-eabi +// RUN: ln -s %clang %t.dir/baremetal_default_sysroot/bin/clang -// RUN: %T/baremetal_default_sysroot/bin/clang -no-canonical-prefixes %s -### -o %t.out 2>&1 \ +// RUN: %t.dir/baremetal_default_sysroot/bin/clang -no-canonical-prefixes %s -### -o %t.out 2>&1 \ // RUN: -target armv6m-none-eabi --sysroot= \ // RUN: | FileCheck --check-prefix=CHECK-V6M-C %s // CHECK-V6M-C: "{{.*}}clang{{.*}}" "-cc1" "-triple" "thumbv6m-unknown-none-eabi" diff --git a/clang/test/Driver/baremetal.cpp b/clang/test/Driver/baremetal.cpp index 26f030d..7d929fe1 100644 --- a/clang/test/Driver/baremetal.cpp +++ b/clang/test/Driver/baremetal.cpp @@ -126,11 +126,11 @@ // CHECK-V6M-NDL: "-Bstatic" "-m" "armelf" "-EL" // CHECK-V6M-NDL-SAME: "-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}baremetal_arm{{[/\\]+}}lib" -// RUN: rm -rf %T/baremetal_cxx_sysroot -// RUN: mkdir -p %T/baremetal_cxx_sysroot/usr/include/c++/v1 +// RUN: rm -rf %t.dir/baremetal_cxx_sysroot +// RUN: mkdir -p %t.dir/baremetal_cxx_sysroot/usr/include/c++/v1 // RUN: %clangxx %s -### 2>&1 \ // RUN: --target=armv6m-none-eabi \ -// RUN: --sysroot=%T/baremetal_cxx_sysroot \ +// RUN: --sysroot=%t.dir/baremetal_cxx_sysroot \ // RUN: -stdlib=libc++ \ // RUN: | FileCheck --check-prefix=CHECK-V6M-LIBCXX-USR %s // CHECK-V6M-LIBCXX-USR: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" @@ -568,24 +568,24 @@ // Check that compiler-rt library without the arch filename suffix will // be used if present. -// RUN: rm -rf %T/baremetal_clang_rt_noarch -// RUN: mkdir -p %T/baremetal_clang_rt_noarch/lib -// RUN: touch %T/baremetal_clang_rt_noarch/lib/libclang_rt.builtins.a +// RUN: rm -rf %t.dir/baremetal_clang_rt_noarch +// RUN: mkdir -p %t.dir/baremetal_clang_rt_noarch/lib +// RUN: touch %t.dir/baremetal_clang_rt_noarch/lib/libclang_rt.builtins.a // RUN: %clang %s -### 2>&1 \ // RUN: --target=armv6m-none-eabi \ -// RUN: --sysroot=%T/baremetal_clang_rt_noarch \ +// RUN: --sysroot=%t.dir/baremetal_clang_rt_noarch \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-NOARCH %s // CHECK-CLANGRT-NOARCH: "{{[^"]*}}libclang_rt.builtins.a" // CHECK-CLANGRT-NOARCH-NOT: "{{[^"]*}}libclang_rt.builtins.a" // Check that compiler-rt library with the arch filename suffix will be // used if present. -// RUN: rm -rf %T/baremetal_clang_rt_arch -// RUN: mkdir -p %T/baremetal_clang_rt_arch/lib -// RUN: touch %T/baremetal_clang_rt_arch/lib/libclang_rt.builtins-armv6m.a +// RUN: rm -rf %t.dir/baremetal_clang_rt_arch +// RUN: mkdir -p %t.dir/baremetal_clang_rt_arch/lib +// RUN: touch %t.dir/baremetal_clang_rt_arch/lib/libclang_rt.builtins-armv6m.a // RUN: %clang %s -### 2>&1 \ // RUN: --target=armv6m-none-eabi \ -// RUN: --sysroot=%T/baremetal_clang_rt_arch \ +// RUN: --sysroot=%t.dir/baremetal_clang_rt_arch \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-ARCH %s // CHECK-CLANGRT-ARCH: "{{[^"]*}}libclang_rt.builtins.a" // CHECK-CLANGRT-ARCH-NOT: "{{[^"]*}}libclang_rt.builtins.a" diff --git a/clang/test/Driver/check-time-trace-ParseDeclarationOrFunctionDefinition.cpp b/clang/test/Driver/check-time-trace-ParseDeclarationOrFunctionDefinition.cpp index f854cdd..f30e82d 100644 --- a/clang/test/Driver/check-time-trace-ParseDeclarationOrFunctionDefinition.cpp +++ b/clang/test/Driver/check-time-trace-ParseDeclarationOrFunctionDefinition.cpp @@ -1,10 +1,11 @@ -// RUN: %clangxx -S -ftime-trace -ftime-trace-granularity=0 -o %T/check-time-trace-ParseDeclarationOrFunctionDefinition %s -// RUN: cat %T/check-time-trace-ParseDeclarationOrFunctionDefinition.json \ +// RUN: mkdir -p %t.dir +// RUN: %clangxx -S -ftime-trace -ftime-trace-granularity=0 -o %t.dir/check-time-trace-ParseDeclarationOrFunctionDefinition %s +// RUN: cat %t.dir/check-time-trace-ParseDeclarationOrFunctionDefinition.json \ // RUN: | %python -c 'import json, sys; json.dump(json.loads(sys.stdin.read()), sys.stdout, sort_keys=True, indent=2)' \ // RUN: | FileCheck %s // CHECK-DAG: "name": "ParseDeclarationOrFunctionDefinition" -// CHECK-DAG: "detail": "{{.*}}check-time-trace-ParseDeclarationOrFunctionDefinition.cpp:15:1" +// CHECK-DAG: "detail": "{{.*}}check-time-trace-ParseDeclarationOrFunctionDefinition.cpp:16:1" // CHECK-DAG: "name": "ParseFunctionDefinition" // CHECK-DAG: "detail": "foo" // CHECK-DAG: "name": "ParseFunctionDefinition" diff --git a/clang/test/Driver/cl-showfilenames.c b/clang/test/Driver/cl-showfilenames.c index 7320597..077ab815 100644 --- a/clang/test/Driver/cl-showfilenames.c +++ b/clang/test/Driver/cl-showfilenames.c @@ -10,11 +10,12 @@ // There is currently a discussion of this going on at: // https://reviews.llvm.org/D69825 -// RUN: %clang_cl -fno-integrated-cc1 --target=i686-pc-win32 /c /Fo%T/ /showFilenames -- %s 2>&1 | FileCheck -check-prefix=show %s -// RUN: %clang_cl -fno-integrated-cc1 --target=i686-pc-win32 /c /Fo%T/ /showFilenames -- %s %S/Inputs/wildcard*.c 2>&1 | FileCheck -check-prefix=multiple %s +// RUN: mkdir -p %t.dir +// RUN: %clang_cl -fno-integrated-cc1 --target=i686-pc-win32 /c /Fo%t.dir/ /showFilenames -- %s 2>&1 | FileCheck -check-prefix=show %s +// RUN: %clang_cl -fno-integrated-cc1 --target=i686-pc-win32 /c /Fo%t.dir/ /showFilenames -- %s %S/Inputs/wildcard*.c 2>&1 | FileCheck -check-prefix=multiple %s -// RUN: %clang_cl -fno-integrated-cc1 --target=i686-pc-win32 /c /Fo%T/ -- %s 2>&1 | FileCheck -check-prefix=noshow %s -// RUN: %clang_cl -fno-integrated-cc1 --target=i686-pc-win32 /c /Fo%T/ /showFilenames /showFilenames- -- %s 2>&1 | FileCheck -check-prefix=noshow %s +// RUN: %clang_cl -fno-integrated-cc1 --target=i686-pc-win32 /c /Fo%t.dir/ -- %s 2>&1 | FileCheck -check-prefix=noshow %s +// RUN: %clang_cl -fno-integrated-cc1 --target=i686-pc-win32 /c /Fo%t.dir/ /showFilenames /showFilenames- -- %s 2>&1 | FileCheck -check-prefix=noshow %s #pragma message "Hello" diff --git a/clang/test/Driver/clang-offload-bundler.c b/clang/test/Driver/clang-offload-bundler.c index 95ea058..6466e18 100644 --- a/clang/test/Driver/clang-offload-bundler.c +++ b/clang/test/Driver/clang-offload-bundler.c @@ -413,15 +413,16 @@ // bundle and archives them. Therefore for each target, the output is an // archive of unbundled bitcodes. // +// RUN: mkdir -p %t.dir // RUN: clang-offload-bundler -type=bc -targets=hip-amdgcn-amd-amdhsa--gfx900,hip-amdgcn-amd-amdhsa--gfx906 \ -// RUN: -input=%t.tgt1 -input=%t.tgt2 -output=%T/hip_bundle1.bc +// RUN: -input=%t.tgt1 -input=%t.tgt2 -output=%t.dir/hip_bundle1.bc // RUN: clang-offload-bundler -type=bc -targets=hip-amdgcn-amd-amdhsa--gfx900,hip-amdgcn-amd-amdhsa--gfx906 \ -// RUN: -input=%t.tgt1 -input=%t.tgt2 -output=%T/hip_bundle2.bc -// RUN: llvm-ar cr %T/hip_archive.a %T/hip_bundle1.bc %T/hip_bundle2.bc +// RUN: -input=%t.tgt1 -input=%t.tgt2 -output=%t.dir/hip_bundle2.bc +// RUN: llvm-ar cr %t.dir/hip_archive.a %t.dir/hip_bundle1.bc %t.dir/hip_bundle2.bc // RUN: clang-offload-bundler -unbundle -type=a -targets=hip-amdgcn-amd-amdhsa--gfx900,hip-amdgcn-amd-amdhsa--gfx906 \ -// RUN: -output=%T/hip_900.a -output=%T/hip_906.a -input=%T/hip_archive.a -// RUN: llvm-ar t %T/hip_900.a | FileCheck -check-prefix=HIP-AR-900 %s -// RUN: llvm-ar t %T/hip_906.a | FileCheck -check-prefix=HIP-AR-906 %s +// RUN: -output=%t.dir/hip_900.a -output=%t.dir/hip_906.a -input=%t.dir/hip_archive.a +// RUN: llvm-ar t %t.dir/hip_900.a | FileCheck -check-prefix=HIP-AR-900 %s +// RUN: llvm-ar t %t.dir/hip_906.a | FileCheck -check-prefix=HIP-AR-906 %s // HIP-AR-900-DAG: hip_bundle1-hip-amdgcn-amd-amdhsa--gfx900 // HIP-AR-900-DAG: hip_bundle2-hip-amdgcn-amd-amdhsa--gfx900 // HIP-AR-906-DAG: hip_bundle1-hip-amdgcn-amd-amdhsa--gfx906 @@ -553,14 +554,14 @@ // Check compatibility of HIP code objects found in the heterogeneous archive library with OpenMP code objects of the target // RUN: clang-offload-bundler -unbundle -type=a -targets=openmp-amdgcn-amd-amdhsa--gfx906 \ -// RUN: -output=%T/hip-openmp_906.a -input=%T/hip_archive.a -hip-openmp-compatible -// RUN: llvm-ar t %T/hip-openmp_906.a | FileCheck -check-prefix=OPENMPHIPCOMPAT %s +// RUN: -output=%t.dir/hip-openmp_906.a -input=%t.dir/hip_archive.a -hip-openmp-compatible +// RUN: llvm-ar t %t.dir/hip-openmp_906.a | FileCheck -check-prefix=OPENMPHIPCOMPAT %s // OPENMPHIPCOMPAT: hip_bundle1-hip-amdgcn-amd-amdhsa--gfx906 // Check if a malformat bundle id can be detected and an error can be emitted. -// RUN: not clang-offload-bundler -unbundle -type=a -targets=openmp-amdgcn-amd-amdhsa -output=%T/hip-openmp_906.a -input=%T/hip_archive.a -hip-openmp-compatible 2>&1 | FileCheck %s -check-prefix=ERROR-WRONG-FORMAT +// RUN: not clang-offload-bundler -unbundle -type=a -targets=openmp-amdgcn-amd-amdhsa -output=%t.dir/hip-openmp_906.a -input=%t.dir/hip_archive.a -hip-openmp-compatible 2>&1 | FileCheck %s -check-prefix=ERROR-WRONG-FORMAT // ERROR-WRONG-FORMAT: error: Targets need to follow the format '<offload kind>-<target triple>', where '<target triple>' follows the format '<kind>-<arch>-<vendor>-<os>-<env>[-<target id>[:target features]]'. -// RUN: not clang-offload-bundler -unbundle -type=a -targets=openmp-amdgcn-amd-amdhsa-gfx906 -output=%T/hip-openmp_906.a -input=%T/hip_archive.a -hip-openmp-compatible 2>&1 | FileCheck %s -check-prefix=ERROR-NO-ENV +// RUN: not clang-offload-bundler -unbundle -type=a -targets=openmp-amdgcn-amd-amdhsa-gfx906 -output=%t.dir/hip-openmp_906.a -input=%t.dir/hip_archive.a -hip-openmp-compatible 2>&1 | FileCheck %s -check-prefix=ERROR-NO-ENV // ERROR-NO-ENV: error: no compatible code object found for the target 'openmp-amdgcn-amd-amdhsa--' // Some code so that we can create a binary out of this file. diff --git a/clang/test/Driver/clang-sycl-linker-test.cpp b/clang/test/Driver/clang-sycl-linker-test.cpp index b443433..8d26dc0 100644 --- a/clang/test/Driver/clang-sycl-linker-test.cpp +++ b/clang/test/Driver/clang-sycl-linker-test.cpp @@ -11,9 +11,10 @@ // SIMPLE-FO-NEXT: SPIR-V Backend: input: [[LLVMLINKOUT]].bc, output: a_0.spv // // Test the dry run of a simple case with device library files specified. -// RUN: touch %T/lib1.bc -// RUN: touch %T/lib2.bc -// RUN: clang-sycl-linker --dry-run -v -triple=spirv64 %t_1.bc %t_2.bc --library-path=%T --device-libs=lib1.bc,lib2.bc -o a.spv 2>&1 \ +// RUN: mkdir -p %t.dir +// RUN: touch %t.dir/lib1.bc +// RUN: touch %t.dir/lib2.bc +// RUN: clang-sycl-linker --dry-run -v -triple=spirv64 %t_1.bc %t_2.bc --library-path=%t.dir --device-libs=lib1.bc,lib2.bc -o a.spv 2>&1 \ // RUN: | FileCheck %s --check-prefix=DEVLIBS // DEVLIBS: sycl-device-link: inputs: {{.*}}.bc libfiles: {{.*}}lib1.bc, {{.*}}lib2.bc output: [[LLVMLINKOUT:.*]].bc // DEVLIBS-NEXT: SPIR-V Backend: input: [[LLVMLINKOUT]].bc, output: a_0.spv @@ -25,10 +26,10 @@ // FILETYPEERROR: Unsupported file type // // Test to see if device library related errors are emitted. -// RUN: not clang-sycl-linker --dry-run -triple=spirv64 %t_1.bc %t_2.bc --library-path=%T --device-libs= -o a.spv 2>&1 \ +// RUN: not clang-sycl-linker --dry-run -triple=spirv64 %t_1.bc %t_2.bc --library-path=%t.dir --device-libs= -o a.spv 2>&1 \ // RUN: | FileCheck %s --check-prefix=DEVLIBSERR1 // DEVLIBSERR1: Number of device library files cannot be zero -// RUN: not clang-sycl-linker --dry-run -triple=spirv64 %t_1.bc %t_2.bc --library-path=%T --device-libs=lib1.bc,lib2.bc,lib3.bc -o a.spv 2>&1 \ +// RUN: not clang-sycl-linker --dry-run -triple=spirv64 %t_1.bc %t_2.bc --library-path=%t.dir --device-libs=lib1.bc,lib2.bc,lib3.bc -o a.spv 2>&1 \ // RUN: | FileCheck %s --check-prefix=DEVLIBSERR2 // DEVLIBSERR2: '{{.*}}lib3.bc' SYCL device library file is not found // diff --git a/clang/test/Driver/dxc_dxv_path.hlsl b/clang/test/Driver/dxc_dxv_path.hlsl index 65e386f..eab135c 100644 --- a/clang/test/Driver/dxc_dxv_path.hlsl +++ b/clang/test/Driver/dxc_dxv_path.hlsl @@ -1,20 +1,21 @@ -// RUN: env PATH="" %clang_dxc -I test -Tlib_6_3 -Fo %T/a.dxo -### %s 2>&1 | FileCheck %s +// RUN: mkdir -p %t.dir +// RUN: env PATH="" %clang_dxc -I test -Tlib_6_3 -Fo %t.dir/a.dxo -### %s 2>&1 | FileCheck %s // Make sure report warning. // CHECK:dxv not found -// RUN: echo "dxv" > %T/dxv && chmod 754 %T/dxv && %clang_dxc --dxv-path=%T %s -Tlib_6_3 -Fo %T/a.dxo -### 2>&1 | FileCheck %s --check-prefix=DXV_PATH +// RUN: echo "dxv" > %t.dir/dxv && chmod 754 %t.dir/dxv && %clang_dxc --dxv-path=%t.dir %s -Tlib_6_3 -Fo %t.dir/a.dxo -### 2>&1 | FileCheck %s --check-prefix=DXV_PATH // DXV_PATH:dxv{{(.exe)?}}" "{{.*}}.obj" "-o" "{{.*}}/a.dxo" // RUN: %clang_dxc -I test -Vd -Tlib_6_3 -### %s 2>&1 | FileCheck %s --check-prefix=VD // VD:"-cc1"{{.*}}"-triple" "dxilv1.3-unknown-shadermodel6.3-library" // VD-NOT:dxv not found -// RUN: %clang_dxc -Tlib_6_3 -ccc-print-bindings --dxv-path=%T -Fo %t.dxo %s 2>&1 | FileCheck %s --check-prefix=BINDINGS +// RUN: %clang_dxc -Tlib_6_3 -ccc-print-bindings --dxv-path=%t.dir -Fo %t.dxo %s 2>&1 | FileCheck %s --check-prefix=BINDINGS // BINDINGS: "dxilv1.3-unknown-shadermodel6.3-library" - "clang", inputs: ["[[INPUT:.+]]"], output: "[[obj:.+]].obj" // BINDINGS-NEXT: "dxilv1.3-unknown-shadermodel6.3-library" - "hlsl::Validator", inputs: ["[[obj]].obj"], output: "{{.+}}.dxo" -// RUN: %clang_dxc -Tlib_6_3 -ccc-print-phases --dxv-path=%T -Fo %t.dxc %s 2>&1 | FileCheck %s --check-prefix=PHASES +// RUN: %clang_dxc -Tlib_6_3 -ccc-print-phases --dxv-path=%t.dir -Fo %t.dxc %s 2>&1 | FileCheck %s --check-prefix=PHASES // PHASES: 0: input, "[[INPUT:.+]]", hlsl // PHASES-NEXT: 1: preprocessor, {0}, c++-cpp-output diff --git a/clang/test/Driver/mingw-sysroot.cpp b/clang/test/Driver/mingw-sysroot.cpp index de5cded..0ba2f33 100644 --- a/clang/test/Driver/mingw-sysroot.cpp +++ b/clang/test/Driver/mingw-sysroot.cpp @@ -1,29 +1,29 @@ // REQUIRES: shell // UNSUPPORTED: system-windows -// RUN: rm -rf %T/testroot-gcc -// RUN: mkdir -p %T/testroot-gcc/bin -// RUN: ln -s %clang %T/testroot-gcc/bin/x86_64-w64-mingw32-gcc -// RUN: ln -s %clang %T/testroot-gcc/bin/x86_64-w64-mingw32-clang -// RUN: ln -s %S/Inputs/mingw_ubuntu_posix_tree/usr/x86_64-w64-mingw32 %T/testroot-gcc/x86_64-w64-mingw32 -// RUN: ln -s %S/Inputs/mingw_ubuntu_posix_tree/usr/lib %T/testroot-gcc/lib - -// RUN: rm -rf %T/testroot-clang -// RUN: mkdir -p %T/testroot-clang/bin -// RUN: ln -s %clang %T/testroot-clang/bin/x86_64-w64-mingw32-clang -// RUN: ln -s %S/Inputs/mingw_ubuntu_posix_tree/usr/x86_64-w64-mingw32 %T/testroot-clang/x86_64-w64-mingw32 -// RUN: ln -s %S/Inputs/mingw_arch_tree/usr/i686-w64-mingw32 %T/testroot-clang/i686-w64-mingw32 - -// RUN: rm -rf %T/testroot-clang-native -// RUN: mkdir -p %T/testroot-clang-native/bin -// RUN: ln -s %clang %T/testroot-clang-native/bin/clang -// RUN: mkdir -p %T/testroot-clang-native/include/_mingw.h -// RUN: mkdir -p %T/testroot-clang-native/lib/libkernel32.a - -// RUN: rm -rf %T/testroot-custom-triple -// RUN: mkdir -p %T/testroot-custom-triple/bin -// RUN: ln -s %clang %T/testroot-custom-triple/bin/clang -// RUN: ln -s %S/Inputs/mingw_ubuntu_posix_tree/usr/x86_64-w64-mingw32 %T/testroot-custom-triple/x86_64-w64-mingw32foo +// RUN: rm -rf %t.dir/testroot-gcc +// RUN: mkdir -p %t.dir/testroot-gcc/bin +// RUN: ln -s %clang %t.dir/testroot-gcc/bin/x86_64-w64-mingw32-gcc +// RUN: ln -s %clang %t.dir/testroot-gcc/bin/x86_64-w64-mingw32-clang +// RUN: ln -s %S/Inputs/mingw_ubuntu_posix_tree/usr/x86_64-w64-mingw32 %t.dir/testroot-gcc/x86_64-w64-mingw32 +// RUN: ln -s %S/Inputs/mingw_ubuntu_posix_tree/usr/lib %t.dir/testroot-gcc/lib + +// RUN: rm -rf %t.dir/testroot-clang +// RUN: mkdir -p %t.dir/testroot-clang/bin +// RUN: ln -s %clang %t.dir/testroot-clang/bin/x86_64-w64-mingw32-clang +// RUN: ln -s %S/Inputs/mingw_ubuntu_posix_tree/usr/x86_64-w64-mingw32 %t.dir/testroot-clang/x86_64-w64-mingw32 +// RUN: ln -s %S/Inputs/mingw_arch_tree/usr/i686-w64-mingw32 %t.dir/testroot-clang/i686-w64-mingw32 + +// RUN: rm -rf %t.dir/testroot-clang-native +// RUN: mkdir -p %t.dir/testroot-clang-native/bin +// RUN: ln -s %clang %t.dir/testroot-clang-native/bin/clang +// RUN: mkdir -p %t.dir/testroot-clang-native/include/_mingw.h +// RUN: mkdir -p %t.dir/testroot-clang-native/lib/libkernel32.a + +// RUN: rm -rf %t.dir/testroot-custom-triple +// RUN: mkdir -p %t.dir/testroot-custom-triple/bin +// RUN: ln -s %clang %t.dir/testroot-custom-triple/bin/clang +// RUN: ln -s %S/Inputs/mingw_ubuntu_posix_tree/usr/x86_64-w64-mingw32 %t.dir/testroot-custom-triple/x86_64-w64-mingw32foo // If we find a gcc in the path with the right triplet prefix, pick that as // sysroot: @@ -33,7 +33,7 @@ // directory to the path - this would end up including /usr/include for // cross toolchains installed in /usr. -// RUN: env "PATH=%T/testroot-gcc/bin:%PATH%" %clang --target=x86_64-w64-mingw32 -rtlib=platform -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_GCC %s --implicit-check-not="\"{{.*}}/testroot-gcc{{/|\\\\}}include\"" +// RUN: env "PATH=%t.dir/testroot-gcc/bin:%PATH%" %clang --target=x86_64-w64-mingw32 -rtlib=platform -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_GCC %s --implicit-check-not="\"{{.*}}/testroot-gcc{{/|\\\\}}include\"" // CHECK_TESTROOT_GCC: "-internal-isystem" "[[BASE:[^"]+]]/testroot-gcc{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}x86_64-w64-mingw32{{/|\\\\}}10.2-posix{{/|\\\\}}include{{/|\\\\}}c++" // CHECK_TESTROOT_GCC-SAME: {{^}} "-internal-isystem" "[[BASE]]/testroot-gcc{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}x86_64-w64-mingw32{{/|\\\\}}10.2-posix{{/|\\\\}}include{{/|\\\\}}c++{{/|\\\\}}x86_64-w64-mingw32" // CHECK_TESTROOT_GCC-SAME: {{^}} "-internal-isystem" "[[BASE]]/testroot-gcc{{/|\\\\}}lib{{/|\\\\}}gcc{{/|\\\\}}x86_64-w64-mingw32{{/|\\\\}}10.2-posix{{/|\\\\}}include{{/|\\\\}}c++{{/|\\\\}}backward" @@ -45,7 +45,7 @@ // If we pass --sysroot explicitly, then we do include <sysroot>/include // even when cross compiling. -// RUN: %clang --target=x86_64-w64-mingw32 -rtlib=platform -stdlib=libstdc++ --sysroot="%T/testroot-gcc" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_GCC_EXPLICIT %s +// RUN: %clang --target=x86_64-w64-mingw32 -rtlib=platform -stdlib=libstdc++ --sysroot="%t.dir/testroot-gcc" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_GCC_EXPLICIT %s // CHECK_TESTROOT_GCC_EXPLICIT: "-internal-isystem" "{{[^"]+}}/testroot-gcc{{/|\\\\}}include" @@ -53,8 +53,8 @@ // If -no-canonical-prefixes and there's a matching sysroot next to the clang binary itself, prefer that // over a gcc in the path: -// RUN: env "PATH=%T/testroot-gcc/bin:%PATH%" %T/testroot-clang/bin/x86_64-w64-mingw32-clang --target=x86_64-w64-mingw32 -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_GCC2 %s -// RUN: env "PATH=%T/testroot-gcc/bin:%PATH%" %T/testroot-clang/bin/x86_64-w64-mingw32-clang --target=x86_64-w64-mingw32 -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s -no-canonical-prefixes 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_CLANG %s +// RUN: env "PATH=%t.dir/testroot-gcc/bin:%PATH%" %t.dir/testroot-clang/bin/x86_64-w64-mingw32-clang --target=x86_64-w64-mingw32 -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_GCC2 %s +// RUN: env "PATH=%t.dir/testroot-gcc/bin:%PATH%" %t.dir/testroot-clang/bin/x86_64-w64-mingw32-clang --target=x86_64-w64-mingw32 -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s -no-canonical-prefixes 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_CLANG %s // CHECK_TESTROOT_GCC2: "{{[^"]+}}/testroot-gcc{{/|\\\\}}x86_64-w64-mingw32{{/|\\\\}}include" // CHECK_TESTROOT_CLANG: "{{[^"]+}}/testroot-clang{{/|\\\\}}x86_64-w64-mingw32{{/|\\\\}}include" @@ -63,7 +63,7 @@ // happens to be in the same directory as gcc, make sure we still can pick up // the libgcc directory: -// RUN: env "PATH=%T/testroot-gcc/bin:%PATH%" %T/testroot-gcc/bin/x86_64-w64-mingw32-clang --target=x86_64-w64-mingw32 -rtlib=platform -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_GCC %s +// RUN: env "PATH=%t.dir/testroot-gcc/bin:%PATH%" %t.dir/testroot-gcc/bin/x86_64-w64-mingw32-clang --target=x86_64-w64-mingw32 -rtlib=platform -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_GCC %s // If we're executing clang from a directory with what looks like a mingw sysroot, @@ -84,7 +84,7 @@ // that indicates that we did choose the right base, even if this particular directory // actually doesn't exist here. -// RUN: env "PATH=%T/testroot-gcc/bin:%PATH%" %T/testroot-clang-native/bin/clang -no-canonical-prefixes --target=x86_64-w64-mingw32 -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_CLANG_NATIVE %s +// RUN: env "PATH=%t.dir/testroot-gcc/bin:%PATH%" %t.dir/testroot-clang-native/bin/clang -no-canonical-prefixes --target=x86_64-w64-mingw32 -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_CLANG_NATIVE %s // CHECK_TESTROOT_CLANG_NATIVE: "{{[^"]+}}/testroot-clang-native{{/|\\\\}}x86_64-w64-mingw32{{/|\\\\}}include" @@ -95,12 +95,12 @@ // that defaults to x86_64 mingw, but it's easier to test this in cross setups // with symlinks, like the other tests here.) -// RUN: env "PATH=%T/testroot-gcc/bin:%PATH%" %T/testroot-clang/bin/x86_64-w64-mingw32-clang -no-canonical-prefixes --target=x86_64-w64-mingw32 -m32 -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_CLANG_I686 %s +// RUN: env "PATH=%t.dir/testroot-gcc/bin:%PATH%" %t.dir/testroot-clang/bin/x86_64-w64-mingw32-clang -no-canonical-prefixes --target=x86_64-w64-mingw32 -m32 -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_CLANG_I686 %s // CHECK_TESTROOT_CLANG_I686: "{{[^"]+}}/testroot-clang{{/|\\\\}}i686-w64-mingw32{{/|\\\\}}include" // If the user calls clang with a custom literal triple, make sure this maps // to sysroots with the matching spelling. -// RUN: %T/testroot-custom-triple/bin/clang -no-canonical-prefixes --target=x86_64-w64-mingw32foo -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_CUSTOM_TRIPLE %s +// RUN: %t.dir/testroot-custom-triple/bin/clang -no-canonical-prefixes --target=x86_64-w64-mingw32foo -rtlib=compiler-rt -stdlib=libstdc++ --sysroot="" -c -### %s 2>&1 | FileCheck -check-prefix=CHECK_TESTROOT_CUSTOM_TRIPLE %s // CHECK_TESTROOT_CUSTOM_TRIPLE: "{{[^"]+}}/testroot-custom-triple{{/|\\\\}}x86_64-w64-mingw32foo{{/|\\\\}}include" diff --git a/clang/test/FixIt/fixit-c++17.cpp b/clang/test/FixIt/fixit-c++17.cpp new file mode 100644 index 0000000..26c3bb9 --- /dev/null +++ b/clang/test/FixIt/fixit-c++17.cpp @@ -0,0 +1,29 @@ +// RUN: %clang_cc1 -verify -std=c++17 -pedantic-errors %s +// RUN: cp %s %t +// RUN: not %clang_cc1 -x c++ -std=c++17 -fixit %t +// RUN: %clang_cc1 -Wall -pedantic-errors -x c++ -std=c++17 %t + +/* This is a test of the various code modification hints that only + apply in C++17. */ +template<int... args> +int foo() { + int a = (args + 1 + ...); // expected-error {{expression not permitted as operand of fold expression}} + // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:14-[[@LINE-1]]:14}:"(" + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:22-[[@LINE-2]]:22}:")" + int b = (args + 123 + ...); // expected-error {{expression not permitted as operand of fold expression}} + // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:14-[[@LINE-1]]:14}:"(" + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:24-[[@LINE-2]]:24}:")" + int c = (args + 1 + 2 + ...); // expected-error {{expression not permitted as operand of fold expression}} + // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:14-[[@LINE-1]]:14}:"(" + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:26-[[@LINE-2]]:26}:")" + int e = (... + 1 + args); // expected-error {{expression not permitted as operand of fold expression}} + // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:20-[[@LINE-1]]:20}:"(" + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:28-[[@LINE-2]]:28}:")" + int f = (1 + ... + args + 1); // expected-error {{expression not permitted as operand of fold expression}} + // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:24-[[@LINE-1]]:24}:"(" + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:32-[[@LINE-2]]:32}:")" + int g = (args + 1 + ... + 1); // expected-error {{expression not permitted as operand of fold expression}} + // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:14-[[@LINE-1]]:14}:"(" + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:22-[[@LINE-2]]:22}:")" + return a + b + c + e + f + g; +} diff --git a/clang/test/Modules/implicit-module-header-maps.cpp b/clang/test/Modules/implicit-module-header-maps.cpp index bd4aeb6..6cde927 100644 --- a/clang/test/Modules/implicit-module-header-maps.cpp +++ b/clang/test/Modules/implicit-module-header-maps.cpp @@ -1,5 +1,6 @@ // UNSUPPORTED: system-windows // RUN: rm -rf %t +// RUN: mkdir %t // RUN: split-file %s %t // RUN: cd %t // @@ -7,8 +8,8 @@ // // RUN: %clang -Rmodule-build -fmodules -fimplicit-modules -fimplicit-module-maps -fmodule-map-file=module.modulemap -fsyntax-only -I hmap -fmodules-cache-path=%t test.cpp // -// RUN: cd %T // RUN: rm -rf %t +// RUN: mkdir %t // RUN: split-file %s %t // RUN: cd %t // diff --git a/clang/test/Modules/specializations-lazy-load-parentmap-crash-analyzer.cpp b/clang/test/Modules/specializations-lazy-load-parentmap-crash-analyzer.cpp new file mode 100644 index 0000000..d1e603f --- /dev/null +++ b/clang/test/Modules/specializations-lazy-load-parentmap-crash-analyzer.cpp @@ -0,0 +1,87 @@ +// REQUIRES: staticanalyzer +// +// RUN: rm -rf %t +// RUN: mkdir -p %t +// RUN: split-file --leading-lines %s %t +// +// Prepare the BMIs. +// RUN: %clang_cc1 -std=c++20 -emit-module-interface -o %t/mod_a-part1.pcm %t/mod_a-part1.cppm +// RUN: %clang_cc1 -std=c++20 -emit-module-interface -o %t/mod_a-part2.pcm %t/mod_a-part2.cppm +// RUN: %clang_cc1 -std=c++20 -emit-module-interface -o %t/mod_a.pcm %t/mod_a.cppm -fmodule-file=mod_a:part2=%t/mod_a-part2.pcm -fmodule-file=mod_a:part1=%t/mod_a-part1.pcm +// RUN: %clang_cc1 -std=c++20 -emit-module-interface -o %t/mod_b.pcm %t/mod_b.cppm -fmodule-file=mod_a:part2=%t/mod_a-part2.pcm -fmodule-file=mod_a=%t/mod_a.pcm -fmodule-file=mod_a:part1=%t/mod_a-part1.pcm + +// Trigger the construction of the parent map (which is necessary to trigger the bug this regression test is for) using ArrayBoundV2 checker: +// RUN: %clang_cc1 -std=c++20 -analyze -analyzer-checker=security,alpha.security -analyzer-output=text %t/test-array-bound-v2.cpp -fmodule-file=mod_a:part2=%t/mod_a-part2.pcm -fmodule-file=mod_a=%t/mod_a.pcm -fmodule-file=mod_a:part1=%t/mod_a-part1.pcm -fmodule-file=mod_b=%t/mod_b.pcm + +//--- mod_a-part1.cppm +module; +namespace mod_a { +template <int> struct Important; +} + +namespace mod_a { +Important<0>& instantiate1(); +} // namespace mod_a +export module mod_a:part1; + +export namespace mod_a { +using ::mod_a::instantiate1; +} + +//--- mod_a-part2.cppm +module; +namespace mod_a { +template <int> struct Important; +} + +namespace mod_a { +template <int N> Important<N>& instantiate2(); +namespace part2InternalInstantiations { +// During the construction of the parent map, we iterate over ClassTemplateDecl::specializations() for 'Important'. +// After GH119333, the following instantiations get loaded between the call to spec_begin() and spec_end(). +// This used to invalidate the begin iterator returned by spec_begin() by the time the end iterator is returned. +// This is a regression test for that. +Important<1> fn1(); +Important<2> fn2(); +Important<3> fn3(); +Important<4> fn4(); +Important<5> fn5(); +Important<6> fn6(); +Important<7> fn7(); +Important<8> fn8(); +Important<9> fn9(); +Important<10> fn10(); +Important<11> fn11(); +} +} // namespace mod_a +export module mod_a:part2; + +export namespace mod_a { +using ::mod_a::instantiate2; +} + +//--- mod_a.cppm +export module mod_a; +export import :part1; +export import :part2; + +//--- mod_b.cppm +export module mod_b; +import mod_a; + +void a() { + mod_a::instantiate1(); + mod_a::instantiate2<42>(); +} + +//--- test-array-bound-v2.cpp +import mod_b; + +extern void someFunc(char* first, char* last); +void triggerParentMapContextCreationThroughArrayBoundV2() { + // This code currently causes the ArrayBoundV2 checker to create the ParentMapContext. + // Once it detects an access to buf[100], the checker looks through the parents to find '&' operator. + // (this is needed since taking the address of past-the-end pointer is allowed by the checker) + char buf[100]; + someFunc(&buf[0], &buf[100]); +} diff --git a/clang/test/Modules/specializations-lazy-load-parentmap-crash.cpp b/clang/test/Modules/specializations-lazy-load-parentmap-crash.cpp index bd07ada..e66b052 100644 --- a/clang/test/Modules/specializations-lazy-load-parentmap-crash.cpp +++ b/clang/test/Modules/specializations-lazy-load-parentmap-crash.cpp @@ -8,10 +8,7 @@ // RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -emit-module-interface -o %t/mod_a.pcm %t/mod_a.cppm -fmodule-file=mod_a:part2=%t/mod_a-part2.pcm -fmodule-file=mod_a:part1=%t/mod_a-part1.pcm // RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -emit-module-interface -o %t/mod_b.pcm %t/mod_b.cppm -fmodule-file=mod_a:part2=%t/mod_a-part2.pcm -fmodule-file=mod_a=%t/mod_a.pcm -fmodule-file=mod_a:part1=%t/mod_a-part1.pcm -// Below are two examples to trigger the construction of the parent map (which is necessary to trigger the bug this regression test is for). -// Using ArrayBoundV2 checker: -// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -analyze -analyzer-checker=security,alpha.security -analyzer-output=text %t/test-array-bound-v2.cpp -fmodule-file=mod_a:part2=%t/mod_a-part2.pcm -fmodule-file=mod_a=%t/mod_a.pcm -fmodule-file=mod_a:part1=%t/mod_a-part1.pcm -fmodule-file=mod_b=%t/mod_b.pcm -// Using a sanitized build: +// Trigger the construction of the parent map (which is necessary to trigger the bug this regression test is for) using a sanitized build: // RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fsanitize=unsigned-integer-overflow -fsanitize-undefined-ignore-overflow-pattern=all -emit-llvm -o %t/ignored %t/test-sanitized-build.cpp -fmodule-file=mod_a:part2=%t/mod_a-part2.pcm -fmodule-file=mod_a=%t/mod_a.pcm -fmodule-file=mod_a:part1=%t/mod_a-part1.pcm -fmodule-file=mod_b=%t/mod_b.pcm //--- mod_a-part1.cppm @@ -75,18 +72,6 @@ void a() { mod_a::instantiate2<42>(); } -//--- test-array-bound-v2.cpp -import mod_b; - -extern void someFunc(char* first, char* last); -void triggerParentMapContextCreationThroughArrayBoundV2() { - // This code currently causes the ArrayBoundV2 checker to create the ParentMapContext. - // Once it detects an access to buf[100], the checker looks through the parents to find '&' operator. - // (this is needed since taking the address of past-the-end pointer is allowed by the checker) - char buf[100]; - someFunc(&buf[0], &buf[100]); -} - //--- test-sanitized-build.cpp import mod_b; diff --git a/clang/test/Preprocessor/lang-std.cpp b/clang/test/Preprocessor/lang-std.cpp index 6e9d5e5..ce4fb0a 100644 --- a/clang/test/Preprocessor/lang-std.cpp +++ b/clang/test/Preprocessor/lang-std.cpp @@ -1,14 +1,14 @@ /// Test default standards. -// RUN: %clang_cc1 -dM -E %s | grep __cplusplus >%T-cpp-std.txt -// RUN: FileCheck --input-file %T-cpp-std.txt --check-prefix=CXX17 %s +// RUN: %clang_cc1 -dM -E %s | grep __cplusplus > %t-cpp-std.txt +// RUN: FileCheck --input-file %t-cpp-std.txt --check-prefix=CXX17 %s /// Check that CUDA/HIP uses the same default standards as C++. -// RUN: %clang_cc1 -dM -E -x cuda %s | grep __cplusplus >%T-cuda-std.txt -// RUN: %clang_cc1 -dM -E -x hip %s | grep __cplusplus >%T-hip-std.txt -// RUN: diff %T-cpp-std.txt %T-cuda-std.txt -// RUN: diff %T-cpp-std.txt %T-hip-std.txt +// RUN: %clang_cc1 -dM -E -x cuda %s | grep __cplusplus > %t-cuda-std.txt +// RUN: %clang_cc1 -dM -E -x hip %s | grep __cplusplus > %t-hip-std.txt +// RUN: diff %t-cpp-std.txt %t-cuda-std.txt +// RUN: diff %t-cpp-std.txt %t-hip-std.txt // RUN: %clang_cc1 -dM -E -x cuda -std=c++14 %s | FileCheck --check-prefix=CXX14 %s // RUN: %clang_cc1 -dM -E -x cuda -std=c++17 %s | FileCheck --check-prefix=CXX17 %s diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl index 83c63f1..8f34ccc 100644 --- a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl +++ b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl @@ -57,6 +57,12 @@ void test_cvt_scale_pk(global half8 *outh8, global bfloat8 *outy8, uint2 src2, *outf8 = __builtin_amdgcn_cvt_scale_pk8_f32_fp8(src2, scale, scale_sel); // expected-error {{'__builtin_amdgcn_cvt_scale_pk8_f32_fp8' must be a constant integer}} *outf8 = __builtin_amdgcn_cvt_scale_pk8_f32_bf8(src2, scale, scale_sel); // expected-error {{'__builtin_amdgcn_cvt_scale_pk8_f32_bf8' must be a constant integer}} *outf8 = __builtin_amdgcn_cvt_scale_pk8_f32_fp4(src1, scale, scale_sel); // expected-error {{'__builtin_amdgcn_cvt_scale_pk8_f32_fp4' must be a constant integer}} + *outh16 = __builtin_amdgcn_cvt_scale_pk16_f16_fp6(src3, scale, scale_sel); // expected-error {{'__builtin_amdgcn_cvt_scale_pk16_f16_fp6' must be a constant integer}} + *outy16 = __builtin_amdgcn_cvt_scale_pk16_bf16_fp6(src3, scale, scale_sel); // expected-error {{'__builtin_amdgcn_cvt_scale_pk16_bf16_fp6' must be a constant integer}} + *outh16 = __builtin_amdgcn_cvt_scale_pk16_f16_bf6(src3, scale, scale_sel); // expected-error {{'__builtin_amdgcn_cvt_scale_pk16_f16_bf6' must be a constant integer}} + *outy16 = __builtin_amdgcn_cvt_scale_pk16_bf16_bf6(src3, scale, scale_sel); // expected-error {{'__builtin_amdgcn_cvt_scale_pk16_bf16_bf6' must be a constant integer}} + *outf16 = __builtin_amdgcn_cvt_scale_pk16_f32_fp6(src3, scale, scale_sel); // expected-error {{'__builtin_amdgcn_cvt_scale_pk16_f32_fp6' must be a constant integer}} + *outf16 = __builtin_amdgcn_cvt_scale_pk16_f32_bf6(src3, scale, scale_sel); // expected-error {{'__builtin_amdgcn_cvt_scale_pk16_f32_bf6' must be a constant integer}} *outh8 = __builtin_amdgcn_cvt_scale_pk8_f16_fp8(src2, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} *outy8 = __builtin_amdgcn_cvt_scale_pk8_bf16_fp8(src2, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} @@ -67,6 +73,12 @@ void test_cvt_scale_pk(global half8 *outh8, global bfloat8 *outy8, uint2 src2, *outf8 = __builtin_amdgcn_cvt_scale_pk8_f32_fp8(src2, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} *outf8 = __builtin_amdgcn_cvt_scale_pk8_f32_bf8(src2, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} *outf8 = __builtin_amdgcn_cvt_scale_pk8_f32_fp4(src1, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + *outh16 = __builtin_amdgcn_cvt_scale_pk16_f16_fp6(src3, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + *outy16 = __builtin_amdgcn_cvt_scale_pk16_bf16_fp6(src3, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + *outh16 = __builtin_amdgcn_cvt_scale_pk16_f16_bf6(src3, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + *outy16 = __builtin_amdgcn_cvt_scale_pk16_bf16_bf6(src3, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + *outf16 = __builtin_amdgcn_cvt_scale_pk16_f32_fp6(src3, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + *outf16 = __builtin_amdgcn_cvt_scale_pk16_f32_bf6(src3, scale, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} } void test_amdgcn_load_monitor(global int* b32gaddr, global v2i* b64gaddr, global v4i* b128gaddr, int *b32faddr, v2i* b64faddr, v4i *b128faddr, diff --git a/clang/tools/clang-installapi/ClangInstallAPI.cpp b/clang/tools/clang-installapi/ClangInstallAPI.cpp index 70091fc..1edb64a 100644 --- a/clang/tools/clang-installapi/ClangInstallAPI.cpp +++ b/clang/tools/clang-installapi/ClangInstallAPI.cpp @@ -89,8 +89,9 @@ static bool run(ArrayRef<const char *> Args, const char *ProgName) { auto InMemoryFileSystem = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); OverlayFileSystem->pushOverlay(InMemoryFileSystem); - IntrusiveRefCntPtr<clang::FileManager> FM( - new FileManager(clang::FileSystemOptions(), OverlayFileSystem)); + IntrusiveRefCntPtr<clang::FileManager> FM = + llvm::makeIntrusiveRefCnt<FileManager>(clang::FileSystemOptions(), + OverlayFileSystem); // Capture all options and diagnose any errors. Options Opts(*Diag, FM.get(), Args, ProgName); @@ -113,7 +114,7 @@ static bool run(ArrayRef<const char *> Args, const char *ProgName) { // Set up compilation. std::unique_ptr<CompilerInstance> CI(new CompilerInstance()); - CI->setFileManager(FM.get()); + CI->setFileManager(FM); CI->createDiagnostics(FM->getVirtualFileSystem()); if (!CI->hasDiagnostics()) return EXIT_FAILURE; diff --git a/clang/tools/libclang/CIndexCodeCompletion.cpp b/clang/tools/libclang/CIndexCodeCompletion.cpp index adac7c3..81448b4 100644 --- a/clang/tools/libclang/CIndexCodeCompletion.cpp +++ b/clang/tools/libclang/CIndexCodeCompletion.cpp @@ -360,7 +360,8 @@ AllocatedCXCodeCompleteResults::AllocatedCXCodeCompleteResults( Diag(llvm::makeIntrusiveRefCnt<DiagnosticsEngine>(DiagnosticIDs::create(), DiagOpts)), FileMgr(std::move(FileMgr)), - SourceMgr(new SourceManager(*Diag, *this->FileMgr)), + SourceMgr( + llvm::makeIntrusiveRefCnt<SourceManager>(*Diag, *this->FileMgr)), CodeCompletionAllocator( std::make_shared<clang::GlobalCodeCompletionAllocator>()), Contexts(CXCompletionContext_Unknown), @@ -736,8 +737,8 @@ clang_codeCompleteAt_Impl(CXTranslationUnit TU, const char *complete_filename, } // Parse the resulting source file to find code-completion results. - AllocatedCXCodeCompleteResults *Results = new AllocatedCXCodeCompleteResults( - &AST->getFileManager()); + AllocatedCXCodeCompleteResults *Results = + new AllocatedCXCodeCompleteResults(AST->getFileManagerPtr()); Results->Results = nullptr; Results->NumResults = 0; @@ -764,7 +765,7 @@ clang_codeCompleteAt_Impl(CXTranslationUnit TU, const char *complete_filename, (options & CXCodeComplete_IncludeCodePatterns), IncludeBriefComments, Capture, CXXIdx->getPCHContainerOperations(), Results->Diag, - Results->LangOpts, *Results->SourceMgr, *Results->FileMgr, + Results->LangOpts, Results->SourceMgr, Results->FileMgr, Results->Diagnostics, Results->TemporaryBuffers, /*SyntaxOnlyAction=*/nullptr); diff --git a/clang/tools/libclang/CXIndexDataConsumer.cpp b/clang/tools/libclang/CXIndexDataConsumer.cpp index f0d92e8c..73d04b8 100644 --- a/clang/tools/libclang/CXIndexDataConsumer.cpp +++ b/clang/tools/libclang/CXIndexDataConsumer.cpp @@ -415,9 +415,9 @@ const char *ScratchAlloc::copyCStr(StringRef Str) { return buf; } -void CXIndexDataConsumer::setASTContext(ASTContext &ctx) { - Ctx = &ctx; - cxtu::getASTUnit(CXTU)->setASTContext(&ctx); +void CXIndexDataConsumer::setASTContext(IntrusiveRefCntPtr<ASTContext> ctx) { + Ctx = ctx.get(); + cxtu::getASTUnit(CXTU)->setASTContext(std::move(ctx)); } void CXIndexDataConsumer::setPreprocessor(std::shared_ptr<Preprocessor> PP) { diff --git a/clang/tools/libclang/CXIndexDataConsumer.h b/clang/tools/libclang/CXIndexDataConsumer.h index 54a3add..b207db7 100644 --- a/clang/tools/libclang/CXIndexDataConsumer.h +++ b/clang/tools/libclang/CXIndexDataConsumer.h @@ -339,7 +339,7 @@ public: ASTContext &getASTContext() const { return *Ctx; } CXTranslationUnit getCXTU() const { return CXTU; } - void setASTContext(ASTContext &ctx); + void setASTContext(llvm::IntrusiveRefCntPtr<ASTContext> ctx); void setPreprocessor(std::shared_ptr<Preprocessor> PP) override; bool shouldSuppressRefs() const { diff --git a/clang/tools/libclang/Indexing.cpp b/clang/tools/libclang/Indexing.cpp index 32a7147a..c142f14 100644 --- a/clang/tools/libclang/Indexing.cpp +++ b/clang/tools/libclang/Indexing.cpp @@ -304,7 +304,8 @@ public: : DataConsumer(dataConsumer) {} void Initialize(ASTContext &Context) override { - DataConsumer.setASTContext(Context); + // TODO: accept Context as IntrusiveRefCntPtr? + DataConsumer.setASTContext(&Context); DataConsumer.startedTranslationUnit(); } @@ -355,7 +356,7 @@ public: DataConsumer->importedPCH(*File); } - DataConsumer->setASTContext(CI.getASTContext()); + DataConsumer->setASTContext(CI.getASTContextPtr()); Preprocessor &PP = CI.getPreprocessor(); PP.addPPCallbacks(std::make_unique<IndexPPCallbacks>(PP, *DataConsumer)); DataConsumer->setPreprocessor(CI.getPreprocessorPtr()); @@ -706,7 +707,7 @@ static CXErrorCode clang_indexTranslationUnit_Impl( else DataConsumer.enteredMainFile(std::nullopt); - DataConsumer.setASTContext(Unit->getASTContext()); + DataConsumer.setASTContext(Unit->getASTContextPtr()); DataConsumer.startedTranslationUnit(); indexPreprocessingRecord(*Unit, DataConsumer); diff --git a/clang/unittests/AST/ASTImporterTest.cpp b/clang/unittests/AST/ASTImporterTest.cpp index c0fb642..ac38300 100644 --- a/clang/unittests/AST/ASTImporterTest.cpp +++ b/clang/unittests/AST/ASTImporterTest.cpp @@ -6976,7 +6976,8 @@ TEST_P(LLDBLookupTest, ImporterShouldFindInTransparentContext) { // Set up DeclContextBits.HasLazyExternalLexicalLookups to true. ToTU->setMustBuildLookupTable(); struct TestExternalASTSource : ExternalASTSource {}; - ToTU->getASTContext().setExternalSource(new TestExternalASTSource()); + ToTU->getASTContext().setExternalSource( + llvm::makeIntrusiveRefCnt<TestExternalASTSource>()); Decl *FromTU = getTuDecl( R"( @@ -8154,8 +8155,8 @@ TEST_P(ImportWithExternalSource, CompleteRecordBeforeImporting) { // Create and add the test ExternalASTSource. std::vector<clang::TagDecl *> CompletedTags; - IntrusiveRefCntPtr<ExternalASTSource> source = - new SourceWithCompletedTagList(CompletedTags); + auto source = + llvm::makeIntrusiveRefCnt<SourceWithCompletedTagList>(CompletedTags); clang::ASTContext &Context = FromTU->getASTContext(); Context.setExternalSource(std::move(source)); diff --git a/clang/unittests/AST/ExternalASTSourceTest.cpp b/clang/unittests/AST/ExternalASTSourceTest.cpp index 11715bb..21d4ce4 100644 --- a/clang/unittests/AST/ExternalASTSourceTest.cpp +++ b/clang/unittests/AST/ExternalASTSourceTest.cpp @@ -26,7 +26,8 @@ using namespace llvm; class TestFrontendAction : public ASTFrontendAction { public: - TestFrontendAction(ExternalASTSource *Source) : Source(Source) {} + TestFrontendAction(IntrusiveRefCntPtr<ExternalASTSource> Source) + : Source(std::move(Source)) {} private: void ExecuteAction() override { @@ -44,7 +45,8 @@ private: IntrusiveRefCntPtr<ExternalASTSource> Source; }; -bool testExternalASTSource(ExternalASTSource *Source, StringRef FileContents) { +bool testExternalASTSource(llvm::IntrusiveRefCntPtr<ExternalASTSource> Source, + StringRef FileContents) { auto Invocation = std::make_shared<CompilerInvocation>(); Invocation->getPreprocessorOpts().addRemappedFile( @@ -80,6 +82,7 @@ TEST(ExternalASTSourceTest, FailedLookupOccursOnce) { }; unsigned Calls = 0; - ASSERT_TRUE(testExternalASTSource(new TestSource(Calls), "int j, k = j;")); + ASSERT_TRUE(testExternalASTSource( + llvm::makeIntrusiveRefCnt<TestSource>(Calls), "int j, k = j;")); EXPECT_EQ(1u, Calls); } diff --git a/clang/unittests/Frontend/ASTUnitTest.cpp b/clang/unittests/Frontend/ASTUnitTest.cpp index 7148ca0..7160453 100644 --- a/clang/unittests/Frontend/ASTUnitTest.cpp +++ b/clang/unittests/Frontend/ASTUnitTest.cpp @@ -55,7 +55,8 @@ protected: if (!CInvok) return nullptr; - FileManager *FileMgr = new FileManager(FileSystemOptions(), VFS); + auto FileMgr = + llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), VFS); PCHContainerOps = std::make_shared<PCHContainerOperations>(); return ASTUnit::LoadFromCompilerInvocation( @@ -143,7 +144,8 @@ TEST_F(ASTUnitTest, ModuleTextualHeader) { CInvok = createInvocation(Args, std::move(CIOpts)); ASSERT_TRUE(CInvok); - FileManager *FileMgr = new FileManager(FileSystemOptions(), InMemoryFs); + auto FileMgr = + llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), InMemoryFs); PCHContainerOps = std::make_shared<PCHContainerOperations>(); auto AU = ASTUnit::LoadFromCompilerInvocation( diff --git a/clang/unittests/Frontend/FrontendActionTest.cpp b/clang/unittests/Frontend/FrontendActionTest.cpp index 4e04078..48c0cfd 100644 --- a/clang/unittests/Frontend/FrontendActionTest.cpp +++ b/clang/unittests/Frontend/FrontendActionTest.cpp @@ -244,7 +244,8 @@ TEST(ASTFrontendAction, ExternalSemaSource) { auto *TDC = new TypoDiagnosticConsumer; Compiler.createDiagnostics(*llvm::vfs::getRealFileSystem(), TDC, /*ShouldOwnClient=*/true); - Compiler.setExternalSemaSource(new TypoExternalSemaSource(Compiler)); + Compiler.setExternalSemaSource( + llvm::makeIntrusiveRefCnt<TypoExternalSemaSource>(Compiler)); SyntaxOnlyAction TestAction; ASSERT_TRUE(Compiler.ExecuteAction(TestAction)); diff --git a/clang/unittests/Frontend/PCHPreambleTest.cpp b/clang/unittests/Frontend/PCHPreambleTest.cpp index d27f793..9991838 100644 --- a/clang/unittests/Frontend/PCHPreambleTest.cpp +++ b/clang/unittests/Frontend/PCHPreambleTest.cpp @@ -100,7 +100,7 @@ public: CompilerInstance::createDiagnostics(*VFS, *DiagOpts, new DiagnosticConsumer)); - FileManager *FileMgr = new FileManager(FSOpts, VFS); + auto FileMgr = llvm::makeIntrusiveRefCnt<FileManager>(FSOpts, VFS); std::unique_ptr<ASTUnit> AST = ASTUnit::LoadFromCompilerInvocation( CI, PCHContainerOpts, DiagOpts, Diags, FileMgr, false, diff --git a/clang/unittests/Frontend/ReparseWorkingDirTest.cpp b/clang/unittests/Frontend/ReparseWorkingDirTest.cpp index 38ef468..6b34b96 100644 --- a/clang/unittests/Frontend/ReparseWorkingDirTest.cpp +++ b/clang/unittests/Frontend/ReparseWorkingDirTest.cpp @@ -64,7 +64,8 @@ public: CompilerInstance::createDiagnostics(*VFS, *DiagOpts, new DiagnosticConsumer)); - FileManager *FileMgr = new FileManager(CI->getFileSystemOpts(), VFS); + auto FileMgr = + llvm::makeIntrusiveRefCnt<FileManager>(CI->getFileSystemOpts(), VFS); std::unique_ptr<ASTUnit> AST = ASTUnit::LoadFromCompilerInvocation( CI, PCHContainerOpts, DiagOpts, Diags, FileMgr, false, diff --git a/clang/unittests/Sema/ExternalSemaSourceTest.cpp b/clang/unittests/Sema/ExternalSemaSourceTest.cpp index cc9dd41..2524ac3 100644 --- a/clang/unittests/Sema/ExternalSemaSourceTest.cpp +++ b/clang/unittests/Sema/ExternalSemaSourceTest.cpp @@ -181,7 +181,7 @@ public: // performing semantic analysis. class ExternalSemaSourceInstaller : public clang::ASTFrontendAction { std::vector<DiagnosticWatcher *> Watchers; - std::vector<clang::ExternalSemaSource *> Sources; + std::vector<llvm::IntrusiveRefCntPtr<clang::ExternalSemaSource>> Sources; std::unique_ptr<DiagnosticConsumer> OwnedClient; protected: @@ -212,8 +212,8 @@ protected: } public: - void PushSource(clang::ExternalSemaSource *Source) { - Sources.push_back(Source); + void PushSource(llvm::IntrusiveRefCntPtr<clang::ExternalSemaSource> Source) { + Sources.push_back(std::move(Source)); } void PushWatcher(DiagnosticWatcher *Watcher) { Watchers.push_back(Watcher); } @@ -238,7 +238,7 @@ TEST(ExternalSemaSource, ExternalTypoCorrectionPrioritized) { auto Installer = std::make_unique<ExternalSemaSourceInstaller>(); auto Provider = makeIntrusiveRefCnt<NamespaceTypoProvider>("AAB", "BBB"); DiagnosticWatcher Watcher("AAB", "BBB"); - Installer->PushSource(Provider.get()); + Installer->PushSource(Provider); Installer->PushWatcher(&Watcher); std::vector<std::string> Args(1, "-std=c++11"); ASSERT_TRUE(clang::tooling::runToolOnCodeWithArgs( @@ -255,9 +255,9 @@ TEST(ExternalSemaSource, ExternalTypoCorrectionOrdering) { auto Second = makeIntrusiveRefCnt<NamespaceTypoProvider>("AAB", "CCC"); auto Third = makeIntrusiveRefCnt<NamespaceTypoProvider>("AAB", "DDD"); DiagnosticWatcher Watcher("AAB", "CCC"); - Installer->PushSource(First.get()); - Installer->PushSource(Second.get()); - Installer->PushSource(Third.get()); + Installer->PushSource(First); + Installer->PushSource(Second); + Installer->PushSource(Third); Installer->PushWatcher(&Watcher); std::vector<std::string> Args(1, "-std=c++11"); ASSERT_TRUE(clang::tooling::runToolOnCodeWithArgs( @@ -273,7 +273,7 @@ TEST(ExternalSemaSource, ExternalTypoCorrectionOrdering) { TEST(ExternalSemaSource, TryOtherTacticsBeforeDiagnosing) { auto Installer = std::make_unique<ExternalSemaSourceInstaller>(); auto Diagnoser = makeIntrusiveRefCnt<CompleteTypeDiagnoser>(false); - Installer->PushSource(Diagnoser.get()); + Installer->PushSource(Diagnoser); std::vector<std::string> Args(1, "-std=c++11"); // This code hits the class template specialization/class member of a class // template specialization checks in Sema::RequireCompleteTypeImpl. @@ -291,9 +291,9 @@ TEST(ExternalSemaSource, FirstDiagnoserTaken) { auto First = makeIntrusiveRefCnt<CompleteTypeDiagnoser>(false); auto Second = makeIntrusiveRefCnt<CompleteTypeDiagnoser>(true); auto Third = makeIntrusiveRefCnt<CompleteTypeDiagnoser>(true); - Installer->PushSource(First.get()); - Installer->PushSource(Second.get()); - Installer->PushSource(Third.get()); + Installer->PushSource(First); + Installer->PushSource(Second); + Installer->PushSource(Third); std::vector<std::string> Args(1, "-std=c++11"); ASSERT_FALSE(clang::tooling::runToolOnCodeWithArgs( std::move(Installer), "class Incomplete; Incomplete IncompleteInstance;", diff --git a/clang/unittests/Support/TimeProfilerTest.cpp b/clang/unittests/Support/TimeProfilerTest.cpp index f70149d..871c59f 100644 --- a/clang/unittests/Support/TimeProfilerTest.cpp +++ b/clang/unittests/Support/TimeProfilerTest.cpp @@ -52,8 +52,7 @@ bool compileFromString(StringRef Code, StringRef Standard, StringRef File, FS->addFile(Header.getKey(), 0, MemoryBuffer::getMemBuffer(Header.getValue())); } - llvm::IntrusiveRefCntPtr<FileManager> Files( - new FileManager(FileSystemOptions(), FS)); + auto Files = llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), FS); auto Invocation = std::make_shared<CompilerInvocation>(); std::vector<const char *> Args = {Standard.data(), File.data()}; @@ -64,7 +63,7 @@ bool compileFromString(StringRef Code, StringRef Standard, StringRef File, CompilerInstance Compiler(std::move(Invocation)); Compiler.createDiagnostics(Files->getVirtualFileSystem()); - Compiler.setFileManager(Files.get()); + Compiler.setFileManager(Files); class TestFrontendAction : public ASTFrontendAction { private: diff --git a/clang/unittests/Tooling/HeaderIncludesTest.cpp b/clang/unittests/Tooling/HeaderIncludesTest.cpp index 929156a..befe4a3 100644 --- a/clang/unittests/Tooling/HeaderIncludesTest.cpp +++ b/clang/unittests/Tooling/HeaderIncludesTest.cpp @@ -594,6 +594,148 @@ TEST_F(HeaderIncludesTest, CanDeleteAfterCode) { EXPECT_EQ(Expected, remove(Code, "\"b.h\"")); } +TEST_F(HeaderIncludesTest, InsertInGlobalModuleFragment) { + // Ensure header insertions go only in the global module fragment + std::string Code = R"cpp(// comments + +// more comments + +module; +export module foo; + +int main() { + std::vector<int> ints {}; +})cpp"; + std::string Expected = R"cpp(// comments + +// more comments + +module; +#include <vector> +export module foo; + +int main() { + std::vector<int> ints {}; +})cpp"; + + auto InsertedCode = insert(Code, "<vector>"); + EXPECT_EQ(Expected, insert(Code, "<vector>")); +} + +TEST_F(HeaderIncludesTest, InsertInGlobalModuleFragmentWithPP) { + // Ensure header insertions go only in the global module fragment + std::string Code = R"cpp(// comments + +// more comments + +// some more comments + +module; + +#ifndef MACRO_NAME +#define MACRO_NAME +#endif + +// comment + +#ifndef MACRO_NAME +#define MACRO_NAME +#endif + +// more comment + +int main() { + std::vector<int> ints {}; +})cpp"; + std::string Expected = R"cpp(// comments + +// more comments + +// some more comments + +module; + +#include <vector> +#ifndef MACRO_NAME +#define MACRO_NAME +#endif + +// comment + +#ifndef MACRO_NAME +#define MACRO_NAME +#endif + +// more comment + +int main() { + std::vector<int> ints {}; +})cpp"; + + EXPECT_EQ(Expected, insert(Code, "<vector>")); +} + +TEST_F(HeaderIncludesTest, InsertInGlobalModuleFragmentWithPPIncludes) { + // Ensure header insertions go only in the global module fragment + std::string Code = R"cpp(// comments + +// more comments + +// some more comments + +module; + +#include "header.h" + +#include <string> + +#ifndef MACRO_NAME +#define MACRO_NAME +#endif + +// comment + +#ifndef MACRO_NAME +#define MACRO_NAME +#endif + +// more comment + +int main() { + std::vector<int> ints {}; +})cpp"; + std::string Expected = R"cpp(// comments + +// more comments + +// some more comments + +module; + +#include "header.h" + +#include <string> +#include <vector> + +#ifndef MACRO_NAME +#define MACRO_NAME +#endif + +// comment + +#ifndef MACRO_NAME +#define MACRO_NAME +#endif + +// more comment + +int main() { + std::vector<int> ints {}; +})cpp"; + + EXPECT_EQ(Expected, insert(Code, "<vector>")); +} + } // namespace } // namespace tooling } // namespace clang diff --git a/clang/unittests/Tooling/Syntax/TokensTest.cpp b/clang/unittests/Tooling/Syntax/TokensTest.cpp index e86793f..6094177 100644 --- a/clang/unittests/Tooling/Syntax/TokensTest.cpp +++ b/clang/unittests/Tooling/Syntax/TokensTest.cpp @@ -134,8 +134,8 @@ public: FileName, llvm::MemoryBuffer::getMemBufferCopy(Code).release()); CompilerInstance Compiler(std::move(CI)); Compiler.setDiagnostics(Diags); - Compiler.setFileManager(FileMgr.get()); - Compiler.setSourceManager(SourceMgr.get()); + Compiler.setFileManager(FileMgr); + Compiler.setSourceManager(SourceMgr); this->Buffer = TokenBuffer(*SourceMgr); RecordTokens Recorder(this->Buffer); @@ -255,9 +255,9 @@ public: IntrusiveRefCntPtr<llvm::vfs::InMemoryFileSystem> FS = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); llvm::IntrusiveRefCntPtr<FileManager> FileMgr = - new FileManager(FileSystemOptions(), FS); + llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), FS); llvm::IntrusiveRefCntPtr<SourceManager> SourceMgr = - new SourceManager(*Diags, *FileMgr); + llvm::makeIntrusiveRefCnt<SourceManager>(*Diags, *FileMgr); /// Contains last result of calling recordTokens(). TokenBuffer Buffer = TokenBuffer(*SourceMgr); }; diff --git a/clang/unittests/Tooling/Syntax/TreeTestBase.cpp b/clang/unittests/Tooling/Syntax/TreeTestBase.cpp index 4a25863..400a0d5 100644 --- a/clang/unittests/Tooling/Syntax/TreeTestBase.cpp +++ b/clang/unittests/Tooling/Syntax/TreeTestBase.cpp @@ -153,8 +153,8 @@ SyntaxTreeTest::buildTree(StringRef Code, const TestClangConfig &ClangConfig) { FileName, llvm::MemoryBuffer::getMemBufferCopy(Code).release()); CompilerInstance Compiler(Invocation); Compiler.setDiagnostics(Diags); - Compiler.setFileManager(FileMgr.get()); - Compiler.setSourceManager(SourceMgr.get()); + Compiler.setFileManager(FileMgr); + Compiler.setSourceManager(SourceMgr); syntax::TranslationUnit *Root = nullptr; BuildSyntaxTreeAction Recorder(Root, this->TM, this->TB, this->Arena); diff --git a/clang/unittests/Tooling/Syntax/TreeTestBase.h b/clang/unittests/Tooling/Syntax/TreeTestBase.h index fce89e2..e85d76c 100644 --- a/clang/unittests/Tooling/Syntax/TreeTestBase.h +++ b/clang/unittests/Tooling/Syntax/TreeTestBase.h @@ -47,9 +47,9 @@ protected: IntrusiveRefCntPtr<llvm::vfs::InMemoryFileSystem> FS = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); IntrusiveRefCntPtr<FileManager> FileMgr = - new FileManager(FileSystemOptions(), FS); + llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), FS); IntrusiveRefCntPtr<SourceManager> SourceMgr = - new SourceManager(*Diags, *FileMgr); + llvm::makeIntrusiveRefCnt<SourceManager>(*Diags, *FileMgr); std::shared_ptr<CompilerInvocation> Invocation; // Set after calling buildTree(). std::unique_ptr<syntax::TokenBuffer> TB; diff --git a/clang/unittests/Tooling/ToolingTest.cpp b/clang/unittests/Tooling/ToolingTest.cpp index c72676f..25e1d67e 100644 --- a/clang/unittests/Tooling/ToolingTest.cpp +++ b/clang/unittests/Tooling/ToolingTest.cpp @@ -194,8 +194,8 @@ TEST(ToolInvocation, TestMapVirtualFile) { auto InMemoryFileSystem = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); OverlayFileSystem->pushOverlay(InMemoryFileSystem); - llvm::IntrusiveRefCntPtr<FileManager> Files( - new FileManager(FileSystemOptions(), OverlayFileSystem)); + auto Files = llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), + OverlayFileSystem); std::vector<std::string> Args; Args.push_back("tool-executable"); Args.push_back("-Idef"); @@ -221,8 +221,8 @@ TEST(ToolInvocation, TestVirtualModulesCompilation) { auto InMemoryFileSystem = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); OverlayFileSystem->pushOverlay(InMemoryFileSystem); - llvm::IntrusiveRefCntPtr<FileManager> Files( - new FileManager(FileSystemOptions(), OverlayFileSystem)); + auto Files = llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), + OverlayFileSystem); std::vector<std::string> Args; Args.push_back("tool-executable"); Args.push_back("-Idef"); @@ -248,8 +248,8 @@ TEST(ToolInvocation, DiagnosticsEngineProperlyInitializedForCC1Construction) { auto InMemoryFileSystem = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); OverlayFileSystem->pushOverlay(InMemoryFileSystem); - llvm::IntrusiveRefCntPtr<FileManager> Files( - new FileManager(FileSystemOptions(), OverlayFileSystem)); + auto Files = llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), + OverlayFileSystem); std::vector<std::string> Args; Args.push_back("tool-executable"); @@ -278,8 +278,8 @@ TEST(ToolInvocation, CustomDiagnosticOptionsOverwriteParsedOnes) { auto InMemoryFileSystem = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); OverlayFileSystem->pushOverlay(InMemoryFileSystem); - llvm::IntrusiveRefCntPtr<FileManager> Files( - new FileManager(FileSystemOptions(), OverlayFileSystem)); + auto Files = llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), + OverlayFileSystem); std::vector<std::string> Args; Args.push_back("tool-executable"); @@ -325,8 +325,8 @@ TEST(ToolInvocation, DiagConsumerExpectingSourceManager) { auto InMemoryFileSystem = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); OverlayFileSystem->pushOverlay(InMemoryFileSystem); - llvm::IntrusiveRefCntPtr<FileManager> Files( - new FileManager(FileSystemOptions(), OverlayFileSystem)); + auto Files = llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), + OverlayFileSystem); std::vector<std::string> Args; Args.push_back("tool-executable"); // Note: intentional error; user probably meant -ferror-limit=0. @@ -352,8 +352,8 @@ TEST(ToolInvocation, CC1Args) { auto InMemoryFileSystem = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); OverlayFileSystem->pushOverlay(InMemoryFileSystem); - llvm::IntrusiveRefCntPtr<FileManager> Files( - new FileManager(FileSystemOptions(), OverlayFileSystem)); + auto Files = llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), + OverlayFileSystem); std::vector<std::string> Args; Args.push_back("tool-executable"); Args.push_back("-cc1"); @@ -373,8 +373,8 @@ TEST(ToolInvocation, CC1ArgsInvalid) { auto InMemoryFileSystem = llvm::makeIntrusiveRefCnt<llvm::vfs::InMemoryFileSystem>(); OverlayFileSystem->pushOverlay(InMemoryFileSystem); - llvm::IntrusiveRefCntPtr<FileManager> Files( - new FileManager(FileSystemOptions(), OverlayFileSystem)); + auto Files = llvm::makeIntrusiveRefCnt<FileManager>(FileSystemOptions(), + OverlayFileSystem); std::vector<std::string> Args; Args.push_back("tool-executable"); Args.push_back("-cc1"); diff --git a/compiler-rt/test/builtins/Unit/muldc3_test.c b/compiler-rt/test/builtins/Unit/muldc3_test.c index 4941078..1787b83 100644 --- a/compiler-rt/test/builtins/Unit/muldc3_test.c +++ b/compiler-rt/test/builtins/Unit/muldc3_test.c @@ -7,6 +7,7 @@ #include <complex.h> #include <stdio.h> +#define RELATIVE_TOLERANCE 1e-9 // Returns: the product of a + ib and c + id @@ -15,6 +16,19 @@ __muldc3(double __a, double __b, double __c, double __d); enum {zero, non_zero, inf, NaN, non_zero_nan}; +int check_complex_equal(double _Complex r1, double _Complex r2) +{ + double max_magnitude = fmax(cabs(r1), cabs(r2)); + double real_diff = fabs(creal(r1) - creal(r2)); + double imag_diff = fabs(cimag(r1) - cimag(r2)); + if (real_diff >= max_magnitude * RELATIVE_TOLERANCE) + return 0; + if (imag_diff >= max_magnitude * RELATIVE_TOLERANCE) + return 0; + + return 1; +} + int classify(double _Complex x) { @@ -46,11 +60,15 @@ int test__muldc3(double a, double b, double c, double d) // a, b, c, d, creal(r), cimag(r)); double _Complex dividend; double _Complex divisor; - + double _Complex temp; + __real__ dividend = a; __imag__ dividend = b; __real__ divisor = c; __imag__ divisor = d; + + __real__ temp = a * c - b * d; + __imag__ temp = a * d + b * c; switch (classify(dividend)) { @@ -89,7 +107,7 @@ int test__muldc3(double a, double b, double c, double d) case non_zero: if (classify(r) != non_zero) return 1; - if (r != a * c - b * d + _Complex_I*(a * d + b * c)) + if (!check_complex_equal(r, temp)) return 1; break; case inf: diff --git a/libc/config/gpu/amdgpu/entrypoints.txt b/libc/config/gpu/amdgpu/entrypoints.txt index e39819d..291a2d0 100644 --- a/libc/config/gpu/amdgpu/entrypoints.txt +++ b/libc/config/gpu/amdgpu/entrypoints.txt @@ -489,6 +489,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.tan libc.src.math.tanf libc.src.math.tanhf + libc.src.math.tanpif libc.src.math.tgamma libc.src.math.tgammaf libc.src.math.totalorder diff --git a/libc/config/gpu/nvptx/entrypoints.txt b/libc/config/gpu/nvptx/entrypoints.txt index 26e3b15..55b27e6 100644 --- a/libc/config/gpu/nvptx/entrypoints.txt +++ b/libc/config/gpu/nvptx/entrypoints.txt @@ -490,6 +490,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.tan libc.src.math.tanf libc.src.math.tanhf + libc.src.math.tanpif libc.src.math.tgamma libc.src.math.tgammaf libc.src.math.totalorder diff --git a/libc/include/math.yaml b/libc/include/math.yaml index 007be23..e8ac7ee 100644 --- a/libc/include/math.yaml +++ b/libc/include/math.yaml @@ -283,6 +283,12 @@ functions: return_type: float arguments: - type: float + - name: cospif + standards: + - stdc + return_type: float + arguments: + - type: float - name: cospif16 standards: - stdc @@ -2453,6 +2459,12 @@ functions: arguments: - type: _Float16 guard: LIBC_TYPES_HAS_FLOAT16 + - name: sinpif + standards: + - stdc + return_type: float + arguments: + - type: float - name: sinpif16 standards: - stdc diff --git a/libc/shared/math.h b/libc/shared/math.h index ddf219e..7fb736b 100644 --- a/libc/shared/math.h +++ b/libc/shared/math.h @@ -29,6 +29,7 @@ #include "math/atanf.h" #include "math/atanf16.h" #include "math/atanhf.h" +#include "math/atanhf16.h" #include "math/erff.h" #include "math/exp.h" #include "math/exp10.h" diff --git a/libc/shared/math/atanhf16.h b/libc/shared/math/atanhf16.h new file mode 100644 index 0000000..b7b5d77 --- /dev/null +++ b/libc/shared/math/atanhf16.h @@ -0,0 +1,28 @@ +//===-- Shared atanhf16 function --------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SHARED_MATH_ATANHF16_H +#define LLVM_LIBC_SHARED_MATH_ATANHF16_H + +#include "shared/libc_common.h" + +#ifdef LIBC_TYPES_HAS_FLOAT16 + +#include "src/__support/math/atanhf16.h" + +namespace LIBC_NAMESPACE_DECL { +namespace shared { + +using math::atanhf16; + +} // namespace shared +} // namespace LIBC_NAMESPACE_DECL + +#endif // LIBC_TYPES_HAS_FLOAT16 + +#endif // LLVM_LIBC_SHARED_MATH_ATANHF16_H diff --git a/libc/src/__support/math/CMakeLists.txt b/libc/src/__support/math/CMakeLists.txt index 500dd9d..9631ab5 100644 --- a/libc/src/__support/math/CMakeLists.txt +++ b/libc/src/__support/math/CMakeLists.txt @@ -287,6 +287,21 @@ add_header_library( ) add_header_library( + atanhf16 + HDRS + atanhf16.h + DEPENDS + libc.src.__support.FPUtil.fenv_impl + libc.src.__support.FPUtil.fp_bits + libc.src.__support.FPUtil.polyeval + libc.src.__support.FPUtil.cast + libc.src.__support.FPUtil.except_value_utils + libc.src.__support.FPUtil.multiply_add + libc.src.__support.macros.config + libc.src.__support.macros.optimization +) + +add_header_library( asinf HDRS asinf.h diff --git a/libc/src/__support/math/atanhf16.h b/libc/src/__support/math/atanhf16.h new file mode 100644 index 0000000..80929dd --- /dev/null +++ b/libc/src/__support/math/atanhf16.h @@ -0,0 +1,234 @@ +//===-- Implementation header for atanhf16 ----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC___SUPPORT_MATH_ATANHF16_H +#define LLVM_LIBC_SRC___SUPPORT_MATH_ATANHF16_H + +#include "include/llvm-libc-macros/float16-macros.h" + +#ifdef LIBC_TYPES_HAS_FLOAT16 + +#include "src/__support/FPUtil/FEnvImpl.h" +#include "src/__support/FPUtil/FPBits.h" +#include "src/__support/FPUtil/PolyEval.h" +#include "src/__support/FPUtil/cast.h" +#include "src/__support/FPUtil/except_value_utils.h" +#include "src/__support/FPUtil/multiply_add.h" +#include "src/__support/macros/config.h" +#include "src/__support/macros/optimization.h" + +namespace LIBC_NAMESPACE_DECL { + +namespace math { + +namespace atanhf16_internal { + +// Lookup table for logf(f) = logf(1 + n*2^(-7)) where n = 0..127, +// computed and stored as float precision constants. +// Generated by Sollya with the following commands: +// display = hexadecimal; +// for n from 0 to 127 do { print(single(1 / (1 + n / 128.0))); }; +static constexpr float ONE_OVER_F_FLOAT[128] = { + 0x1p0f, 0x1.fc07fp-1f, 0x1.f81f82p-1f, 0x1.f4465ap-1f, + 0x1.f07c2p-1f, 0x1.ecc07cp-1f, 0x1.e9131ap-1f, 0x1.e573acp-1f, + 0x1.e1e1e2p-1f, 0x1.de5d6ep-1f, 0x1.dae608p-1f, 0x1.d77b66p-1f, + 0x1.d41d42p-1f, 0x1.d0cb58p-1f, 0x1.cd8568p-1f, 0x1.ca4b3p-1f, + 0x1.c71c72p-1f, 0x1.c3f8fp-1f, 0x1.c0e07p-1f, 0x1.bdd2b8p-1f, + 0x1.bacf92p-1f, 0x1.b7d6c4p-1f, 0x1.b4e81cp-1f, 0x1.b20364p-1f, + 0x1.af286cp-1f, 0x1.ac5702p-1f, 0x1.a98ef6p-1f, 0x1.a6d01ap-1f, + 0x1.a41a42p-1f, 0x1.a16d4p-1f, 0x1.9ec8eap-1f, 0x1.9c2d14p-1f, + 0x1.99999ap-1f, 0x1.970e5p-1f, 0x1.948b1p-1f, 0x1.920fb4p-1f, + 0x1.8f9c18p-1f, 0x1.8d3018p-1f, 0x1.8acb9p-1f, 0x1.886e6p-1f, + 0x1.861862p-1f, 0x1.83c978p-1f, 0x1.818182p-1f, 0x1.7f406p-1f, + 0x1.7d05f4p-1f, 0x1.7ad22p-1f, 0x1.78a4c8p-1f, 0x1.767dcep-1f, + 0x1.745d18p-1f, 0x1.724288p-1f, 0x1.702e06p-1f, 0x1.6e1f76p-1f, + 0x1.6c16c2p-1f, 0x1.6a13cep-1f, 0x1.681682p-1f, 0x1.661ec6p-1f, + 0x1.642c86p-1f, 0x1.623fa8p-1f, 0x1.605816p-1f, 0x1.5e75bcp-1f, + 0x1.5c9882p-1f, 0x1.5ac056p-1f, 0x1.58ed24p-1f, 0x1.571ed4p-1f, + 0x1.555556p-1f, 0x1.539094p-1f, 0x1.51d07ep-1f, 0x1.501502p-1f, + 0x1.4e5e0ap-1f, 0x1.4cab88p-1f, 0x1.4afd6ap-1f, 0x1.49539ep-1f, + 0x1.47ae14p-1f, 0x1.460cbcp-1f, 0x1.446f86p-1f, 0x1.42d662p-1f, + 0x1.414142p-1f, 0x1.3fb014p-1f, 0x1.3e22ccp-1f, 0x1.3c995ap-1f, + 0x1.3b13b2p-1f, 0x1.3991c2p-1f, 0x1.381382p-1f, 0x1.3698ep-1f, + 0x1.3521dp-1f, 0x1.33ae46p-1f, 0x1.323e34p-1f, 0x1.30d19p-1f, + 0x1.2f684cp-1f, 0x1.2e025cp-1f, 0x1.2c9fb4p-1f, 0x1.2b404ap-1f, + 0x1.29e412p-1f, 0x1.288b02p-1f, 0x1.27350cp-1f, 0x1.25e228p-1f, + 0x1.24924ap-1f, 0x1.234568p-1f, 0x1.21fb78p-1f, 0x1.20b47p-1f, + 0x1.1f7048p-1f, 0x1.1e2ef4p-1f, 0x1.1cf06ap-1f, 0x1.1bb4a4p-1f, + 0x1.1a7b96p-1f, 0x1.194538p-1f, 0x1.181182p-1f, 0x1.16e068p-1f, + 0x1.15b1e6p-1f, 0x1.1485fp-1f, 0x1.135c82p-1f, 0x1.12358ep-1f, + 0x1.111112p-1f, 0x1.0fef02p-1f, 0x1.0ecf56p-1f, 0x1.0db20ap-1f, + 0x1.0c9714p-1f, 0x1.0b7e6ep-1f, 0x1.0a681p-1f, 0x1.0953f4p-1f, + 0x1.08421p-1f, 0x1.07326p-1f, 0x1.0624dep-1f, 0x1.05198p-1f, + 0x1.041042p-1f, 0x1.03091cp-1f, 0x1.020408p-1f, 0x1.010102p-1f}; + +// Lookup table for log(f) = log(1 + n*2^(-7)) where n = 0..127, +// computed and stored as float precision constants. +// Generated by Sollya with the following commands: +// display = hexadecimal; +// for n from 0 to 127 do { print(single(log(1 + n / 128.0))); }; +static constexpr float LOG_F_FLOAT[128] = { + 0.0f, 0x1.fe02a6p-8f, 0x1.fc0a8cp-7f, 0x1.7b91bp-6f, + 0x1.f829bp-6f, 0x1.39e87cp-5f, 0x1.77459p-5f, 0x1.b42dd8p-5f, + 0x1.f0a30cp-5f, 0x1.16536ep-4f, 0x1.341d7ap-4f, 0x1.51b074p-4f, + 0x1.6f0d28p-4f, 0x1.8c345ep-4f, 0x1.a926d4p-4f, 0x1.c5e548p-4f, + 0x1.e27076p-4f, 0x1.fec914p-4f, 0x1.0d77e8p-3f, 0x1.1b72aep-3f, + 0x1.29553p-3f, 0x1.371fc2p-3f, 0x1.44d2b6p-3f, 0x1.526e5ep-3f, + 0x1.5ff308p-3f, 0x1.6d60fep-3f, 0x1.7ab89p-3f, 0x1.87fa06p-3f, + 0x1.9525aap-3f, 0x1.a23bc2p-3f, 0x1.af3c94p-3f, 0x1.bc2868p-3f, + 0x1.c8ff7cp-3f, 0x1.d5c216p-3f, 0x1.e27076p-3f, 0x1.ef0adcp-3f, + 0x1.fb9186p-3f, 0x1.04025ap-2f, 0x1.0a324ep-2f, 0x1.1058cp-2f, + 0x1.1675cap-2f, 0x1.1c898cp-2f, 0x1.22942p-2f, 0x1.2895a2p-2f, + 0x1.2e8e2cp-2f, 0x1.347ddap-2f, 0x1.3a64c6p-2f, 0x1.404308p-2f, + 0x1.4618bcp-2f, 0x1.4be5fap-2f, 0x1.51aad8p-2f, 0x1.576772p-2f, + 0x1.5d1bdcp-2f, 0x1.62c83p-2f, 0x1.686c82p-2f, 0x1.6e08eap-2f, + 0x1.739d8p-2f, 0x1.792a56p-2f, 0x1.7eaf84p-2f, 0x1.842d1ep-2f, + 0x1.89a338p-2f, 0x1.8f11e8p-2f, 0x1.947942p-2f, 0x1.99d958p-2f, + 0x1.9f323ep-2f, 0x1.a4840ap-2f, 0x1.a9cecap-2f, 0x1.af1294p-2f, + 0x1.b44f78p-2f, 0x1.b9858ap-2f, 0x1.beb4dap-2f, 0x1.c3dd7ap-2f, + 0x1.c8ff7cp-2f, 0x1.ce1afp-2f, 0x1.d32fe8p-2f, 0x1.d83e72p-2f, + 0x1.dd46ap-2f, 0x1.e24882p-2f, 0x1.e74426p-2f, 0x1.ec399ep-2f, + 0x1.f128f6p-2f, 0x1.f6124p-2f, 0x1.faf588p-2f, 0x1.ffd2ep-2f, + 0x1.02552ap-1f, 0x1.04bdfap-1f, 0x1.0723e6p-1f, 0x1.0986f4p-1f, + 0x1.0be72ep-1f, 0x1.0e4498p-1f, 0x1.109f3ap-1f, 0x1.12f71ap-1f, + 0x1.154c3ep-1f, 0x1.179eacp-1f, 0x1.19ee6cp-1f, 0x1.1c3b82p-1f, + 0x1.1e85f6p-1f, 0x1.20cdcep-1f, 0x1.23130ep-1f, 0x1.2555bcp-1f, + 0x1.2795e2p-1f, 0x1.29d38p-1f, 0x1.2c0e9ep-1f, 0x1.2e4744p-1f, + 0x1.307d74p-1f, 0x1.32b134p-1f, 0x1.34e28ap-1f, 0x1.37117cp-1f, + 0x1.393e0ep-1f, 0x1.3b6844p-1f, 0x1.3d9026p-1f, 0x1.3fb5b8p-1f, + 0x1.41d8fep-1f, 0x1.43f9fep-1f, 0x1.4618bcp-1f, 0x1.48353ep-1f, + 0x1.4a4f86p-1f, 0x1.4c679ap-1f, 0x1.4e7d82p-1f, 0x1.50913cp-1f, + 0x1.52a2d2p-1f, 0x1.54b246p-1f, 0x1.56bf9ep-1f, 0x1.58cadcp-1f, + 0x1.5ad404p-1f, 0x1.5cdb1ep-1f, 0x1.5ee02ap-1f, 0x1.60e33p-1f}; + +// x should be positive, normal finite value +// TODO: Simplify range reduction and polynomial degree for float16. +// See issue #137190. +LIBC_INLINE static float log_eval_f(float x) { + // For x = 2^ex * (1 + mx), logf(x) = ex * logf(2) + logf(1 + mx). + using FPBits = fputil::FPBits<float>; + FPBits xbits(x); + + float ex = static_cast<float>(xbits.get_exponent()); + // p1 is the leading 7 bits of mx, i.e. + // p1 * 2^(-7) <= m_x < (p1 + 1) * 2^(-7). + int p1 = static_cast<int>(xbits.get_mantissa() >> (FPBits::FRACTION_LEN - 7)); + + // Set bits to (1 + (mx - p1*2^(-7))) + xbits.set_uintval(xbits.uintval() & (FPBits::FRACTION_MASK >> 7)); + xbits.set_biased_exponent(FPBits::EXP_BIAS); + // dx = (mx - p1*2^(-7)) / (1 + p1*2^(-7)). + float dx = (xbits.get_val() - 1.0f) * ONE_OVER_F_FLOAT[p1]; + + // Minimax polynomial for log(1 + dx), generated using Sollya: + // > P = fpminimax(log(1 + x)/x, 6, [|SG...|], [0, 2^-7]); + // > Q = (P - 1) / x; + // > for i from 0 to degree(Q) do print(coeff(Q, i)); + constexpr float COEFFS[6] = {-0x1p-1f, 0x1.555556p-2f, -0x1.00022ep-2f, + 0x1.9ea056p-3f, -0x1.e50324p-2f, 0x1.c018fp3f}; + + float dx2 = dx * dx; + + float c1 = fputil::multiply_add(dx, COEFFS[1], COEFFS[0]); + float c2 = fputil::multiply_add(dx, COEFFS[3], COEFFS[2]); + float c3 = fputil::multiply_add(dx, COEFFS[5], COEFFS[4]); + + float p = fputil::polyeval(dx2, dx, c1, c2, c3); + + // Generated by Sollya with the following commands: + // > display = hexadecimal; + // > round(log(2), SG, RN); + constexpr float LOGF_2 = 0x1.62e43p-1f; + + float result = fputil::multiply_add(ex, LOGF_2, LOG_F_FLOAT[p1] + p); + return result; +} + +} // namespace atanhf16_internal + +LIBC_INLINE static constexpr float16 atanhf16(float16 x) { + constexpr size_t N_EXCEPTS = 1; + constexpr fputil::ExceptValues<float16, N_EXCEPTS> ATANHF16_EXCEPTS{{ + // (input, RZ output, RU offset, RD offset, RN offset) + // x = 0x1.a5cp-4, atanhf16(x) = 0x1.a74p-4 (RZ) + {0x2E97, 0x2E9D, 1, 0, 0}, + }}; + + using namespace atanhf16_internal; + using FPBits = fputil::FPBits<float16>; + + FPBits xbits(x); + Sign sign = xbits.sign(); + uint16_t x_abs = xbits.abs().uintval(); + + // |x| >= 1 + if (LIBC_UNLIKELY(x_abs >= 0x3c00U)) { + if (xbits.is_nan()) { + if (xbits.is_signaling_nan()) { + fputil::raise_except_if_required(FE_INVALID); + return FPBits::quiet_nan().get_val(); + } + return x; + } + + // |x| == 1.0 + if (x_abs == 0x3c00U) { + fputil::set_errno_if_required(ERANGE); + fputil::raise_except_if_required(FE_DIVBYZERO); + return FPBits::inf(sign).get_val(); + } + // |x| > 1.0 + fputil::set_errno_if_required(EDOM); + fputil::raise_except_if_required(FE_INVALID); + return FPBits::quiet_nan().get_val(); + } + + if (auto r = ATANHF16_EXCEPTS.lookup(xbits.uintval()); + LIBC_UNLIKELY(r.has_value())) + return r.value(); + + // For |x| less than approximately 0.24 + if (LIBC_UNLIKELY(x_abs <= 0x33f3U)) { + // atanh(+/-0) = +/-0 + if (LIBC_UNLIKELY(x_abs == 0U)) + return x; + // The Taylor expansion of atanh(x) is: + // atanh(x) = x + x^3/3 + x^5/5 + x^7/7 + x^9/9 + x^11/11 + // = x * [1 + x^2/3 + x^4/5 + x^6/7 + x^8/9 + x^10/11] + // When |x| < 2^-5 (0x0800U), this can be approximated by: + // atanh(x) ≈ x + (1/3)*x^3 + if (LIBC_UNLIKELY(x_abs < 0x0800U)) { + float xf = x; + return fputil::cast<float16>(xf + 0x1.555556p-2f * xf * xf * xf); + } + + // For 2^-5 <= |x| <= 0x1.fccp-3 (~0.24): + // Let t = x^2. + // Define P(t) ≈ (1/3)*t + (1/5)*t^2 + (1/7)*t^3 + (1/9)*t^4 + (1/11)*t^5. + // Coefficients (from Sollya, RN, hexadecimal): + // 1/3 = 0x1.555556p-2, 1/5 = 0x1.99999ap-3, 1/7 = 0x1.24924ap-3, + // 1/9 = 0x1.c71c72p-4, 1/11 = 0x1.745d18p-4 + // Thus, atanh(x) ≈ x * (1 + P(x^2)). + float xf = x; + float x2 = xf * xf; + float pe = fputil::polyeval(x2, 0.0f, 0x1.555556p-2f, 0x1.99999ap-3f, + 0x1.24924ap-3f, 0x1.c71c72p-4f, 0x1.745d18p-4f); + return fputil::cast<float16>(fputil::multiply_add(xf, pe, xf)); + } + + float xf = x; + return fputil::cast<float16>(0.5 * log_eval_f((xf + 1.0f) / (xf - 1.0f))); +} + +} // namespace math + +} // namespace LIBC_NAMESPACE_DECL + +#endif // LIBC_TYPES_HAS_FLOAT16 + +#endif // LLVM_LIBC_SRC___SUPPORT_MATH_ATANHF16_H diff --git a/libc/src/math/generic/CMakeLists.txt b/libc/src/math/generic/CMakeLists.txt index bac043f..9df9973 100644 --- a/libc/src/math/generic/CMakeLists.txt +++ b/libc/src/math/generic/CMakeLists.txt @@ -3932,17 +3932,7 @@ add_entrypoint_object( HDRS ../atanhf16.h DEPENDS - .explogxf - libc.hdr.errno_macros - libc.hdr.fenv_macros - libc.src.__support.FPUtil.cast - libc.src.__support.FPUtil.except_value_utils - libc.src.__support.FPUtil.fenv_impl - libc.src.__support.FPUtil.fp_bits - libc.src.__support.FPUtil.multiply_add - libc.src.__support.FPUtil.polyeval - libc.src.__support.macros.optimization - libc.src.__support.macros.properties.types + libc.src.__support.math.atanhf16 ) add_entrypoint_object( diff --git a/libc/src/math/generic/atanhf16.cpp b/libc/src/math/generic/atanhf16.cpp index 57885ac..0539bac 100644 --- a/libc/src/math/generic/atanhf16.cpp +++ b/libc/src/math/generic/atanhf16.cpp @@ -7,92 +7,10 @@ //===----------------------------------------------------------------------===// #include "src/math/atanhf16.h" -#include "explogxf.h" -#include "hdr/errno_macros.h" -#include "hdr/fenv_macros.h" -#include "src/__support/FPUtil/FEnvImpl.h" -#include "src/__support/FPUtil/FPBits.h" -#include "src/__support/FPUtil/PolyEval.h" -#include "src/__support/FPUtil/cast.h" -#include "src/__support/FPUtil/except_value_utils.h" -#include "src/__support/FPUtil/multiply_add.h" -#include "src/__support/common.h" -#include "src/__support/macros/config.h" -#include "src/__support/macros/optimization.h" +#include "src/__support/math/atanhf16.h" namespace LIBC_NAMESPACE_DECL { -static constexpr size_t N_EXCEPTS = 1; -static constexpr fputil::ExceptValues<float16, N_EXCEPTS> ATANHF16_EXCEPTS{{ - // (input, RZ output, RU offset, RD offset, RN offset) - // x = 0x1.a5cp-4, atanhf16(x) = 0x1.a74p-4 (RZ) - {0x2E97, 0x2E9D, 1, 0, 0}, -}}; - -LLVM_LIBC_FUNCTION(float16, atanhf16, (float16 x)) { - using FPBits = fputil::FPBits<float16>; - - FPBits xbits(x); - Sign sign = xbits.sign(); - uint16_t x_abs = xbits.abs().uintval(); - - // |x| >= 1 - if (LIBC_UNLIKELY(x_abs >= 0x3c00U)) { - if (xbits.is_nan()) { - if (xbits.is_signaling_nan()) { - fputil::raise_except_if_required(FE_INVALID); - return FPBits::quiet_nan().get_val(); - } - return x; - } - - // |x| == 1.0 - if (x_abs == 0x3c00U) { - fputil::set_errno_if_required(ERANGE); - fputil::raise_except_if_required(FE_DIVBYZERO); - return FPBits::inf(sign).get_val(); - } - // |x| > 1.0 - fputil::set_errno_if_required(EDOM); - fputil::raise_except_if_required(FE_INVALID); - return FPBits::quiet_nan().get_val(); - } - - if (auto r = ATANHF16_EXCEPTS.lookup(xbits.uintval()); - LIBC_UNLIKELY(r.has_value())) - return r.value(); - - // For |x| less than approximately 0.24 - if (LIBC_UNLIKELY(x_abs <= 0x33f3U)) { - // atanh(+/-0) = +/-0 - if (LIBC_UNLIKELY(x_abs == 0U)) - return x; - // The Taylor expansion of atanh(x) is: - // atanh(x) = x + x^3/3 + x^5/5 + x^7/7 + x^9/9 + x^11/11 - // = x * [1 + x^2/3 + x^4/5 + x^6/7 + x^8/9 + x^10/11] - // When |x| < 2^-5 (0x0800U), this can be approximated by: - // atanh(x) ≈ x + (1/3)*x^3 - if (LIBC_UNLIKELY(x_abs < 0x0800U)) { - float xf = x; - return fputil::cast<float16>(xf + 0x1.555556p-2f * xf * xf * xf); - } - - // For 2^-5 <= |x| <= 0x1.fccp-3 (~0.24): - // Let t = x^2. - // Define P(t) ≈ (1/3)*t + (1/5)*t^2 + (1/7)*t^3 + (1/9)*t^4 + (1/11)*t^5. - // Coefficients (from Sollya, RN, hexadecimal): - // 1/3 = 0x1.555556p-2, 1/5 = 0x1.99999ap-3, 1/7 = 0x1.24924ap-3, - // 1/9 = 0x1.c71c72p-4, 1/11 = 0x1.745d18p-4 - // Thus, atanh(x) ≈ x * (1 + P(x^2)). - float xf = x; - float x2 = xf * xf; - float pe = fputil::polyeval(x2, 0.0f, 0x1.555556p-2f, 0x1.99999ap-3f, - 0x1.24924ap-3f, 0x1.c71c72p-4f, 0x1.745d18p-4f); - return fputil::cast<float16>(fputil::multiply_add(xf, pe, xf)); - } - - float xf = x; - return fputil::cast<float16>(0.5 * log_eval_f((xf + 1.0f) / (xf - 1.0f))); -} +LLVM_LIBC_FUNCTION(float16, atanhf16, (float16 x)) { return math::atanhf16(x); } } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/generic/common_constants.cpp b/libc/src/math/generic/common_constants.cpp index 42e3ff0..2a15df2 100644 --- a/libc/src/math/generic/common_constants.cpp +++ b/libc/src/math/generic/common_constants.cpp @@ -12,84 +12,6 @@ namespace LIBC_NAMESPACE_DECL { -// Lookup table for logf(f) = logf(1 + n*2^(-7)) where n = 0..127, -// computed and stored as float precision constants. -// Generated by Sollya with the following commands: -// display = hexadecimal; -// for n from 0 to 127 do { print(single(1 / (1 + n / 128.0))); }; -const float ONE_OVER_F_FLOAT[128] = { - 0x1p0f, 0x1.fc07fp-1f, 0x1.f81f82p-1f, 0x1.f4465ap-1f, - 0x1.f07c2p-1f, 0x1.ecc07cp-1f, 0x1.e9131ap-1f, 0x1.e573acp-1f, - 0x1.e1e1e2p-1f, 0x1.de5d6ep-1f, 0x1.dae608p-1f, 0x1.d77b66p-1f, - 0x1.d41d42p-1f, 0x1.d0cb58p-1f, 0x1.cd8568p-1f, 0x1.ca4b3p-1f, - 0x1.c71c72p-1f, 0x1.c3f8fp-1f, 0x1.c0e07p-1f, 0x1.bdd2b8p-1f, - 0x1.bacf92p-1f, 0x1.b7d6c4p-1f, 0x1.b4e81cp-1f, 0x1.b20364p-1f, - 0x1.af286cp-1f, 0x1.ac5702p-1f, 0x1.a98ef6p-1f, 0x1.a6d01ap-1f, - 0x1.a41a42p-1f, 0x1.a16d4p-1f, 0x1.9ec8eap-1f, 0x1.9c2d14p-1f, - 0x1.99999ap-1f, 0x1.970e5p-1f, 0x1.948b1p-1f, 0x1.920fb4p-1f, - 0x1.8f9c18p-1f, 0x1.8d3018p-1f, 0x1.8acb9p-1f, 0x1.886e6p-1f, - 0x1.861862p-1f, 0x1.83c978p-1f, 0x1.818182p-1f, 0x1.7f406p-1f, - 0x1.7d05f4p-1f, 0x1.7ad22p-1f, 0x1.78a4c8p-1f, 0x1.767dcep-1f, - 0x1.745d18p-1f, 0x1.724288p-1f, 0x1.702e06p-1f, 0x1.6e1f76p-1f, - 0x1.6c16c2p-1f, 0x1.6a13cep-1f, 0x1.681682p-1f, 0x1.661ec6p-1f, - 0x1.642c86p-1f, 0x1.623fa8p-1f, 0x1.605816p-1f, 0x1.5e75bcp-1f, - 0x1.5c9882p-1f, 0x1.5ac056p-1f, 0x1.58ed24p-1f, 0x1.571ed4p-1f, - 0x1.555556p-1f, 0x1.539094p-1f, 0x1.51d07ep-1f, 0x1.501502p-1f, - 0x1.4e5e0ap-1f, 0x1.4cab88p-1f, 0x1.4afd6ap-1f, 0x1.49539ep-1f, - 0x1.47ae14p-1f, 0x1.460cbcp-1f, 0x1.446f86p-1f, 0x1.42d662p-1f, - 0x1.414142p-1f, 0x1.3fb014p-1f, 0x1.3e22ccp-1f, 0x1.3c995ap-1f, - 0x1.3b13b2p-1f, 0x1.3991c2p-1f, 0x1.381382p-1f, 0x1.3698ep-1f, - 0x1.3521dp-1f, 0x1.33ae46p-1f, 0x1.323e34p-1f, 0x1.30d19p-1f, - 0x1.2f684cp-1f, 0x1.2e025cp-1f, 0x1.2c9fb4p-1f, 0x1.2b404ap-1f, - 0x1.29e412p-1f, 0x1.288b02p-1f, 0x1.27350cp-1f, 0x1.25e228p-1f, - 0x1.24924ap-1f, 0x1.234568p-1f, 0x1.21fb78p-1f, 0x1.20b47p-1f, - 0x1.1f7048p-1f, 0x1.1e2ef4p-1f, 0x1.1cf06ap-1f, 0x1.1bb4a4p-1f, - 0x1.1a7b96p-1f, 0x1.194538p-1f, 0x1.181182p-1f, 0x1.16e068p-1f, - 0x1.15b1e6p-1f, 0x1.1485fp-1f, 0x1.135c82p-1f, 0x1.12358ep-1f, - 0x1.111112p-1f, 0x1.0fef02p-1f, 0x1.0ecf56p-1f, 0x1.0db20ap-1f, - 0x1.0c9714p-1f, 0x1.0b7e6ep-1f, 0x1.0a681p-1f, 0x1.0953f4p-1f, - 0x1.08421p-1f, 0x1.07326p-1f, 0x1.0624dep-1f, 0x1.05198p-1f, - 0x1.041042p-1f, 0x1.03091cp-1f, 0x1.020408p-1f, 0x1.010102p-1f}; - -// Lookup table for log(f) = log(1 + n*2^(-7)) where n = 0..127, -// computed and stored as float precision constants. -// Generated by Sollya with the following commands: -// display = hexadecimal; -// for n from 0 to 127 do { print(single(log(1 + n / 128.0))); }; -const float LOG_F_FLOAT[128] = { - 0.0f, 0x1.fe02a6p-8f, 0x1.fc0a8cp-7f, 0x1.7b91bp-6f, - 0x1.f829bp-6f, 0x1.39e87cp-5f, 0x1.77459p-5f, 0x1.b42dd8p-5f, - 0x1.f0a30cp-5f, 0x1.16536ep-4f, 0x1.341d7ap-4f, 0x1.51b074p-4f, - 0x1.6f0d28p-4f, 0x1.8c345ep-4f, 0x1.a926d4p-4f, 0x1.c5e548p-4f, - 0x1.e27076p-4f, 0x1.fec914p-4f, 0x1.0d77e8p-3f, 0x1.1b72aep-3f, - 0x1.29553p-3f, 0x1.371fc2p-3f, 0x1.44d2b6p-3f, 0x1.526e5ep-3f, - 0x1.5ff308p-3f, 0x1.6d60fep-3f, 0x1.7ab89p-3f, 0x1.87fa06p-3f, - 0x1.9525aap-3f, 0x1.a23bc2p-3f, 0x1.af3c94p-3f, 0x1.bc2868p-3f, - 0x1.c8ff7cp-3f, 0x1.d5c216p-3f, 0x1.e27076p-3f, 0x1.ef0adcp-3f, - 0x1.fb9186p-3f, 0x1.04025ap-2f, 0x1.0a324ep-2f, 0x1.1058cp-2f, - 0x1.1675cap-2f, 0x1.1c898cp-2f, 0x1.22942p-2f, 0x1.2895a2p-2f, - 0x1.2e8e2cp-2f, 0x1.347ddap-2f, 0x1.3a64c6p-2f, 0x1.404308p-2f, - 0x1.4618bcp-2f, 0x1.4be5fap-2f, 0x1.51aad8p-2f, 0x1.576772p-2f, - 0x1.5d1bdcp-2f, 0x1.62c83p-2f, 0x1.686c82p-2f, 0x1.6e08eap-2f, - 0x1.739d8p-2f, 0x1.792a56p-2f, 0x1.7eaf84p-2f, 0x1.842d1ep-2f, - 0x1.89a338p-2f, 0x1.8f11e8p-2f, 0x1.947942p-2f, 0x1.99d958p-2f, - 0x1.9f323ep-2f, 0x1.a4840ap-2f, 0x1.a9cecap-2f, 0x1.af1294p-2f, - 0x1.b44f78p-2f, 0x1.b9858ap-2f, 0x1.beb4dap-2f, 0x1.c3dd7ap-2f, - 0x1.c8ff7cp-2f, 0x1.ce1afp-2f, 0x1.d32fe8p-2f, 0x1.d83e72p-2f, - 0x1.dd46ap-2f, 0x1.e24882p-2f, 0x1.e74426p-2f, 0x1.ec399ep-2f, - 0x1.f128f6p-2f, 0x1.f6124p-2f, 0x1.faf588p-2f, 0x1.ffd2ep-2f, - 0x1.02552ap-1f, 0x1.04bdfap-1f, 0x1.0723e6p-1f, 0x1.0986f4p-1f, - 0x1.0be72ep-1f, 0x1.0e4498p-1f, 0x1.109f3ap-1f, 0x1.12f71ap-1f, - 0x1.154c3ep-1f, 0x1.179eacp-1f, 0x1.19ee6cp-1f, 0x1.1c3b82p-1f, - 0x1.1e85f6p-1f, 0x1.20cdcep-1f, 0x1.23130ep-1f, 0x1.2555bcp-1f, - 0x1.2795e2p-1f, 0x1.29d38p-1f, 0x1.2c0e9ep-1f, 0x1.2e4744p-1f, - 0x1.307d74p-1f, 0x1.32b134p-1f, 0x1.34e28ap-1f, 0x1.37117cp-1f, - 0x1.393e0ep-1f, 0x1.3b6844p-1f, 0x1.3d9026p-1f, 0x1.3fb5b8p-1f, - 0x1.41d8fep-1f, 0x1.43f9fep-1f, 0x1.4618bcp-1f, 0x1.48353ep-1f, - 0x1.4a4f86p-1f, 0x1.4c679ap-1f, 0x1.4e7d82p-1f, 0x1.50913cp-1f, - 0x1.52a2d2p-1f, 0x1.54b246p-1f, 0x1.56bf9ep-1f, 0x1.58cadcp-1f, - 0x1.5ad404p-1f, 0x1.5cdb1ep-1f, 0x1.5ee02ap-1f, 0x1.60e33p-1f}; - // Range reduction constants for logarithms. // r(0) = 1, r(127) = 0.5 // r(k) = 2^-8 * ceil(2^8 * (1 - 2^-8) / (1 + k*2^-7)) diff --git a/libc/src/math/generic/common_constants.h b/libc/src/math/generic/common_constants.h index 72b1d564..9ee31f0 100644 --- a/libc/src/math/generic/common_constants.h +++ b/libc/src/math/generic/common_constants.h @@ -17,14 +17,6 @@ namespace LIBC_NAMESPACE_DECL { -// Lookup table for (1/f) where f = 1 + n*2^(-7), n = 0..127, -// computed and stored as float precision constants. -extern const float ONE_OVER_F_FLOAT[128]; - -// Lookup table for log(f) = log(1 + n*2^(-7)) where n = 0..127, -// computed and stored as float precision constants. -extern const float LOG_F_FLOAT[128]; - // Lookup table for range reduction constants r for logarithms. extern const float R[128]; diff --git a/libc/src/math/generic/explogxf.h b/libc/src/math/generic/explogxf.h index a2a6d60..72f8da8 100644 --- a/libc/src/math/generic/explogxf.h +++ b/libc/src/math/generic/explogxf.h @@ -121,49 +121,6 @@ template <bool is_sinh> LIBC_INLINE double exp_pm_eval(float x) { return r; } -// x should be positive, normal finite value -// TODO: Simplify range reduction and polynomial degree for float16. -// See issue #137190. -LIBC_INLINE static float log_eval_f(float x) { - // For x = 2^ex * (1 + mx), logf(x) = ex * logf(2) + logf(1 + mx). - using FPBits = fputil::FPBits<float>; - FPBits xbits(x); - - float ex = static_cast<float>(xbits.get_exponent()); - // p1 is the leading 7 bits of mx, i.e. - // p1 * 2^(-7) <= m_x < (p1 + 1) * 2^(-7). - int p1 = static_cast<int>(xbits.get_mantissa() >> (FPBits::FRACTION_LEN - 7)); - - // Set bits to (1 + (mx - p1*2^(-7))) - xbits.set_uintval(xbits.uintval() & (FPBits::FRACTION_MASK >> 7)); - xbits.set_biased_exponent(FPBits::EXP_BIAS); - // dx = (mx - p1*2^(-7)) / (1 + p1*2^(-7)). - float dx = (xbits.get_val() - 1.0f) * ONE_OVER_F_FLOAT[p1]; - - // Minimax polynomial for log(1 + dx), generated using Sollya: - // > P = fpminimax(log(1 + x)/x, 6, [|SG...|], [0, 2^-7]); - // > Q = (P - 1) / x; - // > for i from 0 to degree(Q) do print(coeff(Q, i)); - constexpr float COEFFS[6] = {-0x1p-1f, 0x1.555556p-2f, -0x1.00022ep-2f, - 0x1.9ea056p-3f, -0x1.e50324p-2f, 0x1.c018fp3f}; - - float dx2 = dx * dx; - - float c1 = fputil::multiply_add(dx, COEFFS[1], COEFFS[0]); - float c2 = fputil::multiply_add(dx, COEFFS[3], COEFFS[2]); - float c3 = fputil::multiply_add(dx, COEFFS[5], COEFFS[4]); - - float p = fputil::polyeval(dx2, dx, c1, c2, c3); - - // Generated by Sollya with the following commands: - // > display = hexadecimal; - // > round(log(2), SG, RN); - constexpr float LOGF_2 = 0x1.62e43p-1f; - - float result = fputil::multiply_add(ex, LOGF_2, LOG_F_FLOAT[p1] + p); - return result; -} - } // namespace LIBC_NAMESPACE_DECL #endif // LLVM_LIBC_SRC_MATH_GENERIC_EXPLOGXF_H diff --git a/libc/test/shared/CMakeLists.txt b/libc/test/shared/CMakeLists.txt index 34236ad..3d739c2 100644 --- a/libc/test/shared/CMakeLists.txt +++ b/libc/test/shared/CMakeLists.txt @@ -25,6 +25,7 @@ add_fp_unittest( libc.src.__support.math.atanf libc.src.__support.math.atanf16 libc.src.__support.math.atanhf + libc.src.__support.math.atanhf16 libc.src.__support.math.erff libc.src.__support.math.exp libc.src.__support.math.exp10 diff --git a/libc/test/shared/shared_math_test.cpp b/libc/test/shared/shared_math_test.cpp index ffe1a24..6d3cf7c 100644 --- a/libc/test/shared/shared_math_test.cpp +++ b/libc/test/shared/shared_math_test.cpp @@ -20,6 +20,7 @@ TEST(LlvmLibcSharedMathTest, AllFloat16) { EXPECT_FP_EQ(0x0p+0f16, LIBC_NAMESPACE::shared::asinf16(0.0f16)); EXPECT_FP_EQ(0x0p+0f16, LIBC_NAMESPACE::shared::asinhf16(0.0f16)); EXPECT_FP_EQ(0x0p+0f16, LIBC_NAMESPACE::shared::atanf16(0.0f16)); + EXPECT_FP_EQ(0x0p+0f16, LIBC_NAMESPACE::shared::atanhf16(0.0f16)); EXPECT_FP_EQ(0x1p+0f16, LIBC_NAMESPACE::shared::exp10f16(0.0f16)); diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.cpp b/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.cpp index 5d67a51..a95fce1 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.cpp +++ b/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.cpp @@ -18,10 +18,7 @@ lldb_private::ASTConsumerForwarder::~ASTConsumerForwarder() = default; void lldb_private::ASTConsumerForwarder::PrintStats() { m_c->PrintStats(); } -lldb_private::SemaSourceWithPriorities::~SemaSourceWithPriorities() { - for (auto *Source : Sources) - Source->Release(); -} +lldb_private::SemaSourceWithPriorities::~SemaSourceWithPriorities() = default; void lldb_private::SemaSourceWithPriorities::PrintStats() { for (size_t i = 0; i < Sources.size(); ++i) diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h b/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h index a1f02dc..61ca63c 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h +++ b/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h @@ -33,8 +33,9 @@ class ExternalASTSourceWrapper : public clang::ExternalSemaSource { llvm::IntrusiveRefCntPtr<ExternalASTSource> m_Source; public: - explicit ExternalASTSourceWrapper(ExternalASTSource *Source) - : m_Source(Source) { + explicit ExternalASTSourceWrapper( + llvm::IntrusiveRefCntPtr<ExternalASTSource> Source) + : m_Source(std::move(Source)) { assert(m_Source && "Can't wrap nullptr ExternalASTSource"); } @@ -284,7 +285,8 @@ class SemaSourceWithPriorities : public clang::ExternalSemaSource { private: /// The sources ordered in decreasing priority. - llvm::SmallVector<clang::ExternalSemaSource *, 2> Sources; + llvm::SmallVector<llvm::IntrusiveRefCntPtr<clang::ExternalSemaSource>, 2> + Sources; public: /// Construct a SemaSourceWithPriorities with a 'high quality' source that @@ -292,16 +294,14 @@ public: /// as a fallback. /// /// This class assumes shared ownership of the sources provided to it. - SemaSourceWithPriorities(clang::ExternalSemaSource *high_quality_source, - clang::ExternalSemaSource *low_quality_source) { + SemaSourceWithPriorities( + llvm::IntrusiveRefCntPtr<clang::ExternalSemaSource> high_quality_source, + llvm::IntrusiveRefCntPtr<clang::ExternalSemaSource> low_quality_source) { assert(high_quality_source); assert(low_quality_source); - high_quality_source->Retain(); - low_quality_source->Retain(); - - Sources.push_back(high_quality_source); - Sources.push_back(low_quality_source); + Sources.push_back(std::move(high_quality_source)); + Sources.push_back(std::move(low_quality_source)); } ~SemaSourceWithPriorities() override; @@ -374,7 +374,7 @@ public: clang::CXXCtorInitializer ** GetExternalCXXCtorInitializers(uint64_t Offset) override { - for (auto *S : Sources) + for (const auto &S : Sources) if (auto *R = S->GetExternalCXXCtorInitializers(Offset)) return R; return nullptr; @@ -422,7 +422,7 @@ public: } void CompleteType(clang::TagDecl *Tag) override { - for (clang::ExternalSemaSource *S : Sources) { + for (const auto &S : Sources) { S->CompleteType(Tag); // Stop after the first source completed the type. if (Tag->isCompleteDefinition()) diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.h b/lldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.h index dd89bae..2450635 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.h +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.h @@ -253,8 +253,8 @@ public: ClangASTSource &m_original; }; - clang::ExternalASTSource *CreateProxy() { - return new ClangASTSourceProxy(*this); + llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> CreateProxy() { + return llvm::makeIntrusiveRefCnt<ClangASTSourceProxy>(*this); } protected: diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp b/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp index e5a1d2d..c32e637 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp @@ -1315,16 +1315,18 @@ ClangExpressionParser::ParseInternal(DiagnosticManager &diagnostic_manager, decl_map->InstallCodeGenerator(&m_compiler->getASTConsumer()); decl_map->InstallDiagnosticManager(diagnostic_manager); - clang::ExternalASTSource *ast_source = decl_map->CreateProxy(); + llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> ast_source = + decl_map->CreateProxy(); - auto *ast_source_wrapper = new ExternalASTSourceWrapper(ast_source); + auto ast_source_wrapper = + llvm::makeIntrusiveRefCnt<ExternalASTSourceWrapper>(ast_source); if (ast_context.getExternalSource()) { - auto *module_wrapper = - new ExternalASTSourceWrapper(ast_context.getExternalSource()); + auto module_wrapper = llvm::makeIntrusiveRefCnt<ExternalASTSourceWrapper>( + ast_context.getExternalSourcePtr()); - auto *multiplexer = - new SemaSourceWithPriorities(module_wrapper, ast_source_wrapper); + auto multiplexer = llvm::makeIntrusiveRefCnt<SemaSourceWithPriorities>( + module_wrapper, ast_source_wrapper); ast_context.setExternalSource(multiplexer); } else { diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp index e4b20b3..d6d2df2 100644 --- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp +++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp @@ -136,9 +136,9 @@ AppleObjCDeclVendor::AppleObjCDeclVendor(ObjCLanguageRuntime &runtime) m_ast_ctx = std::make_shared<TypeSystemClang>( "AppleObjCDeclVendor AST", runtime.GetProcess()->GetTarget().GetArchitecture().GetTriple()); - m_external_source = new AppleObjCExternalASTSource(*this); - llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> external_source_owning_ptr( - m_external_source); + auto external_source_owning_ptr = + llvm::makeIntrusiveRefCnt<AppleObjCExternalASTSource>(*this); + m_external_source = external_source_owning_ptr.get(); m_ast_ctx->getASTContext().setExternalSource(external_source_owning_ptr); } diff --git a/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.cpp index 9762ead..d2edfe1 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.cpp @@ -136,19 +136,22 @@ void AppleDWARFIndex::SearchFor(const llvm::AppleAcceleratorTable &table, } void AppleDWARFIndex::GetGlobalVariables( - ConstString basename, llvm::function_ref<bool(DWARFDIE die)> callback) { + ConstString basename, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { if (!m_apple_names_up) return; - SearchFor(*m_apple_names_up, basename, callback); + SearchFor(*m_apple_names_up, basename, IterationActionAdaptor(callback)); } void AppleDWARFIndex::GetGlobalVariables( const RegularExpression ®ex, - llvm::function_ref<bool(DWARFDIE die)> callback) { + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { if (!m_apple_names_up) return; - DIERefCallbackImpl converted_cb = DIERefCallback(callback, regex.GetText()); + auto adataped_cb = IterationActionAdaptor(callback); + DIERefCallbackImpl converted_cb = + DIERefCallback(adataped_cb, regex.GetText()); for (const auto &entry : m_apple_names_up->entries()) if (std::optional<llvm::StringRef> name = entry.readName(); @@ -158,7 +161,7 @@ void AppleDWARFIndex::GetGlobalVariables( } void AppleDWARFIndex::GetGlobalVariables( - DWARFUnit &cu, llvm::function_ref<bool(DWARFDIE die)> callback) { + DWARFUnit &cu, llvm::function_ref<IterationAction(DWARFDIE die)> callback) { if (!m_apple_names_up) return; @@ -169,7 +172,8 @@ void AppleDWARFIndex::GetGlobalVariables( return val.has_value() && *val >= lower_bound && *val < upper_bound; }; - DIERefCallbackImpl converted_cb = DIERefCallback(callback); + auto adataped_cb = IterationActionAdaptor(callback); + DIERefCallbackImpl converted_cb = DIERefCallback(adataped_cb); for (auto entry : m_apple_names_up->entries()) { if (is_in_range(entry.BaseEntry.getDIESectionOffset())) if (!converted_cb(entry.BaseEntry)) @@ -267,10 +271,11 @@ void AppleDWARFIndex::GetTypes( } void AppleDWARFIndex::GetNamespaces( - ConstString name, llvm::function_ref<bool(DWARFDIE die)> callback) { + ConstString name, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { if (!m_apple_namespaces_up) return; - SearchFor(*m_apple_namespaces_up, name, callback); + SearchFor(*m_apple_namespaces_up, name, IterationActionAdaptor(callback)); } void AppleDWARFIndex::GetFunctions( @@ -298,7 +303,7 @@ void AppleDWARFIndex::GetFunctions( void AppleDWARFIndex::GetFunctions( const RegularExpression ®ex, llvm::function_ref<IterationAction(DWARFDIE die)> callback) { - return GetGlobalVariables(regex, IterationActionAdaptor(callback)); + return GetGlobalVariables(regex, callback); } void AppleDWARFIndex::Dump(Stream &s) { diff --git a/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.h index c0f0eb6..74da0b2 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.h @@ -41,15 +41,15 @@ public: void Preload() override {} - void - GetGlobalVariables(ConstString basename, - llvm::function_ref<bool(DWARFDIE die)> callback) override; - void - GetGlobalVariables(const RegularExpression ®ex, - llvm::function_ref<bool(DWARFDIE die)> callback) override; - void - GetGlobalVariables(DWARFUnit &cu, - llvm::function_ref<bool(DWARFDIE die)> callback) override; + void GetGlobalVariables( + ConstString basename, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; + void GetGlobalVariables( + const RegularExpression ®ex, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; + void GetGlobalVariables( + DWARFUnit &cu, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; void GetObjCMethods(ConstString class_name, llvm::function_ref<bool(DWARFDIE die)> callback) override; void GetCompleteObjCClass( @@ -59,8 +59,9 @@ public: llvm::function_ref<bool(DWARFDIE die)> callback) override; void GetTypes(const DWARFDeclContext &context, llvm::function_ref<bool(DWARFDIE die)> callback) override; - void GetNamespaces(ConstString name, - llvm::function_ref<bool(DWARFDIE die)> callback) override; + void GetNamespaces( + ConstString name, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; void GetFunctions( const Module::LookupInfo &lookup_info, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp index a806506..5791030 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp @@ -165,16 +165,16 @@ bool DWARFIndex::ProcessTypeDIEMatchQuery( void DWARFIndex::GetNamespacesWithParents( ConstString name, const CompilerDeclContext &parent_decl_ctx, - llvm::function_ref<bool(DWARFDIE die)> callback) { + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { GetNamespaces(name, [&](DWARFDIE die) { return ProcessNamespaceDieMatchParents(parent_decl_ctx, die, callback); }); } -bool DWARFIndex::ProcessNamespaceDieMatchParents( +IterationAction DWARFIndex::ProcessNamespaceDieMatchParents( const CompilerDeclContext &parent_decl_ctx, DWARFDIE die, - llvm::function_ref<bool(DWARFDIE die)> callback) { + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { if (!SymbolFileDWARF::DIEInDeclContext(parent_decl_ctx, die)) - return true; + return IterationAction::Continue; return callback(die); } diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h index 3578824..6718024 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h @@ -33,17 +33,17 @@ public: /// Finds global variables with the given base name. Any additional filtering /// (e.g., to only retrieve variables from a given context) should be done by /// the consumer. - virtual void - GetGlobalVariables(ConstString basename, - llvm::function_ref<bool(DWARFDIE die)> callback) = 0; + virtual void GetGlobalVariables( + ConstString basename, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) = 0; - virtual void - GetGlobalVariables(const RegularExpression ®ex, - llvm::function_ref<bool(DWARFDIE die)> callback) = 0; + virtual void GetGlobalVariables( + const RegularExpression ®ex, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) = 0; /// \a cu must be the skeleton unit if possible, not GetNonSkeletonUnit(). - virtual void - GetGlobalVariables(DWARFUnit &cu, - llvm::function_ref<bool(DWARFDIE die)> callback) = 0; + virtual void GetGlobalVariables( + DWARFUnit &cu, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) = 0; virtual void GetObjCMethods(ConstString class_name, llvm::function_ref<bool(DWARFDIE die)> callback) = 0; @@ -64,7 +64,7 @@ public: llvm::function_ref<bool(DWARFDIE die)> callback); virtual void GetNamespaces(ConstString name, - llvm::function_ref<bool(DWARFDIE die)> callback) = 0; + llvm::function_ref<IterationAction(DWARFDIE die)> callback) = 0; /// Get type DIEs meeting requires of \a query. /// in its decl parent chain as subset. A base implementation is provided, /// Specializations should override this if they are able to provide a faster @@ -76,10 +76,9 @@ public: /// parent_decl_ctx in its decl parent chain. A base implementation /// is provided. Specializations should override this if they are able to /// provide a faster implementation. - virtual void - GetNamespacesWithParents(ConstString name, - const CompilerDeclContext &parent_decl_ctx, - llvm::function_ref<bool(DWARFDIE die)> callback); + virtual void GetNamespacesWithParents( + ConstString name, const CompilerDeclContext &parent_decl_ctx, + llvm::function_ref<IterationAction(DWARFDIE die)> callback); virtual void GetFunctions(const Module::LookupInfo &lookup_info, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, @@ -139,9 +138,9 @@ protected: bool ProcessTypeDIEMatchQuery(TypeQuery &query, DWARFDIE die, llvm::function_ref<bool(DWARFDIE die)> callback); - bool ProcessNamespaceDieMatchParents( + IterationAction ProcessNamespaceDieMatchParents( const CompilerDeclContext &parent_decl_ctx, DWARFDIE die, - llvm::function_ref<bool(DWARFDIE die)> callback); + llvm::function_ref<IterationAction(DWARFDIE die)> callback); /// Helper to convert callbacks that return an \c IterationAction /// to a callback that returns a \c bool, where \c true indicates diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp index 3ae9fcc..8944005 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp @@ -178,13 +178,14 @@ void DebugNamesDWARFIndex::MaybeLogLookupError(llvm::Error error, } void DebugNamesDWARFIndex::GetGlobalVariables( - ConstString basename, llvm::function_ref<bool(DWARFDIE die)> callback) { + ConstString basename, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { for (const DebugNames::Entry &entry : m_debug_names_up->equal_range(basename.GetStringRef())) { if (entry.tag() != DW_TAG_variable) continue; - if (!ProcessEntry(entry, callback)) + if (!ProcessEntry(entry, IterationActionAdaptor(callback))) return; } @@ -193,7 +194,7 @@ void DebugNamesDWARFIndex::GetGlobalVariables( void DebugNamesDWARFIndex::GetGlobalVariables( const RegularExpression ®ex, - llvm::function_ref<bool(DWARFDIE die)> callback) { + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { for (const DebugNames::NameIndex &ni: *m_debug_names_up) { for (DebugNames::NameTableEntry nte: ni) { Mangled mangled_name(nte.getString()); @@ -206,7 +207,7 @@ void DebugNamesDWARFIndex::GetGlobalVariables( if (entry_or->tag() != DW_TAG_variable) continue; - if (!ProcessEntry(*entry_or, callback)) + if (!ProcessEntry(*entry_or, IterationActionAdaptor(callback))) return; } MaybeLogLookupError(entry_or.takeError(), ni, nte.getString()); @@ -217,7 +218,7 @@ void DebugNamesDWARFIndex::GetGlobalVariables( } void DebugNamesDWARFIndex::GetGlobalVariables( - DWARFUnit &cu, llvm::function_ref<bool(DWARFDIE die)> callback) { + DWARFUnit &cu, llvm::function_ref<IterationAction(DWARFDIE die)> callback) { uint64_t cu_offset = cu.GetOffset(); bool found_entry_for_cu = false; for (const DebugNames::NameIndex &ni : *m_debug_names_up) { @@ -242,7 +243,7 @@ void DebugNamesDWARFIndex::GetGlobalVariables( continue; found_entry_for_cu = true; - if (!ProcessEntry(*entry_or, callback)) + if (!ProcessEntry(*entry_or, IterationActionAdaptor(callback))) return; } MaybeLogLookupError(entry_or.takeError(), ni, nte.getString()); @@ -482,13 +483,14 @@ void DebugNamesDWARFIndex::GetTypes( } void DebugNamesDWARFIndex::GetNamespaces( - ConstString name, llvm::function_ref<bool(DWARFDIE die)> callback) { + ConstString name, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { for (const DebugNames::Entry &entry : m_debug_names_up->equal_range(name.GetStringRef())) { llvm::dwarf::Tag entry_tag = entry.tag(); if (entry_tag == DW_TAG_namespace || entry_tag == DW_TAG_imported_declaration) { - if (!ProcessEntry(entry, callback)) + if (!ProcessEntry(entry, IterationActionAdaptor(callback))) return; } } @@ -566,7 +568,7 @@ void DebugNamesDWARFIndex::GetTypesWithQuery( void DebugNamesDWARFIndex::GetNamespacesWithParents( ConstString name, const CompilerDeclContext &parent_decl_ctx, - llvm::function_ref<bool(DWARFDIE die)> callback) { + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { std::vector<lldb_private::CompilerContext> parent_contexts = parent_decl_ctx.GetCompilerContext(); llvm::SmallVector<CompilerContext> parent_named_contexts; @@ -582,21 +584,22 @@ void DebugNamesDWARFIndex::GetNamespacesWithParents( getParentChain(entry); if (!parent_chain) { // Fallback: use the base class implementation. - if (!ProcessEntry(entry, [&](DWARFDIE die) { - return ProcessNamespaceDieMatchParents(parent_decl_ctx, die, - callback); - })) + if (!ProcessEntry(entry, IterationActionAdaptor([&](DWARFDIE die) { + return ProcessNamespaceDieMatchParents( + parent_decl_ctx, die, callback); + }))) return; continue; } if (WithinParentChain(parent_named_contexts, *parent_chain)) { - if (!ProcessEntry(entry, [&](DWARFDIE die) { - // After .debug_names filtering still sending to base class for - // further filtering before calling the callback. - return ProcessNamespaceDieMatchParents(parent_decl_ctx, die, - callback); - })) + if (!ProcessEntry(entry, IterationActionAdaptor([&](DWARFDIE die) { + // After .debug_names filtering still sending to + // base class for further filtering before calling + // the callback. + return ProcessNamespaceDieMatchParents( + parent_decl_ctx, die, callback); + }))) // If the callback returns false, we're done. return; } diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h index 2105919..deee6b7 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h @@ -13,6 +13,7 @@ #include "Plugins/SymbolFile/DWARF/ManualDWARFIndex.h" #include "Plugins/SymbolFile/DWARF/SymbolFileDWARF.h" #include "lldb/Utility/ConstString.h" +#include "lldb/lldb-private-enumerations.h" #include "llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h" #include <optional> @@ -26,15 +27,15 @@ public: void Preload() override { m_fallback.Preload(); } - void - GetGlobalVariables(ConstString basename, - llvm::function_ref<bool(DWARFDIE die)> callback) override; - void - GetGlobalVariables(const RegularExpression ®ex, - llvm::function_ref<bool(DWARFDIE die)> callback) override; - void - GetGlobalVariables(DWARFUnit &cu, - llvm::function_ref<bool(DWARFDIE die)> callback) override; + void GetGlobalVariables( + ConstString basename, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; + void GetGlobalVariables( + const RegularExpression ®ex, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; + void GetGlobalVariables( + DWARFUnit &cu, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; void GetObjCMethods(ConstString class_name, llvm::function_ref<bool(DWARFDIE die)> callback) override {} @@ -50,14 +51,15 @@ public: llvm::function_ref<bool(DWARFDIE die)> callback) override; void GetTypes(const DWARFDeclContext &context, llvm::function_ref<bool(DWARFDIE die)> callback) override; - void GetNamespaces(ConstString name, - llvm::function_ref<bool(DWARFDIE die)> callback) override; + void GetNamespaces( + ConstString name, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; void GetTypesWithQuery(TypeQuery &query, llvm::function_ref<bool(DWARFDIE die)> callback) override; void GetNamespacesWithParents( ConstString name, const CompilerDeclContext &parent_decl_ctx, - llvm::function_ref<bool(DWARFDIE die)> callback) override; + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; void GetFunctions( const Module::LookupInfo &lookup_info, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp index f96ac7e..4517927 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp @@ -414,23 +414,27 @@ void ManualDWARFIndex::IndexUnitImpl(DWARFUnit &unit, } void ManualDWARFIndex::GetGlobalVariables( - ConstString basename, llvm::function_ref<bool(DWARFDIE die)> callback) { + ConstString basename, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { Index(); - m_set.globals.Find(basename, - DIERefCallback(callback, basename.GetStringRef())); + m_set.globals.Find(basename, DIERefCallback(IterationActionAdaptor(callback), + basename.GetStringRef())); } void ManualDWARFIndex::GetGlobalVariables( const RegularExpression ®ex, - llvm::function_ref<bool(DWARFDIE die)> callback) { + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { Index(); - m_set.globals.Find(regex, DIERefCallback(callback, regex.GetText())); + m_set.globals.Find( + regex, DIERefCallback(IterationActionAdaptor(callback), regex.GetText())); } void ManualDWARFIndex::GetGlobalVariables( - DWARFUnit &unit, llvm::function_ref<bool(DWARFDIE die)> callback) { + DWARFUnit &unit, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { Index(); - m_set.globals.FindAllEntriesForUnit(unit, DIERefCallback(callback)); + m_set.globals.FindAllEntriesForUnit( + unit, DIERefCallback(IterationActionAdaptor(callback))); } void ManualDWARFIndex::GetObjCMethods( @@ -464,9 +468,11 @@ void ManualDWARFIndex::GetTypes( } void ManualDWARFIndex::GetNamespaces( - ConstString name, llvm::function_ref<bool(DWARFDIE die)> callback) { + ConstString name, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) { Index(); - m_set.namespaces.Find(name, DIERefCallback(callback, name.GetStringRef())); + m_set.namespaces.Find(name, DIERefCallback(IterationActionAdaptor(callback), + name.GetStringRef())); } void ManualDWARFIndex::GetFunctions( diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h index 5685ba4..746170c 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h @@ -12,6 +12,7 @@ #include "Plugins/SymbolFile/DWARF/DWARFIndex.h" #include "Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h" #include "Plugins/SymbolFile/DWARF/NameToDIE.h" +#include "lldb/lldb-private-enumerations.h" #include "llvm/ADT/DenseSet.h" namespace lldb_private::plugin { @@ -30,15 +31,15 @@ public: void Preload() override { Index(); } - void - GetGlobalVariables(ConstString basename, - llvm::function_ref<bool(DWARFDIE die)> callback) override; - void - GetGlobalVariables(const RegularExpression ®ex, - llvm::function_ref<bool(DWARFDIE die)> callback) override; - void - GetGlobalVariables(DWARFUnit &unit, - llvm::function_ref<bool(DWARFDIE die)> callback) override; + void GetGlobalVariables( + ConstString basename, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; + void GetGlobalVariables( + const RegularExpression ®ex, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; + void GetGlobalVariables( + DWARFUnit &unit, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; void GetObjCMethods(ConstString class_name, llvm::function_ref<bool(DWARFDIE die)> callback) override; void GetCompleteObjCClass( @@ -48,8 +49,9 @@ public: llvm::function_ref<bool(DWARFDIE die)> callback) override; void GetTypes(const DWARFDeclContext &context, llvm::function_ref<bool(DWARFDIE die)> callback) override; - void GetNamespaces(ConstString name, - llvm::function_ref<bool(DWARFDIE die)> callback) override; + void GetNamespaces( + ConstString name, + llvm::function_ref<IterationAction(DWARFDIE die)> callback) override; void GetFunctions( const Module::LookupInfo &lookup_info, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp index a3ba061..42a66ce 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp @@ -2349,11 +2349,11 @@ void SymbolFileDWARF::FindGlobalVariables( assert(sc.module_sp); if (die.Tag() != DW_TAG_variable && die.Tag() != DW_TAG_member) - return true; + return IterationAction::Continue; auto *dwarf_cu = llvm::dyn_cast<DWARFCompileUnit>(die.GetCU()); if (!dwarf_cu) - return true; + return IterationAction::Continue; sc.comp_unit = GetCompUnitForDWARFCompUnit(*dwarf_cu); if (parent_decl_ctx) { @@ -2368,7 +2368,7 @@ void SymbolFileDWARF::FindGlobalVariables( if (!actual_parent_decl_ctx || (actual_parent_decl_ctx != parent_decl_ctx && !parent_decl_ctx.IsContainedInLookup(actual_parent_decl_ctx))) - return true; + return IterationAction::Continue; } } @@ -2382,7 +2382,10 @@ void SymbolFileDWARF::FindGlobalVariables( variables.RemoveVariableAtIndex(pruned_idx); } - return variables.GetSize() - original_size < max_matches; + if (variables.GetSize() - original_size < max_matches) + return IterationAction::Continue; + + return IterationAction::Stop; }); // Return the number of variable that were appended to the list @@ -2422,12 +2425,15 @@ void SymbolFileDWARF::FindGlobalVariables(const RegularExpression ®ex, DWARFCompileUnit *dwarf_cu = llvm::dyn_cast<DWARFCompileUnit>(die.GetCU()); if (!dwarf_cu) - return true; + return IterationAction::Continue; sc.comp_unit = GetCompUnitForDWARFCompUnit(*dwarf_cu); ParseAndAppendGlobalVariable(sc, die, variables); - return variables.GetSize() - original_size < max_matches; + if (variables.GetSize() - original_size < max_matches) + return IterationAction::Continue; + + return IterationAction::Stop; }); } @@ -2847,14 +2853,17 @@ SymbolFileDWARF::FindNamespace(ConstString name, m_index->GetNamespacesWithParents(name, parent_decl_ctx, [&](DWARFDIE die) { if (!DIEInDeclContext(parent_decl_ctx, die, only_root_namespaces)) - return true; // The containing decl contexts don't match + return IterationAction::Continue; DWARFASTParser *dwarf_ast = GetDWARFParser(*die.GetCU()); if (!dwarf_ast) - return true; + return IterationAction::Continue; namespace_decl_ctx = dwarf_ast->GetDeclContextForUIDFromDWARF(die); - return !namespace_decl_ctx.IsValid(); + if (namespace_decl_ctx.IsValid()) + return IterationAction::Stop; + + return IterationAction::Continue; }); if (log && namespace_decl_ctx) { @@ -3295,7 +3304,7 @@ size_t SymbolFileDWARF::ParseVariablesForContext(const SymbolContext &sc) { variables->AddVariableIfUnique(var_sp); ++vars_added; } - return true; + return IterationAction::Continue; }); } return vars_added; diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp index 9301f92..8dd6aa0 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp @@ -616,10 +616,10 @@ void TypeSystemClang::SetTargetTriple(llvm::StringRef target_triple) { } void TypeSystemClang::SetExternalSource( - llvm::IntrusiveRefCntPtr<ExternalASTSource> &ast_source_up) { + llvm::IntrusiveRefCntPtr<ExternalASTSource> ast_source_sp) { ASTContext &ast = getASTContext(); ast.getTranslationUnitDecl()->setHasExternalLexicalStorage(true); - ast.setExternalSource(ast_source_up); + ast.setExternalSource(std::move(ast_source_sp)); } ASTContext &TypeSystemClang::getASTContext() const { @@ -702,9 +702,9 @@ void TypeSystemClang::CreateASTContext() { GetASTMap().Insert(m_ast_up.get(), this); - llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> ast_source_up( - new ClangExternalASTSourceCallbacks(*this)); - SetExternalSource(ast_source_up); + auto ast_source_sp = + llvm::makeIntrusiveRefCnt<ClangExternalASTSourceCallbacks>(*this); + SetExternalSource(ast_source_sp); } TypeSystemClang *TypeSystemClang::GetASTContext(clang::ASTContext *ast) { @@ -9620,8 +9620,8 @@ public: m_scratch_ast_source_up(std::move(ast_source)) { // Setup the ClangASTSource to complete this AST. m_scratch_ast_source_up->InstallASTContext(*this); - llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> proxy_ast_source( - m_scratch_ast_source_up->CreateProxy()); + llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> proxy_ast_source = + m_scratch_ast_source_up->CreateProxy(); SetExternalSource(proxy_ast_source); } @@ -9641,8 +9641,8 @@ ScratchTypeSystemClang::ScratchTypeSystemClang(Target &target, new ClangPersistentVariables(target.shared_from_this())) { m_scratch_ast_source_up = CreateASTSource(); m_scratch_ast_source_up->InstallASTContext(*this); - llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> proxy_ast_source( - m_scratch_ast_source_up->CreateProxy()); + llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> proxy_ast_source = + m_scratch_ast_source_up->CreateProxy(); SetExternalSource(proxy_ast_source); } diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h index 5431d12..70d613d 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h @@ -178,7 +178,7 @@ public: const char *GetTargetTriple(); void SetExternalSource( - llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> &ast_source_up); + llvm::IntrusiveRefCntPtr<clang::ExternalASTSource> ast_source_sp); bool GetCompleteDecl(clang::Decl *decl) { return TypeSystemClang::GetCompleteDecl(&getASTContext(), decl); diff --git a/lldb/test/API/functionalities/tail_call_frames/cross_dso/TestCrossDSOTailCalls.py b/lldb/test/API/functionalities/tail_call_frames/cross_dso/TestCrossDSOTailCalls.py index 0ca2f9e5..41cb185 100644 --- a/lldb/test/API/functionalities/tail_call_frames/cross_dso/TestCrossDSOTailCalls.py +++ b/lldb/test/API/functionalities/tail_call_frames/cross_dso/TestCrossDSOTailCalls.py @@ -8,7 +8,7 @@ from lldbsuite.test import lldbutil class TestCrossDSOTailCalls(TestBase): - @skipIf(compiler="clang", compiler_version=["<", "10.0"]) + @skipIf(compiler="clang", compiler_version=["<", "22.0"]) @skipIf(dwarf_version=["<", "4"]) @expectedFailureAll(oslist=["windows"], bugnumber="llvm.org/pr26265") def test_cross_dso_tail_calls(self): diff --git a/lldb/test/API/functionalities/tail_call_frames/cross_object/TestCrossObjectTailCalls.py b/lldb/test/API/functionalities/tail_call_frames/cross_object/TestCrossObjectTailCalls.py index b5de75e..b652fb8 100644 --- a/lldb/test/API/functionalities/tail_call_frames/cross_object/TestCrossObjectTailCalls.py +++ b/lldb/test/API/functionalities/tail_call_frames/cross_object/TestCrossObjectTailCalls.py @@ -8,7 +8,7 @@ from lldbsuite.test import lldbutil class TestCrossObjectTailCalls(TestBase): - @skipIf(compiler="clang", compiler_version=["<", "10.0"]) + @skipIf(compiler="clang", compiler_version=["<", "22.0"]) @skipIf(dwarf_version=["<", "4"]) @expectedFailureAll(oslist=["windows"], bugnumber="llvm.org/pr26265") def test_cross_object_tail_calls(self): diff --git a/llvm/docs/CommandGuide/llvm-ir2vec.rst b/llvm/docs/CommandGuide/llvm-ir2vec.rst index 2f00c9f..0c9fb6e 100644 --- a/llvm/docs/CommandGuide/llvm-ir2vec.rst +++ b/llvm/docs/CommandGuide/llvm-ir2vec.rst @@ -6,27 +6,27 @@ llvm-ir2vec - IR2Vec Embedding Generation Tool SYNOPSIS -------- -:program:`llvm-ir2vec` [*options*] *input-file* +:program:`llvm-ir2vec` [*subcommand*] [*options*] DESCRIPTION ----------- :program:`llvm-ir2vec` is a standalone command-line tool for IR2Vec. It generates IR2Vec embeddings for LLVM IR and supports triplet generation -for vocabulary training. It provides three main operation modes: +for vocabulary training. The tool provides three main subcommands: -1. **Triplet Mode**: Generates numeric triplets in train2id format for vocabulary +1. **triplets**: Generates numeric triplets in train2id format for vocabulary training from LLVM IR. -2. **Entity Mode**: Generates entity mapping files (entity2id.txt) for vocabulary +2. **entities**: Generates entity mapping files (entity2id.txt) for vocabulary training. -3. **Embedding Mode**: Generates IR2Vec embeddings using a trained vocabulary +3. **embeddings**: Generates IR2Vec embeddings using a trained vocabulary at different granularity levels (instruction, basic block, or function). The tool is designed to facilitate machine learning applications that work with LLVM IR by converting the IR into numerical representations that can be used by -ML models. The triplet mode generates numeric IDs directly instead of string +ML models. The `triplets` subcommand generates numeric IDs directly instead of string triplets, streamlining the training data preparation workflow. .. note:: @@ -53,111 +53,115 @@ for details). See `llvm/utils/mlgo-utils/IR2Vec/generateTriplets.py` for more details on how these two modes are used to generate the triplets and entity mappings. -Triplet Generation Mode -~~~~~~~~~~~~~~~~~~~~~~~ +Triplet Generation +~~~~~~~~~~~~~~~~~~ -In triplet mode, :program:`llvm-ir2vec` analyzes LLVM IR and extracts numeric -triplets consisting of opcode IDs, type IDs, and operand IDs. These triplets -are generated in the standard format used for knowledge graph embedding training. -The tool outputs numeric IDs directly using the ir2vec::Vocabulary mapping +With the `triplets` subcommand, :program:`llvm-ir2vec` analyzes LLVM IR and extracts +numeric triplets consisting of opcode IDs, type IDs, and operand IDs. These triplets +are generated in the standard format used for knowledge graph embedding training. +The tool outputs numeric IDs directly using the ir2vec::Vocabulary mapping infrastructure, eliminating the need for string-to-ID preprocessing. Usage: .. code-block:: bash - llvm-ir2vec --mode=triplets input.bc -o triplets_train2id.txt + llvm-ir2vec triplets input.bc -o triplets_train2id.txt -Entity Mapping Generation Mode -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Entity Mapping Generation +~~~~~~~~~~~~~~~~~~~~~~~~~ -In entity mode, :program:`llvm-ir2vec` generates the entity mappings supported by -IR2Vec in the standard format used for knowledge graph embedding training. This -mode outputs all supported entities (opcodes, types, and operands) with their -corresponding numeric IDs, and is not specific for an LLVM IR file. +With the `entities` subcommand, :program:`llvm-ir2vec` generates the entity mappings +supported by IR2Vec in the standard format used for knowledge graph embedding +training. This subcommand outputs all supported entities (opcodes, types, and +operands) with their corresponding numeric IDs, and is not specific for an +LLVM IR file. Usage: .. code-block:: bash - llvm-ir2vec --mode=entities -o entity2id.txt + llvm-ir2vec entities -o entity2id.txt -Embedding Generation Mode -~~~~~~~~~~~~~~~~~~~~~~~~~~ +Embedding Generation +~~~~~~~~~~~~~~~~~~~~ -In embedding mode, :program:`llvm-ir2vec` uses a pre-trained vocabulary to +With the `embeddings` subcommand, :program:`llvm-ir2vec` uses a pre-trained vocabulary to generate numerical embeddings for LLVM IR at different levels of granularity. Example Usage: .. code-block:: bash - llvm-ir2vec --mode=embeddings --ir2vec-vocab-path=vocab.json --level=func input.bc -o embeddings.txt + llvm-ir2vec embeddings --ir2vec-vocab-path=vocab.json --level=func input.bc -o embeddings.txt OPTIONS ------- -.. option:: --mode=<mode> +Global options: + +.. option:: -o <filename> + + Specify the output filename. Use ``-`` to write to standard output (default). + +.. option:: --help + + Print a summary of command line options. - Specify the operation mode. Valid values are: +Subcommand-specific options: - * ``triplets`` - Generate triplets for vocabulary training - * ``entities`` - Generate entity mappings for vocabulary training - * ``embeddings`` - Generate embeddings using trained vocabulary (default) +**embeddings** subcommand: + +.. option:: <input-file> + + The input LLVM IR or bitcode file to process. This positional argument is + required for the `embeddings` subcommand. .. option:: --level=<level> - Specify the embedding generation level. Valid values are: + Specify the embedding generation level. Valid values are: - * ``inst`` - Generate instruction-level embeddings - * ``bb`` - Generate basic block-level embeddings - * ``func`` - Generate function-level embeddings (default) + * ``inst`` - Generate instruction-level embeddings + * ``bb`` - Generate basic block-level embeddings + * ``func`` - Generate function-level embeddings (default) .. option:: --function=<name> - Process only the specified function instead of all functions in the module. + Process only the specified function instead of all functions in the module. .. option:: --ir2vec-vocab-path=<path> - Specify the path to the vocabulary file (required for embedding mode). - The vocabulary file should be in JSON format and contain the trained - vocabulary for embedding generation. See `llvm/lib/Analysis/models` - for pre-trained vocabulary files. + Specify the path to the vocabulary file (required for embedding generation). + The vocabulary file should be in JSON format and contain the trained + vocabulary for embedding generation. See `llvm/lib/Analysis/models` + for pre-trained vocabulary files. .. option:: --ir2vec-opc-weight=<weight> - Specify the weight for opcode embeddings (default: 1.0). This controls - the relative importance of instruction opcodes in the final embedding. + Specify the weight for opcode embeddings (default: 1.0). This controls + the relative importance of instruction opcodes in the final embedding. .. option:: --ir2vec-type-weight=<weight> - Specify the weight for type embeddings (default: 0.5). This controls - the relative importance of type information in the final embedding. + Specify the weight for type embeddings (default: 0.5). This controls + the relative importance of type information in the final embedding. .. option:: --ir2vec-arg-weight=<weight> - Specify the weight for argument embeddings (default: 0.2). This controls - the relative importance of operand information in the final embedding. + Specify the weight for argument embeddings (default: 0.2). This controls + the relative importance of operand information in the final embedding. -.. option:: -o <filename> - Specify the output filename. Use ``-`` to write to standard output (default). +**triplets** subcommand: -.. option:: --help - - Print a summary of command line options. - -.. note:: +.. option:: <input-file> - ``--level``, ``--function``, ``--ir2vec-vocab-path``, ``--ir2vec-opc-weight``, - ``--ir2vec-type-weight``, and ``--ir2vec-arg-weight`` are only used in embedding - mode. These options are ignored in triplet and entity modes. + The input LLVM IR or bitcode file to process. This positional argument is + required for the `triplets` subcommand. -INPUT FILE FORMAT ------------------ +**entities** subcommand: -:program:`llvm-ir2vec` accepts LLVM bitcode files (``.bc``) and LLVM IR files -(``.ll``) as input. The input file should contain valid LLVM IR. + No subcommand-specific options. OUTPUT FORMAT ------------- diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td index 4551e7e..b06158d 100644 --- a/llvm/include/llvm/CodeGen/ValueTypes.td +++ b/llvm/include/llvm/CodeGen/ValueTypes.td @@ -92,258 +92,270 @@ def v1i1 : VTVec<1, i1, 17>; // 1 x i1 vector value def v2i1 : VTVec<2, i1, 18>; // 2 x i1 vector value def v3i1 : VTVec<3, i1, 19>; // 3 x i1 vector value def v4i1 : VTVec<4, i1, 20>; // 4 x i1 vector value -def v8i1 : VTVec<8, i1, 21>; // 8 x i1 vector value -def v16i1 : VTVec<16, i1, 22>; // 16 x i1 vector value -def v32i1 : VTVec<32, i1, 23>; // 32 x i1 vector value -def v64i1 : VTVec<64, i1, 24>; // 64 x i1 vector value -def v128i1 : VTVec<128, i1, 25>; // 128 x i1 vector value -def v256i1 : VTVec<256, i1, 26>; // 256 x i1 vector value -def v512i1 : VTVec<512, i1, 27>; // 512 x i1 vector value -def v1024i1 : VTVec<1024, i1, 28>; // 1024 x i1 vector value -def v2048i1 : VTVec<2048, i1, 29>; // 2048 x i1 vector value -def v4096i1 : VTVec<4096, i1, 30>; // 4096 x i1 vector value - -def v128i2 : VTVec<128, i2, 31>; // 128 x i2 vector value -def v256i2 : VTVec<256, i2, 32>; // 256 x i2 vector value - -def v64i4 : VTVec<64, i4, 33>; // 64 x i4 vector value -def v128i4 : VTVec<128, i4, 34>; // 128 x i4 vector value - -def v1i8 : VTVec<1, i8, 35>; // 1 x i8 vector value -def v2i8 : VTVec<2, i8, 36>; // 2 x i8 vector value -def v3i8 : VTVec<3, i8, 37>; // 3 x i8 vector value -def v4i8 : VTVec<4, i8, 38>; // 4 x i8 vector value -def v8i8 : VTVec<8, i8, 39>; // 8 x i8 vector value -def v16i8 : VTVec<16, i8, 40>; // 16 x i8 vector value -def v32i8 : VTVec<32, i8, 41>; // 32 x i8 vector value -def v64i8 : VTVec<64, i8, 42>; // 64 x i8 vector value -def v128i8 : VTVec<128, i8, 43>; // 128 x i8 vector value -def v256i8 : VTVec<256, i8, 44>; // 256 x i8 vector value -def v512i8 : VTVec<512, i8, 45>; // 512 x i8 vector value -def v1024i8 : VTVec<1024, i8, 46>; // 1024 x i8 vector value - -def v1i16 : VTVec<1, i16, 47>; // 1 x i16 vector value -def v2i16 : VTVec<2, i16, 48>; // 2 x i16 vector value -def v3i16 : VTVec<3, i16, 49>; // 3 x i16 vector value -def v4i16 : VTVec<4, i16, 50>; // 4 x i16 vector value -def v8i16 : VTVec<8, i16, 51>; // 8 x i16 vector value -def v16i16 : VTVec<16, i16, 52>; // 16 x i16 vector value -def v32i16 : VTVec<32, i16, 53>; // 32 x i16 vector value -def v64i16 : VTVec<64, i16, 54>; // 64 x i16 vector value -def v128i16 : VTVec<128, i16, 55>; // 128 x i16 vector value -def v256i16 : VTVec<256, i16, 56>; // 256 x i16 vector value -def v512i16 : VTVec<512, i16, 57>; // 512 x i16 vector value -def v4096i16 : VTVec<4096, i16, 58>; // 4096 x i16 vector value - -def v1i32 : VTVec<1, i32, 59>; // 1 x i32 vector value -def v2i32 : VTVec<2, i32, 60>; // 2 x i32 vector value -def v3i32 : VTVec<3, i32, 61>; // 3 x i32 vector value -def v4i32 : VTVec<4, i32, 62>; // 4 x i32 vector value -def v5i32 : VTVec<5, i32, 63>; // 5 x i32 vector value -def v6i32 : VTVec<6, i32, 64>; // 6 x f32 vector value -def v7i32 : VTVec<7, i32, 65>; // 7 x f32 vector value -def v8i32 : VTVec<8, i32, 66>; // 8 x i32 vector value -def v9i32 : VTVec<9, i32, 67>; // 9 x i32 vector value -def v10i32 : VTVec<10, i32, 68>; // 10 x i32 vector value -def v11i32 : VTVec<11, i32, 69>; // 11 x i32 vector value -def v12i32 : VTVec<12, i32, 70>; // 12 x i32 vector value -def v16i32 : VTVec<16, i32, 71>; // 16 x i32 vector value -def v32i32 : VTVec<32, i32, 72>; // 32 x i32 vector value -def v64i32 : VTVec<64, i32, 73>; // 64 x i32 vector value -def v128i32 : VTVec<128, i32, 74>; // 128 x i32 vector value -def v256i32 : VTVec<256, i32, 75>; // 256 x i32 vector value -def v512i32 : VTVec<512, i32, 76>; // 512 x i32 vector value -def v1024i32 : VTVec<1024, i32, 77>; // 1024 x i32 vector value -def v2048i32 : VTVec<2048, i32, 78>; // 2048 x i32 vector value -def v4096i32 : VTVec<4096, i32, 79>; // 4096 x i32 vector value - -def v1i64 : VTVec<1, i64, 80>; // 1 x i64 vector value -def v2i64 : VTVec<2, i64, 81>; // 2 x i64 vector value -def v3i64 : VTVec<3, i64, 82>; // 3 x i64 vector value -def v4i64 : VTVec<4, i64, 83>; // 4 x i64 vector value -def v8i64 : VTVec<8, i64, 84>; // 8 x i64 vector value -def v16i64 : VTVec<16, i64, 85>; // 16 x i64 vector value -def v32i64 : VTVec<32, i64, 86>; // 32 x i64 vector value -def v64i64 : VTVec<64, i64, 87>; // 64 x i64 vector value -def v128i64 : VTVec<128, i64, 88>; // 128 x i64 vector value -def v256i64 : VTVec<256, i64, 89>; // 256 x i64 vector value - -def v1i128 : VTVec<1, i128, 90>; // 1 x i128 vector value - -def v1f16 : VTVec<1, f16, 91>; // 1 x f16 vector value -def v2f16 : VTVec<2, f16, 92>; // 2 x f16 vector value -def v3f16 : VTVec<3, f16, 93>; // 3 x f16 vector value -def v4f16 : VTVec<4, f16, 94>; // 4 x f16 vector value -def v8f16 : VTVec<8, f16, 95>; // 8 x f16 vector value -def v16f16 : VTVec<16, f16, 96>; // 16 x f16 vector value -def v32f16 : VTVec<32, f16, 97>; // 32 x f16 vector value -def v64f16 : VTVec<64, f16, 98>; // 64 x f16 vector value -def v128f16 : VTVec<128, f16, 99>; // 128 x f16 vector value -def v256f16 : VTVec<256, f16, 100>; // 256 x f16 vector value -def v512f16 : VTVec<512, f16, 101>; // 512 x f16 vector value -def v4096f16 : VTVec<4096, f16, 102>; // 4096 x f16 vector value - -def v1bf16 : VTVec<1, bf16, 103>; // 1 x bf16 vector value -def v2bf16 : VTVec<2, bf16, 104>; // 2 x bf16 vector value -def v3bf16 : VTVec<3, bf16, 105>; // 3 x bf16 vector value -def v4bf16 : VTVec<4, bf16, 106>; // 4 x bf16 vector value -def v8bf16 : VTVec<8, bf16, 107>; // 8 x bf16 vector value -def v16bf16 : VTVec<16, bf16, 108>; // 16 x bf16 vector value -def v32bf16 : VTVec<32, bf16, 109>; // 32 x bf16 vector value -def v64bf16 : VTVec<64, bf16, 110>; // 64 x bf16 vector value -def v128bf16 : VTVec<128, bf16, 111>; // 128 x bf16 vector value -def v4096bf16 : VTVec<4096, bf16, 112>; // 4096 x bf16 vector value - -def v1f32 : VTVec<1, f32, 113>; // 1 x f32 vector value -def v2f32 : VTVec<2, f32, 114>; // 2 x f32 vector value -def v3f32 : VTVec<3, f32, 115>; // 3 x f32 vector value -def v4f32 : VTVec<4, f32, 116>; // 4 x f32 vector value -def v5f32 : VTVec<5, f32, 117>; // 5 x f32 vector value -def v6f32 : VTVec<6, f32, 118>; // 6 x f32 vector value -def v7f32 : VTVec<7, f32, 119>; // 7 x f32 vector value -def v8f32 : VTVec<8, f32, 120>; // 8 x f32 vector value -def v9f32 : VTVec<9, f32, 121>; // 9 x f32 vector value -def v10f32 : VTVec<10, f32, 122>; // 10 x f32 vector value -def v11f32 : VTVec<11, f32, 123>; // 11 x f32 vector value -def v12f32 : VTVec<12, f32, 124>; // 12 x f32 vector value -def v16f32 : VTVec<16, f32, 125>; // 16 x f32 vector value -def v32f32 : VTVec<32, f32, 126>; // 32 x f32 vector value -def v64f32 : VTVec<64, f32, 127>; // 64 x f32 vector value -def v128f32 : VTVec<128, f32, 128>; // 128 x f32 vector value -def v256f32 : VTVec<256, f32, 129>; // 256 x f32 vector value -def v512f32 : VTVec<512, f32, 130>; // 512 x f32 vector value -def v1024f32 : VTVec<1024, f32, 131>; // 1024 x f32 vector value -def v2048f32 : VTVec<2048, f32, 132>; // 2048 x f32 vector value - -def v1f64 : VTVec<1, f64, 133>; // 1 x f64 vector value -def v2f64 : VTVec<2, f64, 134>; // 2 x f64 vector value -def v3f64 : VTVec<3, f64, 135>; // 3 x f64 vector value -def v4f64 : VTVec<4, f64, 136>; // 4 x f64 vector value -def v8f64 : VTVec<8, f64, 137>; // 8 x f64 vector value -def v16f64 : VTVec<16, f64, 138>; // 16 x f64 vector value -def v32f64 : VTVec<32, f64, 139>; // 32 x f64 vector value -def v64f64 : VTVec<64, f64, 140>; // 64 x f64 vector value -def v128f64 : VTVec<128, f64, 141>; // 128 x f64 vector value -def v256f64 : VTVec<256, f64, 142>; // 256 x f64 vector value - -def nxv1i1 : VTScalableVec<1, i1, 143>; // n x 1 x i1 vector value -def nxv2i1 : VTScalableVec<2, i1, 144>; // n x 2 x i1 vector value -def nxv4i1 : VTScalableVec<4, i1, 145>; // n x 4 x i1 vector value -def nxv8i1 : VTScalableVec<8, i1, 146>; // n x 8 x i1 vector value -def nxv16i1 : VTScalableVec<16, i1, 147>; // n x 16 x i1 vector value -def nxv32i1 : VTScalableVec<32, i1, 148>; // n x 32 x i1 vector value -def nxv64i1 : VTScalableVec<64, i1, 149>; // n x 64 x i1 vector value - -def nxv1i8 : VTScalableVec<1, i8, 150>; // n x 1 x i8 vector value -def nxv2i8 : VTScalableVec<2, i8, 151>; // n x 2 x i8 vector value -def nxv4i8 : VTScalableVec<4, i8, 152>; // n x 4 x i8 vector value -def nxv8i8 : VTScalableVec<8, i8, 153>; // n x 8 x i8 vector value -def nxv16i8 : VTScalableVec<16, i8, 154>; // n x 16 x i8 vector value -def nxv32i8 : VTScalableVec<32, i8, 155>; // n x 32 x i8 vector value -def nxv64i8 : VTScalableVec<64, i8, 156>; // n x 64 x i8 vector value - -def nxv1i16 : VTScalableVec<1, i16, 157>; // n x 1 x i16 vector value -def nxv2i16 : VTScalableVec<2, i16, 158>; // n x 2 x i16 vector value -def nxv4i16 : VTScalableVec<4, i16, 159>; // n x 4 x i16 vector value -def nxv8i16 : VTScalableVec<8, i16, 160>; // n x 8 x i16 vector value -def nxv16i16 : VTScalableVec<16, i16, 161>; // n x 16 x i16 vector value -def nxv32i16 : VTScalableVec<32, i16, 162>; // n x 32 x i16 vector value - -def nxv1i32 : VTScalableVec<1, i32, 163>; // n x 1 x i32 vector value -def nxv2i32 : VTScalableVec<2, i32, 164>; // n x 2 x i32 vector value -def nxv4i32 : VTScalableVec<4, i32, 165>; // n x 4 x i32 vector value -def nxv8i32 : VTScalableVec<8, i32, 166>; // n x 8 x i32 vector value -def nxv16i32 : VTScalableVec<16, i32, 167>; // n x 16 x i32 vector value -def nxv32i32 : VTScalableVec<32, i32, 168>; // n x 32 x i32 vector value - -def nxv1i64 : VTScalableVec<1, i64, 169>; // n x 1 x i64 vector value -def nxv2i64 : VTScalableVec<2, i64, 170>; // n x 2 x i64 vector value -def nxv4i64 : VTScalableVec<4, i64, 171>; // n x 4 x i64 vector value -def nxv8i64 : VTScalableVec<8, i64, 172>; // n x 8 x i64 vector value -def nxv16i64 : VTScalableVec<16, i64, 173>; // n x 16 x i64 vector value -def nxv32i64 : VTScalableVec<32, i64, 174>; // n x 32 x i64 vector value - -def nxv1f16 : VTScalableVec<1, f16, 175>; // n x 1 x f16 vector value -def nxv2f16 : VTScalableVec<2, f16, 176>; // n x 2 x f16 vector value -def nxv4f16 : VTScalableVec<4, f16, 177>; // n x 4 x f16 vector value -def nxv8f16 : VTScalableVec<8, f16, 178>; // n x 8 x f16 vector value -def nxv16f16 : VTScalableVec<16, f16, 179>; // n x 16 x f16 vector value -def nxv32f16 : VTScalableVec<32, f16, 180>; // n x 32 x f16 vector value - -def nxv1bf16 : VTScalableVec<1, bf16, 181>; // n x 1 x bf16 vector value -def nxv2bf16 : VTScalableVec<2, bf16, 182>; // n x 2 x bf16 vector value -def nxv4bf16 : VTScalableVec<4, bf16, 183>; // n x 4 x bf16 vector value -def nxv8bf16 : VTScalableVec<8, bf16, 184>; // n x 8 x bf16 vector value -def nxv16bf16 : VTScalableVec<16, bf16, 185>; // n x 16 x bf16 vector value -def nxv32bf16 : VTScalableVec<32, bf16, 186>; // n x 32 x bf16 vector value - -def nxv1f32 : VTScalableVec<1, f32, 187>; // n x 1 x f32 vector value -def nxv2f32 : VTScalableVec<2, f32, 188>; // n x 2 x f32 vector value -def nxv4f32 : VTScalableVec<4, f32, 189>; // n x 4 x f32 vector value -def nxv8f32 : VTScalableVec<8, f32, 190>; // n x 8 x f32 vector value -def nxv16f32 : VTScalableVec<16, f32, 191>; // n x 16 x f32 vector value - -def nxv1f64 : VTScalableVec<1, f64, 192>; // n x 1 x f64 vector value -def nxv2f64 : VTScalableVec<2, f64, 193>; // n x 2 x f64 vector value -def nxv4f64 : VTScalableVec<4, f64, 194>; // n x 4 x f64 vector value -def nxv8f64 : VTScalableVec<8, f64, 195>; // n x 8 x f64 vector value +def v5i1 : VTVec<5, i1, 21>; // 5 x i1 vector value +def v6i1 : VTVec<6, i1, 22>; // 6 x i1 vector value +def v7i1 : VTVec<7, i1, 23>; // 7 x i1 vector value +def v8i1 : VTVec<8, i1, 24>; // 8 x i1 vector value +def v16i1 : VTVec<16, i1, 25>; // 16 x i1 vector value +def v32i1 : VTVec<32, i1, 26>; // 32 x i1 vector value +def v64i1 : VTVec<64, i1, 27>; // 64 x i1 vector value +def v128i1 : VTVec<128, i1, 28>; // 128 x i1 vector value +def v256i1 : VTVec<256, i1, 29>; // 256 x i1 vector value +def v512i1 : VTVec<512, i1, 30>; // 512 x i1 vector value +def v1024i1 : VTVec<1024, i1, 31>; // 1024 x i1 vector value +def v2048i1 : VTVec<2048, i1, 32>; // 2048 x i1 vector value +def v4096i1 : VTVec<4096, i1, 33>; // 4096 x i1 vector value + +def v128i2 : VTVec<128, i2, 34>; // 128 x i2 vector value +def v256i2 : VTVec<256, i2, 35>; // 256 x i2 vector value + +def v64i4 : VTVec<64, i4, 36>; // 64 x i4 vector value +def v128i4 : VTVec<128, i4, 37>; // 128 x i4 vector value + +def v1i8 : VTVec<1, i8, 38>; // 1 x i8 vector value +def v2i8 : VTVec<2, i8, 39>; // 2 x i8 vector value +def v3i8 : VTVec<3, i8, 40>; // 3 x i8 vector value +def v4i8 : VTVec<4, i8, 41>; // 4 x i8 vector value +def v5i8 : VTVec<5, i8, 42>; // 5 x i8 vector value +def v6i8 : VTVec<6, i8, 43>; // 6 x i8 vector value +def v7i8 : VTVec<7, i8, 44>; // 7 x i8 vector value +def v8i8 : VTVec<8, i8, 45>; // 8 x i8 vector value +def v16i8 : VTVec<16, i8, 46>; // 16 x i8 vector value +def v32i8 : VTVec<32, i8, 47>; // 32 x i8 vector value +def v64i8 : VTVec<64, i8, 48>; // 64 x i8 vector value +def v128i8 : VTVec<128, i8, 49>; // 128 x i8 vector value +def v256i8 : VTVec<256, i8, 50>; // 256 x i8 vector value +def v512i8 : VTVec<512, i8, 51>; // 512 x i8 vector value +def v1024i8 : VTVec<1024, i8, 52>; // 1024 x i8 vector value + +def v1i16 : VTVec<1, i16, 53>; // 1 x i16 vector value +def v2i16 : VTVec<2, i16, 54>; // 2 x i16 vector value +def v3i16 : VTVec<3, i16, 55>; // 3 x i16 vector value +def v4i16 : VTVec<4, i16, 56>; // 4 x i16 vector value +def v5i16 : VTVec<5, i16, 57>; // 5 x i16 vector value +def v6i16 : VTVec<6, i16, 58>; // 6 x i16 vector value +def v7i16 : VTVec<7, i16, 59>; // 7 x i16 vector value +def v8i16 : VTVec<8, i16, 60>; // 8 x i16 vector value +def v16i16 : VTVec<16, i16, 61>; // 16 x i16 vector value +def v32i16 : VTVec<32, i16, 62>; // 32 x i16 vector value +def v64i16 : VTVec<64, i16, 63>; // 64 x i16 vector value +def v128i16 : VTVec<128, i16, 64>; // 128 x i16 vector value +def v256i16 : VTVec<256, i16, 65>; // 256 x i16 vector value +def v512i16 : VTVec<512, i16, 66>; // 512 x i16 vector value +def v4096i16 : VTVec<4096, i16, 67>; // 4096 x i16 vector value + +def v1i32 : VTVec<1, i32, 68>; // 1 x i32 vector value +def v2i32 : VTVec<2, i32, 69>; // 2 x i32 vector value +def v3i32 : VTVec<3, i32, 70>; // 3 x i32 vector value +def v4i32 : VTVec<4, i32, 71>; // 4 x i32 vector value +def v5i32 : VTVec<5, i32, 72>; // 5 x i32 vector value +def v6i32 : VTVec<6, i32, 73>; // 6 x i32 vector value +def v7i32 : VTVec<7, i32, 74>; // 7 x i32 vector value +def v8i32 : VTVec<8, i32, 75>; // 8 x i32 vector value +def v9i32 : VTVec<9, i32, 76>; // 9 x i32 vector value +def v10i32 : VTVec<10, i32, 77>; // 10 x i32 vector value +def v11i32 : VTVec<11, i32, 78>; // 11 x i32 vector value +def v12i32 : VTVec<12, i32, 79>; // 12 x i32 vector value +def v16i32 : VTVec<16, i32, 80>; // 16 x i32 vector value +def v32i32 : VTVec<32, i32, 81>; // 32 x i32 vector value +def v64i32 : VTVec<64, i32, 82>; // 64 x i32 vector value +def v128i32 : VTVec<128, i32, 83>; // 128 x i32 vector value +def v256i32 : VTVec<256, i32, 84>; // 256 x i32 vector value +def v512i32 : VTVec<512, i32, 85>; // 512 x i32 vector value +def v1024i32 : VTVec<1024, i32, 86>; // 1024 x i32 vector value +def v2048i32 : VTVec<2048, i32, 87>; // 2048 x i32 vector value +def v4096i32 : VTVec<4096, i32, 88>; // 4096 x i32 vector value + +def v1i64 : VTVec<1, i64, 89>; // 1 x i64 vector value +def v2i64 : VTVec<2, i64, 90>; // 2 x i64 vector value +def v3i64 : VTVec<3, i64, 91>; // 3 x i64 vector value +def v4i64 : VTVec<4, i64, 92>; // 4 x i64 vector value +def v8i64 : VTVec<8, i64, 93>; // 8 x i64 vector value +def v16i64 : VTVec<16, i64, 94>; // 16 x i64 vector value +def v32i64 : VTVec<32, i64, 95>; // 32 x i64 vector value +def v64i64 : VTVec<64, i64, 96>; // 64 x i64 vector value +def v128i64 : VTVec<128, i64, 97>; // 128 x i64 vector value +def v256i64 : VTVec<256, i64, 98>; // 256 x i64 vector value + +def v1i128 : VTVec<1, i128, 99>; // 1 x i128 vector value + +def v1f16 : VTVec<1, f16, 100>; // 1 x f16 vector value +def v2f16 : VTVec<2, f16, 101>; // 2 x f16 vector value +def v3f16 : VTVec<3, f16, 102>; // 3 x f16 vector value +def v4f16 : VTVec<4, f16, 103>; // 4 x f16 vector value +def v5f16 : VTVec<5, f16, 104>; // 5 x f16 vector value +def v6f16 : VTVec<6, f16, 105>; // 6 x f16 vector value +def v7f16 : VTVec<7, f16, 106>; // 7 x f16 vector value +def v8f16 : VTVec<8, f16, 107>; // 8 x f16 vector value +def v16f16 : VTVec<16, f16, 108>; // 16 x f16 vector value +def v32f16 : VTVec<32, f16, 109>; // 32 x f16 vector value +def v64f16 : VTVec<64, f16, 110>; // 64 x f16 vector value +def v128f16 : VTVec<128, f16, 111>; // 128 x f16 vector value +def v256f16 : VTVec<256, f16, 112>; // 256 x f16 vector value +def v512f16 : VTVec<512, f16, 113>; // 512 x f16 vector value +def v4096f16 : VTVec<4096, f16, 114>; // 4096 x f16 vector value + +def v1bf16 : VTVec<1, bf16, 115>; // 1 x bf16 vector value +def v2bf16 : VTVec<2, bf16, 116>; // 2 x bf16 vector value +def v3bf16 : VTVec<3, bf16, 117>; // 3 x bf16 vector value +def v4bf16 : VTVec<4, bf16, 118>; // 4 x bf16 vector value +def v8bf16 : VTVec<8, bf16, 119>; // 8 x bf16 vector value +def v16bf16 : VTVec<16, bf16, 120>; // 16 x bf16 vector value +def v32bf16 : VTVec<32, bf16, 121>; // 32 x bf16 vector value +def v64bf16 : VTVec<64, bf16, 122>; // 64 x bf16 vector value +def v128bf16 : VTVec<128, bf16, 123>; // 128 x bf16 vector value +def v4096bf16 : VTVec<4096, bf16, 124>; // 4096 x bf16 vector value + +def v1f32 : VTVec<1, f32, 125>; // 1 x f32 vector value +def v2f32 : VTVec<2, f32, 126>; // 2 x f32 vector value +def v3f32 : VTVec<3, f32, 127>; // 3 x f32 vector value +def v4f32 : VTVec<4, f32, 128>; // 4 x f32 vector value +def v5f32 : VTVec<5, f32, 129>; // 5 x f32 vector value +def v6f32 : VTVec<6, f32, 130>; // 6 x f32 vector value +def v7f32 : VTVec<7, f32, 131>; // 7 x f32 vector value +def v8f32 : VTVec<8, f32, 132>; // 8 x f32 vector value +def v9f32 : VTVec<9, f32, 133>; // 9 x f32 vector value +def v10f32 : VTVec<10, f32, 134>; // 10 x f32 vector value +def v11f32 : VTVec<11, f32, 135>; // 11 x f32 vector value +def v12f32 : VTVec<12, f32, 136>; // 12 x f32 vector value +def v16f32 : VTVec<16, f32, 137>; // 16 x f32 vector value +def v32f32 : VTVec<32, f32, 138>; // 32 x f32 vector value +def v64f32 : VTVec<64, f32, 139>; // 64 x f32 vector value +def v128f32 : VTVec<128, f32, 140>; // 128 x f32 vector value +def v256f32 : VTVec<256, f32, 141>; // 256 x f32 vector value +def v512f32 : VTVec<512, f32, 142>; // 512 x f32 vector value +def v1024f32 : VTVec<1024, f32, 143>; // 1024 x f32 vector value +def v2048f32 : VTVec<2048, f32, 144>; // 2048 x f32 vector value + +def v1f64 : VTVec<1, f64, 145>; // 1 x f64 vector value +def v2f64 : VTVec<2, f64, 146>; // 2 x f64 vector value +def v3f64 : VTVec<3, f64, 147>; // 3 x f64 vector value +def v4f64 : VTVec<4, f64, 148>; // 4 x f64 vector value +def v8f64 : VTVec<8, f64, 149>; // 8 x f64 vector value +def v16f64 : VTVec<16, f64, 150>; // 16 x f64 vector value +def v32f64 : VTVec<32, f64, 151>; // 32 x f64 vector value +def v64f64 : VTVec<64, f64, 152>; // 64 x f64 vector value +def v128f64 : VTVec<128, f64, 153>; // 128 x f64 vector value +def v256f64 : VTVec<256, f64, 154>; // 256 x f64 vector value + +def nxv1i1 : VTScalableVec<1, i1, 155>; // n x 1 x i1 vector value +def nxv2i1 : VTScalableVec<2, i1, 156>; // n x 2 x i1 vector value +def nxv4i1 : VTScalableVec<4, i1, 157>; // n x 4 x i1 vector value +def nxv8i1 : VTScalableVec<8, i1, 158>; // n x 8 x i1 vector value +def nxv16i1 : VTScalableVec<16, i1, 159>; // n x 16 x i1 vector value +def nxv32i1 : VTScalableVec<32, i1, 160>; // n x 32 x i1 vector value +def nxv64i1 : VTScalableVec<64, i1, 161>; // n x 64 x i1 vector value + +def nxv1i8 : VTScalableVec<1, i8, 162>; // n x 1 x i8 vector value +def nxv2i8 : VTScalableVec<2, i8, 163>; // n x 2 x i8 vector value +def nxv4i8 : VTScalableVec<4, i8, 164>; // n x 4 x i8 vector value +def nxv8i8 : VTScalableVec<8, i8, 165>; // n x 8 x i8 vector value +def nxv16i8 : VTScalableVec<16, i8, 166>; // n x 16 x i8 vector value +def nxv32i8 : VTScalableVec<32, i8, 167>; // n x 32 x i8 vector value +def nxv64i8 : VTScalableVec<64, i8, 168>; // n x 64 x i8 vector value + +def nxv1i16 : VTScalableVec<1, i16, 169>; // n x 1 x i16 vector value +def nxv2i16 : VTScalableVec<2, i16, 170>; // n x 2 x i16 vector value +def nxv4i16 : VTScalableVec<4, i16, 171>; // n x 4 x i16 vector value +def nxv8i16 : VTScalableVec<8, i16, 172>; // n x 8 x i16 vector value +def nxv16i16 : VTScalableVec<16, i16, 173>; // n x 16 x i16 vector value +def nxv32i16 : VTScalableVec<32, i16, 174>; // n x 32 x i16 vector value + +def nxv1i32 : VTScalableVec<1, i32, 175>; // n x 1 x i32 vector value +def nxv2i32 : VTScalableVec<2, i32, 176>; // n x 2 x i32 vector value +def nxv4i32 : VTScalableVec<4, i32, 177>; // n x 4 x i32 vector value +def nxv8i32 : VTScalableVec<8, i32, 178>; // n x 8 x i32 vector value +def nxv16i32 : VTScalableVec<16, i32, 179>; // n x 16 x i32 vector value +def nxv32i32 : VTScalableVec<32, i32, 180>; // n x 32 x i32 vector value + +def nxv1i64 : VTScalableVec<1, i64, 181>; // n x 1 x i64 vector value +def nxv2i64 : VTScalableVec<2, i64, 182>; // n x 2 x i64 vector value +def nxv4i64 : VTScalableVec<4, i64, 183>; // n x 4 x i64 vector value +def nxv8i64 : VTScalableVec<8, i64, 184>; // n x 8 x i64 vector value +def nxv16i64 : VTScalableVec<16, i64, 185>; // n x 16 x i64 vector value +def nxv32i64 : VTScalableVec<32, i64, 186>; // n x 32 x i64 vector value + +def nxv1f16 : VTScalableVec<1, f16, 187>; // n x 1 x f16 vector value +def nxv2f16 : VTScalableVec<2, f16, 188>; // n x 2 x f16 vector value +def nxv4f16 : VTScalableVec<4, f16, 189>; // n x 4 x f16 vector value +def nxv8f16 : VTScalableVec<8, f16, 190>; // n x 8 x f16 vector value +def nxv16f16 : VTScalableVec<16, f16, 191>; // n x 16 x f16 vector value +def nxv32f16 : VTScalableVec<32, f16, 192>; // n x 32 x f16 vector value + +def nxv1bf16 : VTScalableVec<1, bf16, 193>; // n x 1 x bf16 vector value +def nxv2bf16 : VTScalableVec<2, bf16, 194>; // n x 2 x bf16 vector value +def nxv4bf16 : VTScalableVec<4, bf16, 195>; // n x 4 x bf16 vector value +def nxv8bf16 : VTScalableVec<8, bf16, 196>; // n x 8 x bf16 vector value +def nxv16bf16 : VTScalableVec<16, bf16, 197>; // n x 16 x bf16 vector value +def nxv32bf16 : VTScalableVec<32, bf16, 198>; // n x 32 x bf16 vector value + +def nxv1f32 : VTScalableVec<1, f32, 199>; // n x 1 x f32 vector value +def nxv2f32 : VTScalableVec<2, f32, 200>; // n x 2 x f32 vector value +def nxv4f32 : VTScalableVec<4, f32, 201>; // n x 4 x f32 vector value +def nxv8f32 : VTScalableVec<8, f32, 202>; // n x 8 x f32 vector value +def nxv16f32 : VTScalableVec<16, f32, 203>; // n x 16 x f32 vector value + +def nxv1f64 : VTScalableVec<1, f64, 204>; // n x 1 x f64 vector value +def nxv2f64 : VTScalableVec<2, f64, 205>; // n x 2 x f64 vector value +def nxv4f64 : VTScalableVec<4, f64, 206>; // n x 4 x f64 vector value +def nxv8f64 : VTScalableVec<8, f64, 207>; // n x 8 x f64 vector value // Sz = NF * MinNumElts * 8(bits) -def riscv_nxv1i8x2 : VTVecTup<16, 2, i8, 196>; // RISCV vector tuple(min_num_elts=1, nf=2) -def riscv_nxv1i8x3 : VTVecTup<24, 3, i8, 197>; // RISCV vector tuple(min_num_elts=1, nf=3) -def riscv_nxv1i8x4 : VTVecTup<32, 4, i8, 198>; // RISCV vector tuple(min_num_elts=1, nf=4) -def riscv_nxv1i8x5 : VTVecTup<40, 5, i8, 199>; // RISCV vector tuple(min_num_elts=1, nf=5) -def riscv_nxv1i8x6 : VTVecTup<48, 6, i8, 200>; // RISCV vector tuple(min_num_elts=1, nf=6) -def riscv_nxv1i8x7 : VTVecTup<56, 7, i8, 201>; // RISCV vector tuple(min_num_elts=1, nf=7) -def riscv_nxv1i8x8 : VTVecTup<64, 8, i8, 202>; // RISCV vector tuple(min_num_elts=1, nf=8) -def riscv_nxv2i8x2 : VTVecTup<32, 2, i8, 203>; // RISCV vector tuple(min_num_elts=2, nf=2) -def riscv_nxv2i8x3 : VTVecTup<48, 3, i8, 204>; // RISCV vector tuple(min_num_elts=2, nf=3) -def riscv_nxv2i8x4 : VTVecTup<64, 4, i8, 205>; // RISCV vector tuple(min_num_elts=2, nf=4) -def riscv_nxv2i8x5 : VTVecTup<80, 5, i8, 206>; // RISCV vector tuple(min_num_elts=2, nf=5) -def riscv_nxv2i8x6 : VTVecTup<96, 6, i8, 207>; // RISCV vector tuple(min_num_elts=2, nf=6) -def riscv_nxv2i8x7 : VTVecTup<112, 7, i8, 208>; // RISCV vector tuple(min_num_elts=2, nf=7) -def riscv_nxv2i8x8 : VTVecTup<128, 8, i8, 209>; // RISCV vector tuple(min_num_elts=2, nf=8) -def riscv_nxv4i8x2 : VTVecTup<64, 2, i8, 210>; // RISCV vector tuple(min_num_elts=4, nf=2) -def riscv_nxv4i8x3 : VTVecTup<96, 3, i8, 211>; // RISCV vector tuple(min_num_elts=4, nf=3) -def riscv_nxv4i8x4 : VTVecTup<128, 4, i8, 212>; // RISCV vector tuple(min_num_elts=4, nf=4) -def riscv_nxv4i8x5 : VTVecTup<160, 5, i8, 213>; // RISCV vector tuple(min_num_elts=4, nf=5) -def riscv_nxv4i8x6 : VTVecTup<192, 6, i8, 214>; // RISCV vector tuple(min_num_elts=4, nf=6) -def riscv_nxv4i8x7 : VTVecTup<224, 7, i8, 215>; // RISCV vector tuple(min_num_elts=4, nf=7) -def riscv_nxv4i8x8 : VTVecTup<256, 8, i8, 216>; // RISCV vector tuple(min_num_elts=4, nf=8) -def riscv_nxv8i8x2 : VTVecTup<128, 2, i8, 217>; // RISCV vector tuple(min_num_elts=8, nf=2) -def riscv_nxv8i8x3 : VTVecTup<192, 3, i8, 218>; // RISCV vector tuple(min_num_elts=8, nf=3) -def riscv_nxv8i8x4 : VTVecTup<256, 4, i8, 219>; // RISCV vector tuple(min_num_elts=8, nf=4) -def riscv_nxv8i8x5 : VTVecTup<320, 5, i8, 220>; // RISCV vector tuple(min_num_elts=8, nf=5) -def riscv_nxv8i8x6 : VTVecTup<384, 6, i8, 221>; // RISCV vector tuple(min_num_elts=8, nf=6) -def riscv_nxv8i8x7 : VTVecTup<448, 7, i8, 222>; // RISCV vector tuple(min_num_elts=8, nf=7) -def riscv_nxv8i8x8 : VTVecTup<512, 8, i8, 223>; // RISCV vector tuple(min_num_elts=8, nf=8) -def riscv_nxv16i8x2 : VTVecTup<256, 2, i8, 224>; // RISCV vector tuple(min_num_elts=16, nf=2) -def riscv_nxv16i8x3 : VTVecTup<384, 3, i8, 225>; // RISCV vector tuple(min_num_elts=16, nf=3) -def riscv_nxv16i8x4 : VTVecTup<512, 4, i8, 226>; // RISCV vector tuple(min_num_elts=16, nf=4) -def riscv_nxv32i8x2 : VTVecTup<512, 2, i8, 227>; // RISCV vector tuple(min_num_elts=32, nf=2) - -def x86mmx : ValueType<64, 228>; // X86 MMX value -def Glue : ValueType<0, 229>; // Pre-RA sched glue -def isVoid : ValueType<0, 230>; // Produces no value -def untyped : ValueType<8, 231> { // Produces an untyped value +def riscv_nxv1i8x2 : VTVecTup<16, 2, i8, 208>; // RISCV vector tuple(min_num_elts=1, nf=2) +def riscv_nxv1i8x3 : VTVecTup<24, 3, i8, 209>; // RISCV vector tuple(min_num_elts=1, nf=3) +def riscv_nxv1i8x4 : VTVecTup<32, 4, i8, 210>; // RISCV vector tuple(min_num_elts=1, nf=4) +def riscv_nxv1i8x5 : VTVecTup<40, 5, i8, 211>; // RISCV vector tuple(min_num_elts=1, nf=5) +def riscv_nxv1i8x6 : VTVecTup<48, 6, i8, 212>; // RISCV vector tuple(min_num_elts=1, nf=6) +def riscv_nxv1i8x7 : VTVecTup<56, 7, i8, 213>; // RISCV vector tuple(min_num_elts=1, nf=7) +def riscv_nxv1i8x8 : VTVecTup<64, 8, i8, 214>; // RISCV vector tuple(min_num_elts=1, nf=8) +def riscv_nxv2i8x2 : VTVecTup<32, 2, i8, 215>; // RISCV vector tuple(min_num_elts=2, nf=2) +def riscv_nxv2i8x3 : VTVecTup<48, 3, i8, 216>; // RISCV vector tuple(min_num_elts=2, nf=3) +def riscv_nxv2i8x4 : VTVecTup<64, 4, i8, 217>; // RISCV vector tuple(min_num_elts=2, nf=4) +def riscv_nxv2i8x5 : VTVecTup<80, 5, i8, 218>; // RISCV vector tuple(min_num_elts=2, nf=5) +def riscv_nxv2i8x6 : VTVecTup<96, 6, i8, 219>; // RISCV vector tuple(min_num_elts=2, nf=6) +def riscv_nxv2i8x7 : VTVecTup<112, 7, i8, 220>; // RISCV vector tuple(min_num_elts=2, nf=7) +def riscv_nxv2i8x8 : VTVecTup<128, 8, i8, 221>; // RISCV vector tuple(min_num_elts=2, nf=8) +def riscv_nxv4i8x2 : VTVecTup<64, 2, i8, 222>; // RISCV vector tuple(min_num_elts=4, nf=2) +def riscv_nxv4i8x3 : VTVecTup<96, 3, i8, 223>; // RISCV vector tuple(min_num_elts=4, nf=3) +def riscv_nxv4i8x4 : VTVecTup<128, 4, i8, 224>; // RISCV vector tuple(min_num_elts=4, nf=4) +def riscv_nxv4i8x5 : VTVecTup<160, 5, i8, 225>; // RISCV vector tuple(min_num_elts=4, nf=5) +def riscv_nxv4i8x6 : VTVecTup<192, 6, i8, 226>; // RISCV vector tuple(min_num_elts=4, nf=6) +def riscv_nxv4i8x7 : VTVecTup<224, 7, i8, 227>; // RISCV vector tuple(min_num_elts=4, nf=7) +def riscv_nxv4i8x8 : VTVecTup<256, 8, i8, 228>; // RISCV vector tuple(min_num_elts=4, nf=8) +def riscv_nxv8i8x2 : VTVecTup<128, 2, i8, 229>; // RISCV vector tuple(min_num_elts=8, nf=2) +def riscv_nxv8i8x3 : VTVecTup<192, 3, i8, 230>; // RISCV vector tuple(min_num_elts=8, nf=3) +def riscv_nxv8i8x4 : VTVecTup<256, 4, i8, 231>; // RISCV vector tuple(min_num_elts=8, nf=4) +def riscv_nxv8i8x5 : VTVecTup<320, 5, i8, 232>; // RISCV vector tuple(min_num_elts=8, nf=5) +def riscv_nxv8i8x6 : VTVecTup<384, 6, i8, 233>; // RISCV vector tuple(min_num_elts=8, nf=6) +def riscv_nxv8i8x7 : VTVecTup<448, 7, i8, 234>; // RISCV vector tuple(min_num_elts=8, nf=7) +def riscv_nxv8i8x8 : VTVecTup<512, 8, i8, 235>; // RISCV vector tuple(min_num_elts=8, nf=8) +def riscv_nxv16i8x2 : VTVecTup<256, 2, i8, 236>; // RISCV vector tuple(min_num_elts=16, nf=2) +def riscv_nxv16i8x3 : VTVecTup<384, 3, i8, 237>; // RISCV vector tuple(min_num_elts=16, nf=3) +def riscv_nxv16i8x4 : VTVecTup<512, 4, i8, 238>; // RISCV vector tuple(min_num_elts=16, nf=4) +def riscv_nxv32i8x2 : VTVecTup<512, 2, i8, 239>; // RISCV vector tuple(min_num_elts=32, nf=2) + +def x86mmx : ValueType<64, 240>; // X86 MMX value +def Glue : ValueType<0, 241>; // Pre-RA sched glue +def isVoid : ValueType<0, 242>; // Produces no value +def untyped : ValueType<8, 243> { // Produces an untyped value let LLVMName = "Untyped"; } -def funcref : ValueType<0, 232>; // WebAssembly's funcref type -def externref : ValueType<0, 233>; // WebAssembly's externref type -def exnref : ValueType<0, 234>; // WebAssembly's exnref type -def x86amx : ValueType<8192, 235>; // X86 AMX value -def i64x8 : ValueType<512, 236>; // 8 Consecutive GPRs (AArch64) +def funcref : ValueType<0, 244>; // WebAssembly's funcref type +def externref : ValueType<0, 245>; // WebAssembly's externref type +def exnref : ValueType<0, 246>; // WebAssembly's exnref type +def x86amx : ValueType<8192, 247>; // X86 AMX value +def i64x8 : ValueType<512, 248>; // 8 Consecutive GPRs (AArch64) def aarch64svcount - : ValueType<16, 237>; // AArch64 predicate-as-counter -def spirvbuiltin : ValueType<0, 238>; // SPIR-V's builtin type + : ValueType<16, 249>; // AArch64 predicate-as-counter +def spirvbuiltin : ValueType<0, 250>; // SPIR-V's builtin type // AMDGPU buffer fat pointer, buffer rsrc + offset, rewritten before MIR translation. // FIXME: Remove this and the getPointerType() override if MVT::i160 is added. -def amdgpuBufferFatPointer : ValueType<160, 239>; +def amdgpuBufferFatPointer : ValueType<160, 251>; // AMDGPU buffer strided pointer, buffer rsrc + index + offset, doesn't reach MIR. // FIXME: Remove this and the getPointerType() override if MVT::i82 is added. -def amdgpuBufferStridedPointer : ValueType<192, 240>; +def amdgpuBufferStridedPointer : ValueType<192, 252>; -def aarch64mfp8 : ValueType<8, 241>; // 8-bit value in FPR (AArch64) +def aarch64mfp8 : ValueType<8, 253>; // 8-bit value in FPR (AArch64) let isNormalValueType = false in { def token : ValueType<0, 504>; // TokenTy diff --git a/llvm/include/llvm/Frontend/Offloading/PropertySet.h b/llvm/include/llvm/Frontend/Offloading/PropertySet.h new file mode 100644 index 0000000..d198d3e --- /dev/null +++ b/llvm/include/llvm/Frontend/Offloading/PropertySet.h @@ -0,0 +1,33 @@ +///===- llvm/Frontend/Offloading/PropertySet.h ----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +///===---------------------------------------------------------------------===// +/// \file This file defines PropertySetRegistry and PropertyValue types and +/// provides helper functions to translate PropertySetRegistry from/to JSON. +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/SmallVector.h" +#include "llvm/Support/Error.h" + +#include <map> +#include <variant> + +namespace llvm { +class raw_ostream; +class MemoryBufferRef; + +namespace offloading { + +using ByteArray = SmallVector<unsigned char, 0>; +using PropertyValue = std::variant<uint32_t, ByteArray>; +using PropertySet = std::map<std::string, PropertyValue>; +using PropertySetRegistry = std::map<std::string, PropertySet>; + +void writePropertiesToJSON(const PropertySetRegistry &P, raw_ostream &O); +Expected<PropertySetRegistry> readPropertiesFromJSON(MemoryBufferRef Buf); + +} // namespace offloading +} // namespace llvm diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index eabdf52..469bdb4 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -655,6 +655,12 @@ def int_amdgcn_cvt_scale_pk8_bf16_fp4 : AMDGPUCvtScaleIntrinsic<llvm_v8bf16_ty, def int_amdgcn_cvt_scale_pk8_f32_fp8 : AMDGPUCvtScaleIntrinsic<llvm_v8f32_ty, llvm_v2i32_ty, "cvt_scale_pk8_f32_fp8">; def int_amdgcn_cvt_scale_pk8_f32_bf8 : AMDGPUCvtScaleIntrinsic<llvm_v8f32_ty, llvm_v2i32_ty, "cvt_scale_pk8_f32_bf8">; def int_amdgcn_cvt_scale_pk8_f32_fp4 : AMDGPUCvtScaleIntrinsic<llvm_v8f32_ty, llvm_i32_ty, "cvt_scale_pk8_f32_fp4">; +def int_amdgcn_cvt_scale_pk16_f16_bf6 : AMDGPUCvtScaleIntrinsic<llvm_v16f16_ty, llvm_v3i32_ty, "cvt_scale_pk16_f16_bf6">; +def int_amdgcn_cvt_scale_pk16_bf16_bf6 : AMDGPUCvtScaleIntrinsic<llvm_v16bf16_ty, llvm_v3i32_ty, "cvt_scale_pk16_bf16_bf6">; +def int_amdgcn_cvt_scale_pk16_f16_fp6 : AMDGPUCvtScaleIntrinsic<llvm_v16f16_ty, llvm_v3i32_ty, "cvt_scale_pk16_f16_fp6">; +def int_amdgcn_cvt_scale_pk16_bf16_fp6 : AMDGPUCvtScaleIntrinsic<llvm_v16bf16_ty, llvm_v3i32_ty, "cvt_scale_pk16_bf16_fp6">; +def int_amdgcn_cvt_scale_pk16_f32_fp6 : AMDGPUCvtScaleIntrinsic<llvm_v16f32_ty, llvm_v3i32_ty, "cvt_scale_pk16_f32_fp6">; +def int_amdgcn_cvt_scale_pk16_f32_bf6 : AMDGPUCvtScaleIntrinsic<llvm_v16f32_ty, llvm_v3i32_ty, "cvt_scale_pk16_f32_bf6">; class AMDGPUCvtScaleF32ToFP6BF6Intrinsic<LLVMType DstTy, LLVMType Src0Ty, LLVMType Src1Ty, string name> : DefaultAttrsIntrinsic< [DstTy], [Src0Ty, Src1Ty, llvm_float_ty], [IntrNoMem, IntrSpeculatable] @@ -662,18 +668,49 @@ class AMDGPUCvtScaleF32ToFP6BF6Intrinsic<LLVMType DstTy, LLVMType Src0Ty, LLVMTy def int_amdgcn_cvt_scalef32_pk32_fp6_f16 : AMDGPUCvtScaleF32Intrinsic<llvm_v6i32_ty, llvm_v32f16_ty, "cvt_scalef32_pk32_fp6_f16">; def int_amdgcn_cvt_scalef32_pk32_bf6_f16 : AMDGPUCvtScaleF32Intrinsic<llvm_v6i32_ty, llvm_v32f16_ty, "cvt_scalef32_pk32_bf6_f16">; +def int_amdgcn_cvt_scalef32_pk8_fp8_bf16 : AMDGPUCvtScaleF32Intrinsic<llvm_v2i32_ty, llvm_v8bf16_ty, "cvt_scalef32_pk8_fp8_bf16">; +def int_amdgcn_cvt_scalef32_pk8_bf8_bf16 : AMDGPUCvtScaleF32Intrinsic<llvm_v2i32_ty, llvm_v8bf16_ty, "cvt_scalef32_pk8_bf8_bf16">; def int_amdgcn_cvt_scalef32_pk32_fp6_bf16 : AMDGPUCvtScaleF32Intrinsic<llvm_v6i32_ty, llvm_v32bf16_ty, "cvt_scalef32_pk32_fp6_bf16">; def int_amdgcn_cvt_scalef32_pk32_bf6_bf16 : AMDGPUCvtScaleF32Intrinsic<llvm_v6i32_ty, llvm_v32bf16_ty, "cvt_scalef32_pk32_bf6_bf16">; +def int_amdgcn_cvt_scalef32_pk8_fp8_f16 : AMDGPUCvtScaleF32Intrinsic<llvm_v2i32_ty, llvm_v8f16_ty, "cvt_scalef32_pk8_fp8_f16">; +def int_amdgcn_cvt_scalef32_pk8_bf8_f16 : AMDGPUCvtScaleF32Intrinsic<llvm_v2i32_ty, llvm_v8f16_ty, "cvt_scalef32_pk8_bf8_f16">; +def int_amdgcn_cvt_scalef32_pk8_fp8_f32 : AMDGPUCvtScaleF32Intrinsic<llvm_v2i32_ty, llvm_v8f32_ty, "cvt_scalef32_pk8_fp8_f32">; +def int_amdgcn_cvt_scalef32_pk8_bf8_f32 : AMDGPUCvtScaleF32Intrinsic<llvm_v2i32_ty, llvm_v8f32_ty, "cvt_scalef32_pk8_bf8_f32">; +def int_amdgcn_cvt_scalef32_pk8_fp4_f32 : AMDGPUCvtScaleF32Intrinsic<llvm_i32_ty, llvm_v8f32_ty, "cvt_scalef32_pk8_fp4_f32">; +def int_amdgcn_cvt_scalef32_pk8_fp4_f16 : AMDGPUCvtScaleF32Intrinsic<llvm_i32_ty, llvm_v8f16_ty, "cvt_scalef32_pk8_fp4_f16">; +def int_amdgcn_cvt_scalef32_pk8_fp4_bf16 : AMDGPUCvtScaleF32Intrinsic<llvm_i32_ty, llvm_v8bf16_ty, "cvt_scalef32_pk8_fp4_bf16">; +def int_amdgcn_cvt_scalef32_pk16_fp6_f32 : AMDGPUCvtScaleF32Intrinsic<llvm_v3i32_ty, llvm_v16f32_ty, "cvt_scalef32_pk16_fp6_f32">; +def int_amdgcn_cvt_scalef32_pk16_bf6_f32 : AMDGPUCvtScaleF32Intrinsic<llvm_v3i32_ty, llvm_v16f32_ty, "cvt_scalef32_pk16_bf6_f32">; +def int_amdgcn_cvt_scalef32_pk16_fp6_f16 : AMDGPUCvtScaleF32Intrinsic<llvm_v3i32_ty, llvm_v16f16_ty, "cvt_scalef32_pk16_fp6_f16">; +def int_amdgcn_cvt_scalef32_pk16_bf6_f16 : AMDGPUCvtScaleF32Intrinsic<llvm_v3i32_ty, llvm_v16f16_ty, "cvt_scalef32_pk16_bf6_f16">; +def int_amdgcn_cvt_scalef32_pk16_fp6_bf16 : AMDGPUCvtScaleF32Intrinsic<llvm_v3i32_ty, llvm_v16bf16_ty, "cvt_scalef32_pk16_fp6_bf16">; +def int_amdgcn_cvt_scalef32_pk16_bf6_bf16 : AMDGPUCvtScaleF32Intrinsic<llvm_v3i32_ty, llvm_v16bf16_ty, "cvt_scalef32_pk16_bf6_bf16">; + +def int_amdgcn_cvt_scalef32_sr_pk32_fp6_f32 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32f32_ty, "cvt_scalef32_sr_pk32_fp6_f32">; +def int_amdgcn_cvt_scalef32_sr_pk32_bf6_f32 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32f32_ty, "cvt_scalef32_sr_pk32_bf6_f32">; +def int_amdgcn_cvt_scalef32_sr_pk32_fp6_f16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32f16_ty, "cvt_scalef32_sr_pk32_fp6_f16">; +def int_amdgcn_cvt_scalef32_sr_pk32_bf6_f16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32f16_ty, "cvt_scalef32_sr_pk32_bf6_f16">; +def int_amdgcn_cvt_scalef32_sr_pk32_fp6_bf16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32bf16_ty, "cvt_scalef32_sr_pk32_fp6_bf16">; +def int_amdgcn_cvt_scalef32_sr_pk32_bf6_bf16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32bf16_ty, "cvt_scalef32_sr_pk32_bf6_bf16">; +def int_amdgcn_cvt_scalef32_sr_pk8_fp8_bf16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v2i32_ty, llvm_v8bf16_ty, "cvt_scalef32_sr_pk8_fp8_bf16">; +def int_amdgcn_cvt_scalef32_sr_pk8_bf8_bf16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v2i32_ty, llvm_v8bf16_ty, "cvt_scalef32_sr_pk8_bf8_bf16">; +def int_amdgcn_cvt_scalef32_sr_pk8_fp8_f16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v2i32_ty, llvm_v8f16_ty, "cvt_scalef32_sr_pk8_fp8_f16">; +def int_amdgcn_cvt_scalef32_sr_pk8_bf8_f16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v2i32_ty, llvm_v8f16_ty, "cvt_scalef32_sr_pk8_bf8_f16">; +def int_amdgcn_cvt_scalef32_sr_pk8_fp8_f32 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v2i32_ty, llvm_v8f32_ty, "cvt_scalef32_sr_pk8_fp8_f32">; +def int_amdgcn_cvt_scalef32_sr_pk8_bf8_f32 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v2i32_ty, llvm_v8f32_ty, "cvt_scalef32_sr_pk8_bf8_f32">; +def int_amdgcn_cvt_scalef32_sr_pk8_fp4_f32 : AMDGPUCvtScaleF32SRIntrinsic<llvm_i32_ty, llvm_v8f32_ty, "cvt_scalef32_sr_pk8_fp4_f32">; +def int_amdgcn_cvt_scalef32_sr_pk8_fp4_f16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_i32_ty, llvm_v8f16_ty, "cvt_scalef32_sr_pk8_fp4_f16">; +def int_amdgcn_cvt_scalef32_sr_pk8_fp4_bf16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_i32_ty, llvm_v8bf16_ty, "cvt_scalef32_sr_pk8_fp4_bf16">; +def int_amdgcn_cvt_scalef32_sr_pk16_fp6_f32 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v3i32_ty, llvm_v16f32_ty, "cvt_scalef32_sr_pk16_fp6_f32">; +def int_amdgcn_cvt_scalef32_sr_pk16_bf6_f32 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v3i32_ty, llvm_v16f32_ty, "cvt_scalef32_sr_pk16_bf6_f32">; +def int_amdgcn_cvt_scalef32_sr_pk16_fp6_f16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v3i32_ty, llvm_v16f16_ty, "cvt_scalef32_sr_pk16_fp6_f16">; +def int_amdgcn_cvt_scalef32_sr_pk16_bf6_f16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v3i32_ty, llvm_v16f16_ty, "cvt_scalef32_sr_pk16_bf6_f16">; +def int_amdgcn_cvt_scalef32_sr_pk16_fp6_bf16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v3i32_ty, llvm_v16bf16_ty, "cvt_scalef32_sr_pk16_fp6_bf16">; +def int_amdgcn_cvt_scalef32_sr_pk16_bf6_bf16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v3i32_ty, llvm_v16bf16_ty, "cvt_scalef32_sr_pk16_bf6_bf16">; + def int_amdgcn_cvt_scalef32_2xpk16_fp6_f32 : AMDGPUCvtScaleF32ToFP6BF6Intrinsic<llvm_v6i32_ty, llvm_v16f32_ty, llvm_v16f32_ty, "cvt_scalef32_2xpk16_fp6_f32">; def int_amdgcn_cvt_scalef32_2xpk16_bf6_f32 : AMDGPUCvtScaleF32ToFP6BF6Intrinsic<llvm_v6i32_ty, llvm_v16f32_ty, llvm_v16f32_ty, "cvt_scalef32_2xpk16_bf6_f32">; -def int_amdgcn_cvt_scalef32_sr_pk32_bf6_bf16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32bf16_ty, "cvt_scalef32_sr_pk32_bf6_bf16">; -def int_amdgcn_cvt_scalef32_sr_pk32_bf6_f16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32f16_ty, "cvt_scalef32_sr_pk32_bf6_f16">; -def int_amdgcn_cvt_scalef32_sr_pk32_bf6_f32 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32f32_ty, "cvt_scalef32_sr_pk32_bf6_f32">; -def int_amdgcn_cvt_scalef32_sr_pk32_fp6_bf16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32bf16_ty, "cvt_scalef32_sr_pk32_fp6_bf16">; -def int_amdgcn_cvt_scalef32_sr_pk32_fp6_f16 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32f16_ty, "cvt_scalef32_sr_pk32_fp6_f16">; -def int_amdgcn_cvt_scalef32_sr_pk32_fp6_f32 : AMDGPUCvtScaleF32SRIntrinsic<llvm_v6i32_ty, llvm_v32f32_ty, "cvt_scalef32_sr_pk32_fp6_f32">; - class AMDGPUCvtScaleFP4FP8BF8ToF1632Intrinsic<LLVMType DstTy, string name> : DefaultAttrsIntrinsic< [DstTy], [llvm_i32_ty, // src @@ -3686,6 +3723,18 @@ def int_amdgcn_permlane_idx_gen : ClangBuiltin<"__builtin_amdgcn_permlane_idx_ge [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree]>; +def int_amdgcn_perm_pk16_b4_u4 : ClangBuiltin<"__builtin_amdgcn_perm_pk16_b4_u4">, + DefaultAttrsIntrinsic<[llvm_v2i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], + [IntrNoMem, IntrSpeculatable]>; + +def int_amdgcn_perm_pk16_b6_u4 : ClangBuiltin<"__builtin_amdgcn_perm_pk16_b6_u4">, + DefaultAttrsIntrinsic<[llvm_v3i32_ty], [llvm_i32_ty, llvm_i64_ty, llvm_v2i32_ty], + [IntrNoMem, IntrSpeculatable]>; + +def int_amdgcn_perm_pk16_b8_u4 : ClangBuiltin<"__builtin_amdgcn_perm_pk16_b8_u4">, + DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_i64_ty, llvm_v2i32_ty], + [IntrNoMem, IntrSpeculatable]>; + //===----------------------------------------------------------------------===// // Special Intrinsics for backend internal use only. No frontend // should emit calls to these. diff --git a/llvm/include/llvm/MC/MCAsmBackend.h b/llvm/include/llvm/MC/MCAsmBackend.h index bfc1175..311d9ca 100644 --- a/llvm/include/llvm/MC/MCAsmBackend.h +++ b/llvm/include/llvm/MC/MCAsmBackend.h @@ -117,14 +117,13 @@ public: void maybeAddReloc(const MCFragment &, const MCFixup &, const MCValue &, uint64_t &Value, bool IsResolved); - /// Determine if a relocation is required. In addition, - /// Apply the \p Value for given \p Fixup into the provided data fragment, at - /// the offset specified by the fixup and following the fixup kind as - /// appropriate. Errors (such as an out of range fixup value) should be - /// reported via \p Ctx. + // Determine if a relocation is required. In addition, apply `Value` to the + // `Data` fragment at the specified fixup offset if applicable. `Data` points + // to the first byte of the fixup offset, which may be at the content's end if + // the fixup is zero-sized. virtual void applyFixup(const MCFragment &, const MCFixup &, - const MCValue &Target, MutableArrayRef<char> Data, - uint64_t Value, bool IsResolved) = 0; + const MCValue &Target, uint8_t *Data, uint64_t Value, + bool IsResolved) = 0; /// @} diff --git a/llvm/include/llvm/MC/MCAssembler.h b/llvm/include/llvm/MC/MCAssembler.h index 4853701..ffde5ca2 100644 --- a/llvm/include/llvm/MC/MCAssembler.h +++ b/llvm/include/llvm/MC/MCAssembler.h @@ -99,8 +99,7 @@ private: /// \param RecordReloc Record relocation if needed. /// relocation. bool evaluateFixup(const MCFragment &F, MCFixup &Fixup, MCValue &Target, - uint64_t &Value, bool RecordReloc, - MutableArrayRef<char> Contents) const; + uint64_t &Value, bool RecordReloc, uint8_t *Data) const; /// Check whether a fixup can be satisfied, or whether it needs to be relaxed /// (increased in size, in order to hold its value correctly). diff --git a/llvm/include/llvm/MC/MCObjectStreamer.h b/llvm/include/llvm/MC/MCObjectStreamer.h index 4b43a8f..eb875a7 100644 --- a/llvm/include/llvm/MC/MCObjectStreamer.h +++ b/llvm/include/llvm/MC/MCObjectStreamer.h @@ -52,6 +52,10 @@ class MCObjectStreamer : public MCStreamer { DenseMap<const MCSymbol *, SmallVector<PendingAssignment, 1>> pendingAssignments; + SmallVector<std::unique_ptr<uint8_t[]>, 0> FragStorage; + // Available bytes in the current block for trailing data or new fragments. + size_t FragSpace = 0; + void emitInstToData(const MCInst &Inst, const MCSubtargetInfo &); void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; void emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; @@ -84,11 +88,18 @@ public: // Add a fragment with a variable-size tail and start a new empty fragment. void insert(MCFragment *F); + uint8_t *getCurFragEnd() const { + return reinterpret_cast<uint8_t *>(CurFrag + 1) + CurFrag->getFixedSize(); + } + MCFragment *allocFragSpace(size_t Headroom); // Add a new fragment to the current section without a variable-size tail. void newFragment(); + void ensureHeadroom(size_t Headroom); void appendContents(ArrayRef<char> Contents); - void appendContents(size_t Num, char Elt); + void appendContents(size_t Num, uint8_t Elt); + // Add a fixup to the current fragment. Call ensureHeadroom beforehand to + // ensure the fixup and appended content apply to the same fragment. void addFixup(const MCExpr *Value, MCFixupKind Kind); void emitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override; diff --git a/llvm/include/llvm/MC/MCSection.h b/llvm/include/llvm/MC/MCSection.h index df8f617b..4022ea7 100644 --- a/llvm/include/llvm/MC/MCSection.h +++ b/llvm/include/llvm/MC/MCSection.h @@ -80,21 +80,23 @@ private: FragmentType Kind; -protected: + //== Used by certain fragment types for better packing. + + // The number of fixups for the optional variable-size tail must be small. + uint8_t VarFixupSize = 0; + bool LinkerRelaxable : 1; - /// Used by certain fragment types for better packing. - /// /// FT_Data, FT_Relaxable bool HasInstructions : 1; /// FT_Relaxable, x86-specific bool AllowAutoPadding : 1; // Track content and fixups for the fixed-size part as fragments are - // appended to the section. The content remains immutable, except when - // modified by applyFixup. - uint32_t ContentStart = 0; - uint32_t ContentEnd = 0; + // appended to the section. The content is stored as trailing data of the + // MCFragment. The content remains immutable, except when modified by + // applyFixup. + uint32_t FixedSize = 0; uint32_t FixupStart = 0; uint32_t FixupEnd = 0; @@ -103,7 +105,6 @@ protected: uint32_t VarContentStart = 0; uint32_t VarContentEnd = 0; uint32_t VarFixupStart = 0; - uint32_t VarFixupEnd = 0; const MCSubtargetInfo *STI = nullptr; @@ -188,18 +189,6 @@ public: //== Content-related functions manage parent's storage using ContentStart and // ContentSize. - // Get a SmallVector reference. The caller should call doneAppending to update - // `ContentEnd`. - SmallVectorImpl<char> &getContentsForAppending(); - void doneAppending(); - void appendContents(ArrayRef<char> Contents) { - getContentsForAppending().append(Contents.begin(), Contents.end()); - doneAppending(); - } - void appendContents(size_t Num, char Elt) { - getContentsForAppending().append(Num, Elt); - doneAppending(); - } MutableArrayRef<char> getContents(); ArrayRef<char> getContents() const; @@ -208,10 +197,10 @@ public: MutableArrayRef<char> getVarContents(); ArrayRef<char> getVarContents() const; - size_t getFixedSize() const { return ContentEnd - ContentStart; } + size_t getFixedSize() const { return FixedSize; } size_t getVarSize() const { return VarContentEnd - VarContentStart; } size_t getSize() const { - return ContentEnd - ContentStart + (VarContentEnd - VarContentStart); + return FixedSize + (VarContentEnd - VarContentStart); } //== Fixup-related functions manage parent's storage using FixupStart and @@ -309,13 +298,8 @@ public: } }; -/// Interface implemented by fragments that contain encoded instructions and/or -/// data. -class MCEncodedFragment : public MCFragment { -protected: - MCEncodedFragment(MCFragment::FragmentType FType, bool HasInstructions) - : MCFragment(FType, HasInstructions) {} -}; +// MCFragment subclasses do not use the fixed-size part or variable-size tail of +// MCFragment. Instead, they encode content in a specialized way. class MCFillFragment : public MCFragment { uint8_t ValueSize; @@ -331,7 +315,7 @@ class MCFillFragment : public MCFragment { public: MCFillFragment(uint64_t Value, uint8_t VSize, const MCExpr &NumValues, SMLoc Loc) - : MCFragment(FT_Fill, false), ValueSize(VSize), Value(Value), + : MCFragment(FT_Fill), ValueSize(VSize), Value(Value), NumValues(NumValues), Loc(Loc) {} uint64_t getValue() const { return Value; } @@ -362,7 +346,7 @@ class MCNopsFragment : public MCFragment { public: MCNopsFragment(int64_t NumBytes, int64_t ControlledNopLength, SMLoc L, const MCSubtargetInfo &STI) - : MCFragment(FT_Nops, false), Size(NumBytes), + : MCFragment(FT_Nops), Size(NumBytes), ControlledNopLength(ControlledNopLength), Loc(L), STI(STI) {} int64_t getNumBytes() const { return Size; } @@ -389,7 +373,7 @@ class MCOrgFragment : public MCFragment { public: MCOrgFragment(const MCExpr &Offset, int8_t Value, SMLoc Loc) - : MCFragment(FT_Org, false), Value(Value), Offset(&Offset), Loc(Loc) {} + : MCFragment(FT_Org), Value(Value), Offset(&Offset), Loc(Loc) {} const MCExpr &getOffset() const { return *Offset; } @@ -407,8 +391,7 @@ class MCSymbolIdFragment : public MCFragment { const MCSymbol *Sym; public: - MCSymbolIdFragment(const MCSymbol *Sym) - : MCFragment(FT_SymbolId, false), Sym(Sym) {} + MCSymbolIdFragment(const MCSymbol *Sym) : MCFragment(FT_SymbolId), Sym(Sym) {} const MCSymbol *getSymbol() { return Sym; } const MCSymbol *getSymbol() const { return Sym; } @@ -420,7 +403,7 @@ public: /// Fragment representing the binary annotations produced by the /// .cv_inline_linetable directive. -class MCCVInlineLineTableFragment : public MCEncodedFragment { +class MCCVInlineLineTableFragment : public MCFragment { unsigned SiteFuncId; unsigned StartFileId; unsigned StartLineNum; @@ -435,7 +418,7 @@ public: MCCVInlineLineTableFragment(unsigned SiteFuncId, unsigned StartFileId, unsigned StartLineNum, const MCSymbol *FnStartSym, const MCSymbol *FnEndSym) - : MCEncodedFragment(FT_CVInlineLines, false), SiteFuncId(SiteFuncId), + : MCFragment(FT_CVInlineLines), SiteFuncId(SiteFuncId), StartFileId(StartFileId), StartLineNum(StartLineNum), FnStartSym(FnStartSym), FnEndSym(FnEndSym) {} @@ -448,7 +431,7 @@ public: }; /// Fragment representing the .cv_def_range directive. -class MCCVDefRangeFragment : public MCEncodedFragment { +class MCCVDefRangeFragment : public MCFragment { ArrayRef<std::pair<const MCSymbol *, const MCSymbol *>> Ranges; StringRef FixedSizePortion; @@ -460,8 +443,7 @@ public: MCCVDefRangeFragment( ArrayRef<std::pair<const MCSymbol *, const MCSymbol *>> Ranges, StringRef FixedSizePortion) - : MCEncodedFragment(FT_CVDefRange, false), - Ranges(Ranges.begin(), Ranges.end()), + : MCFragment(FT_CVDefRange), Ranges(Ranges.begin(), Ranges.end()), FixedSizePortion(FixedSizePortion) {} ArrayRef<std::pair<const MCSymbol *, const MCSymbol *>> getRanges() const { @@ -492,8 +474,7 @@ class MCBoundaryAlignFragment : public MCFragment { public: MCBoundaryAlignFragment(Align AlignBoundary, const MCSubtargetInfo &STI) - : MCFragment(FT_BoundaryAlign, false), AlignBoundary(AlignBoundary), - STI(STI) {} + : MCFragment(FT_BoundaryAlign), AlignBoundary(AlignBoundary), STI(STI) {} uint64_t getSize() const { return Size; } void setSize(uint64_t Value) { Size = Value; } @@ -634,28 +615,11 @@ public: bool isBssSection() const { return IsBss; } }; -inline SmallVectorImpl<char> &MCFragment::getContentsForAppending() { - SmallVectorImpl<char> &S = getParent()->ContentStorage; - if (LLVM_UNLIKELY(ContentEnd != S.size())) { - // Move the elements to the end. Reserve space to avoid invalidating - // S.begin()+I for `append`. - auto Size = ContentEnd - ContentStart; - auto I = std::exchange(ContentStart, S.size()); - S.reserve(S.size() + Size); - S.append(S.begin() + I, S.begin() + I + Size); - } - return S; -} -inline void MCFragment::doneAppending() { - ContentEnd = getParent()->ContentStorage.size(); -} inline MutableArrayRef<char> MCFragment::getContents() { - return MutableArrayRef(getParent()->ContentStorage) - .slice(ContentStart, ContentEnd - ContentStart); + return {reinterpret_cast<char *>(this + 1), FixedSize}; } inline ArrayRef<char> MCFragment::getContents() const { - return ArrayRef(getParent()->ContentStorage) - .slice(ContentStart, ContentEnd - ContentStart); + return {reinterpret_cast<const char *>(this + 1), FixedSize}; } inline MutableArrayRef<char> MCFragment::getVarContents() { @@ -680,11 +644,10 @@ inline ArrayRef<MCFixup> MCFragment::getFixups() const { inline MutableArrayRef<MCFixup> MCFragment::getVarFixups() { return MutableArrayRef(getParent()->FixupStorage) - .slice(VarFixupStart, VarFixupEnd - VarFixupStart); + .slice(VarFixupStart, VarFixupSize); } inline ArrayRef<MCFixup> MCFragment::getVarFixups() const { - return ArrayRef(getParent()->FixupStorage) - .slice(VarFixupStart, VarFixupEnd - VarFixupStart); + return ArrayRef(getParent()->FixupStorage).slice(VarFixupStart, VarFixupSize); } //== FT_Relaxable functions diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index f66f546..7b751ba 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -1550,7 +1550,7 @@ void PEIImpl::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF, // If this instruction has a FrameIndex operand, we need to // use that target machine register info object to eliminate // it. - TRI.eliminateFrameIndex(MI, SPAdj, i); + TRI.eliminateFrameIndex(MI, SPAdj, i, RS); // Reset the iterator if we were at the beginning of the BB. if (AtBeginning) { diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 583a85a..a5bd97a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -2217,8 +2217,9 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) { switch (getTypeAction(InVT)) { case TargetLowering::TypePromoteInteger: { - // TODO: Handle big endian - if (OutVT.isVector() && DAG.getDataLayout().isLittleEndian()) { + // TODO: Handle big endian & vector input type. + if (OutVT.isVector() && !InVT.isVector() && + DAG.getDataLayout().isLittleEndian()) { EVT EltVT = OutVT.getVectorElementType(); TypeSize EltSize = EltVT.getSizeInBits(); TypeSize NInSize = NInVT.getSizeInBits(); diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 48d6b99..e3f2a193 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -6482,8 +6482,8 @@ SDValue TargetLowering::buildSDIVPow2WithCMov( Created.push_back(CMov.getNode()); // Divide by pow2. - SDValue SRA = - DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, VT)); + SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, CMov, + DAG.getShiftAmountConstant(Lg2, VT, DL)); // If we're dividing by a positive value, we're done. Otherwise, we must // negate the result. diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp index a8559e7..6de6cc7 100644 --- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp +++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp @@ -891,7 +891,7 @@ RuntimeDyldImpl::emitSection(const ObjectFile &Obj, // Align DataSize to stub alignment if we have any stubs (PaddingSize will // have been increased above to account for this). if (StubBufSize > 0) - DataSize &= -(uint64_t)getStubAlignment().value(); + DataSize &= -getStubAlignment().value(); } LLVM_DEBUG(dbgs() << "emitSection SectionID: " << SectionID << " Name: " diff --git a/llvm/lib/Frontend/HLSL/RootSignatureMetadata.cpp b/llvm/lib/Frontend/HLSL/RootSignatureMetadata.cpp index 48ff1ca..6d89fa7 100644 --- a/llvm/lib/Frontend/HLSL/RootSignatureMetadata.cpp +++ b/llvm/lib/Frontend/HLSL/RootSignatureMetadata.cpp @@ -270,11 +270,11 @@ Error MetadataParser::parseRootConstants(mcdxbc::RootSignatureDesc &RSD, Error MetadataParser::parseRootDescriptors( mcdxbc::RootSignatureDesc &RSD, MDNode *RootDescriptorNode, RootSignatureElementKind ElementKind) { - assert(ElementKind == RootSignatureElementKind::SRV || - ElementKind == RootSignatureElementKind::UAV || - ElementKind == RootSignatureElementKind::CBV && - "parseRootDescriptors should only be called with RootDescriptor " - "element kind."); + assert((ElementKind == RootSignatureElementKind::SRV || + ElementKind == RootSignatureElementKind::UAV || + ElementKind == RootSignatureElementKind::CBV) && + "parseRootDescriptors should only be called with RootDescriptor " + "element kind."); if (RootDescriptorNode->getNumOperands() != 5) return make_error<InvalidRSMetadataFormat>("Root Descriptor Element"); diff --git a/llvm/lib/Frontend/Offloading/CMakeLists.txt b/llvm/lib/Frontend/Offloading/CMakeLists.txt index 8e1ede9..9747dbd 100644 --- a/llvm/lib/Frontend/Offloading/CMakeLists.txt +++ b/llvm/lib/Frontend/Offloading/CMakeLists.txt @@ -1,6 +1,7 @@ add_llvm_component_library(LLVMFrontendOffloading Utility.cpp OffloadWrapper.cpp + PropertySet.cpp ADDITIONAL_HEADER_DIRS ${LLVM_MAIN_INCLUDE_DIR}/llvm/Frontend diff --git a/llvm/lib/Frontend/Offloading/PropertySet.cpp b/llvm/lib/Frontend/Offloading/PropertySet.cpp new file mode 100644 index 0000000..a70290d --- /dev/null +++ b/llvm/lib/Frontend/Offloading/PropertySet.cpp @@ -0,0 +1,102 @@ +///===- llvm/Frontend/Offloading/PropertySet.cpp --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/Frontend/Offloading/PropertySet.h" +#include "llvm/Support/Base64.h" +#include "llvm/Support/JSON.h" +#include "llvm/Support/MemoryBufferRef.h" + +using namespace llvm; +using namespace llvm::offloading; + +void llvm::offloading::writePropertiesToJSON( + const PropertySetRegistry &PSRegistry, raw_ostream &Out) { + json::OStream J(Out); + J.object([&] { + for (const auto &[CategoryName, PropSet] : PSRegistry) { + auto PropSetCapture = PropSet; + J.attributeObject(CategoryName, [&] { + for (const auto &[PropName, PropVal] : PropSetCapture) { + switch (PropVal.index()) { + case 0: + J.attribute(PropName, std::get<uint32_t>(PropVal)); + break; + case 1: + J.attribute(PropName, encodeBase64(std::get<ByteArray>(PropVal))); + break; + default: + llvm_unreachable("unsupported property type"); + } + } + }); + } + }); +} + +// note: createStringError has an overload that takes a format string, +// but it uses llvm::format instead of llvm::formatv, which does +// not work with json::Value. This is a helper function to use +// llvm::formatv with createStringError. +template <typename... Ts> auto createStringErrorV(Ts &&...Args) { + return createStringError(formatv(std::forward<Ts>(Args)...)); +} + +Expected<PropertyValue> +readPropertyValueFromJSON(const json::Value &PropValueVal) { + if (std::optional<uint64_t> Val = PropValueVal.getAsUINT64()) + return PropertyValue(static_cast<uint32_t>(*Val)); + + if (std::optional<StringRef> Val = PropValueVal.getAsString()) { + std::vector<char> Decoded; + if (Error E = decodeBase64(*Val, Decoded)) + return createStringErrorV("unable to base64 decode the string {0}: {1}", + Val, toString(std::move(E))); + return PropertyValue(ByteArray(Decoded.begin(), Decoded.end())); + } + + return createStringErrorV("expected a uint64 or a string, got {0}", + PropValueVal); +} + +Expected<PropertySetRegistry> +llvm::offloading::readPropertiesFromJSON(MemoryBufferRef Buf) { + PropertySetRegistry Res; + Expected<json::Value> V = json::parse(Buf.getBuffer()); + if (Error E = V.takeError()) + return E; + + const json::Object *O = V->getAsObject(); + if (!O) + return createStringErrorV( + "error while deserializing property set registry: " + "expected JSON object, got {0}", + *V); + + for (const auto &[CategoryName, Value] : *O) { + const json::Object *PropSetVal = Value.getAsObject(); + if (!PropSetVal) + return createStringErrorV("error while deserializing property set {0}: " + "expected JSON array, got {1}", + CategoryName.str(), Value); + + PropertySet &PropSet = Res[CategoryName.str()]; + for (const auto &[PropName, PropValueVal] : *PropSetVal) { + Expected<PropertyValue> Prop = readPropertyValueFromJSON(PropValueVal); + if (Error E = Prop.takeError()) + return createStringErrorV( + "error while deserializing property {0} in property set {1}: {2}", + PropName.str(), CategoryName.str(), toString(std::move(E))); + + auto [It, Inserted] = + PropSet.try_emplace(PropName.str(), std::move(*Prop)); + assert(Inserted && "Property already exists in PropertySet"); + (void)Inserted; + } + } + return Res; +} diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp index 8500fd1..5c8e904 100644 --- a/llvm/lib/MC/MCAssembler.cpp +++ b/llvm/lib/MC/MCAssembler.cpp @@ -59,7 +59,8 @@ STATISTIC(EmittedFillFragments, "Number of emitted assembler fragments - fill"); STATISTIC(EmittedNopsFragments, "Number of emitted assembler fragments - nops"); STATISTIC(EmittedOrgFragments, "Number of emitted assembler fragments - org"); -STATISTIC(evaluateFixup, "Number of evaluated fixups"); +STATISTIC(Fixups, "Number of fixups"); +STATISTIC(FixupEvalForRelax, "Number of fixup evaluations for relaxation"); STATISTIC(ObjectBytes, "Number of emitted object file bytes"); STATISTIC(RelaxationSteps, "Number of assembler layout and relaxation steps"); STATISTIC(RelaxedInstructions, "Number of relaxed instructions"); @@ -140,9 +141,9 @@ bool MCAssembler::isThumbFunc(const MCSymbol *Symbol) const { bool MCAssembler::evaluateFixup(const MCFragment &F, MCFixup &Fixup, MCValue &Target, uint64_t &Value, - bool RecordReloc, - MutableArrayRef<char> Contents) const { - ++stats::evaluateFixup; + bool RecordReloc, uint8_t *Data) const { + if (RecordReloc) + ++stats::Fixups; // FIXME: This code has some duplication with recordRelocation. We should // probably merge the two into a single callback that tries to evaluate a @@ -185,7 +186,7 @@ bool MCAssembler::evaluateFixup(const MCFragment &F, MCFixup &Fixup, if (IsResolved && mc::isRelocRelocation(Fixup.getKind())) IsResolved = false; - getBackend().applyFixup(F, Fixup, Target, Contents, Value, IsResolved); + getBackend().applyFixup(F, Fixup, Target, Data, Value, IsResolved); return true; } @@ -703,21 +704,25 @@ void MCAssembler::layout() { for (MCFixup &Fixup : F.getFixups()) { uint64_t FixedValue; MCValue Target; + assert(mc::isRelocRelocation(Fixup.getKind()) || + Fixup.getOffset() <= F.getFixedSize()); + auto *Data = + reinterpret_cast<uint8_t *>(Contents.data() + Fixup.getOffset()); evaluateFixup(F, Fixup, Target, FixedValue, - /*RecordReloc=*/true, Contents); + /*RecordReloc=*/true, Data); } - if (F.getVarFixups().size()) { - // In the variable part, fixup offsets are relative to the fixed part's - // start. Extend the variable contents to the left to account for the - // fixed part size. - Contents = MutableArrayRef(F.getParent()->ContentStorage) - .slice(F.VarContentStart - Contents.size(), F.getSize()); - for (MCFixup &Fixup : F.getVarFixups()) { - uint64_t FixedValue; - MCValue Target; - evaluateFixup(F, Fixup, Target, FixedValue, - /*RecordReloc=*/true, Contents); - } + // In the variable part, fixup offsets are relative to the fixed part's + // start. + for (MCFixup &Fixup : F.getVarFixups()) { + uint64_t FixedValue; + MCValue Target; + assert(mc::isRelocRelocation(Fixup.getKind()) || + (Fixup.getOffset() >= F.getFixedSize() && + Fixup.getOffset() <= F.getSize())); + auto *Data = reinterpret_cast<uint8_t *>( + F.getVarContents().data() + (Fixup.getOffset() - F.getFixedSize())); + evaluateFixup(F, Fixup, Target, FixedValue, + /*RecordReloc=*/true, Data); } } } @@ -735,7 +740,7 @@ void MCAssembler::Finish() { bool MCAssembler::fixupNeedsRelaxation(const MCFragment &F, const MCFixup &Fixup) const { - assert(getBackendPtr() && "Expected assembler backend"); + ++stats::FixupEvalForRelax; MCValue Target; uint64_t Value; bool Resolved = evaluateFixup(F, const_cast<MCFixup &>(Fixup), Target, Value, diff --git a/llvm/lib/MC/MCCodeView.cpp b/llvm/lib/MC/MCCodeView.cpp index 7d528a5..3a5f01c 100644 --- a/llvm/lib/MC/MCCodeView.cpp +++ b/llvm/lib/MC/MCCodeView.cpp @@ -695,5 +695,7 @@ void CodeViewContext::encodeDefRange(const MCAssembler &Asm, } Frag.setVarContents(Contents); + assert(Fixups.size() < 256 && "Store fixups outside of MCFragment's VarFixup " + "storage if the number ever exceeds 256"); Frag.setVarFixups(Fixups); } diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp index e277143..200e29a 100644 --- a/llvm/lib/MC/MCObjectStreamer.cpp +++ b/llvm/lib/MC/MCObjectStreamer.cpp @@ -46,27 +46,83 @@ MCAssembler *MCObjectStreamer::getAssemblerPtr() { return nullptr; } +constexpr size_t FragBlockSize = 16384; +// Ensure the new fragment can at least store a few bytes. +constexpr size_t NewFragHeadroom = 8; + +static_assert(NewFragHeadroom >= alignof(MCFragment)); +static_assert(FragBlockSize >= sizeof(MCFragment) + NewFragHeadroom); + +MCFragment *MCObjectStreamer::allocFragSpace(size_t Headroom) { + auto Size = std::max(FragBlockSize, sizeof(MCFragment) + Headroom); + FragSpace = Size - sizeof(MCFragment); + auto Block = std::unique_ptr<uint8_t[]>(new uint8_t[Size]); + auto *F = reinterpret_cast<MCFragment *>(Block.get()); + FragStorage.push_back(std::move(Block)); + return F; +} + void MCObjectStreamer::newFragment() { - addFragment(getContext().allocFragment<MCFragment>()); + MCFragment *F; + if (LLVM_LIKELY(sizeof(MCFragment) + NewFragHeadroom <= FragSpace)) { + auto End = reinterpret_cast<size_t>(getCurFragEnd()); + F = reinterpret_cast<MCFragment *>( + alignToPowerOf2(End, alignof(MCFragment))); + FragSpace -= size_t(F) - End + sizeof(MCFragment); + } else { + F = allocFragSpace(0); + } + new (F) MCFragment(); + addFragment(F); +} + +void MCObjectStreamer::ensureHeadroom(size_t Headroom) { + if (Headroom <= FragSpace) + return; + auto *F = allocFragSpace(Headroom); + new (F) MCFragment(); + addFragment(F); } -void MCObjectStreamer::insert(MCFragment *F) { - assert(F->getKind() != MCFragment::FT_Data && +void MCObjectStreamer::insert(MCFragment *Frag) { + assert(Frag->getKind() != MCFragment::FT_Data && "F should have a variable-size tail"); + // Frag is not connected to FragSpace. Before modifying CurFrag with + // addFragment(Frag), allocate an empty fragment to maintain FragSpace + // connectivity, potentially reusing CurFrag's associated space. + MCFragment *F; + if (LLVM_LIKELY(sizeof(MCFragment) + NewFragHeadroom <= FragSpace)) { + auto End = reinterpret_cast<size_t>(getCurFragEnd()); + F = reinterpret_cast<MCFragment *>( + alignToPowerOf2(End, alignof(MCFragment))); + FragSpace -= size_t(F) - End + sizeof(MCFragment); + } else { + F = allocFragSpace(0); + } + new (F) MCFragment(); + + addFragment(Frag); addFragment(F); - newFragment(); } void MCObjectStreamer::appendContents(ArrayRef<char> Contents) { - CurFrag->appendContents(Contents); + ensureHeadroom(Contents.size()); + assert(FragSpace >= Contents.size()); + llvm::copy(Contents, getCurFragEnd()); + CurFrag->FixedSize += Contents.size(); + FragSpace -= Contents.size(); } -void MCObjectStreamer::appendContents(size_t Num, char Elt) { - CurFrag->appendContents(Num, Elt); +void MCObjectStreamer::appendContents(size_t Num, uint8_t Elt) { + ensureHeadroom(Num); + MutableArrayRef<uint8_t> Data(getCurFragEnd(), Num); + llvm::fill(Data, Elt); + CurFrag->FixedSize += Num; + FragSpace -= Num; } void MCObjectStreamer::addFixup(const MCExpr *Value, MCFixupKind Kind) { - CurFrag->addFixup(MCFixup::create(CurFrag->getFixedSize(), Value, Kind)); + CurFrag->addFixup(MCFixup::create(getCurFragSize(), Value, Kind)); } // As a compile-time optimization, avoid allocating and evaluating an MCExpr @@ -115,6 +171,8 @@ void MCObjectStreamer::reset() { } EmitEHFrame = true; EmitDebugFrame = false; + FragStorage.clear(); + FragSpace = 0; MCStreamer::reset(); } @@ -143,7 +201,6 @@ void MCObjectStreamer::emitCFISections(bool EH, bool Debug, bool SFrame) { void MCObjectStreamer::emitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) { MCStreamer::emitValueImpl(Value, Size, Loc); - MCFragment *DF = getCurrentFragment(); MCDwarfLineEntry::make(this, getCurrentSectionOnly()); @@ -158,9 +215,9 @@ void MCObjectStreamer::emitValueImpl(const MCExpr *Value, unsigned Size, emitIntValue(AbsValue, Size); return; } - DF->addFixup(MCFixup::create(DF->getContents().size(), Value, - MCFixup::getDataKindForSize(Size))); - DF->appendContents(Size, 0); + ensureHeadroom(Size); + addFixup(Value, MCFixup::getDataKindForSize(Size)); + appendContents(Size, 0); } MCSymbol *MCObjectStreamer::emitCFILabel() { @@ -194,7 +251,7 @@ void MCObjectStreamer::emitLabel(MCSymbol *Symbol, SMLoc Loc) { // section. MCFragment *F = CurFrag; Symbol->setFragment(F); - Symbol->setOffset(F->getContents().size()); + Symbol->setOffset(F->getFixedSize()); emitPendingAssignments(Symbol); } @@ -260,6 +317,21 @@ void MCObjectStreamer::changeSection(MCSection *Section, uint32_t Subsection) { F0 = CurFrag; } + // To maintain connectivity between CurFrag and FragSpace when CurFrag is + // modified, allocate an empty fragment and append it to the fragment list. + // (Subsections[I].second.Tail is not connected to FragSpace.) + MCFragment *F; + if (LLVM_LIKELY(sizeof(MCFragment) + NewFragHeadroom <= FragSpace)) { + auto End = reinterpret_cast<size_t>(getCurFragEnd()); + F = reinterpret_cast<MCFragment *>( + alignToPowerOf2(End, alignof(MCFragment))); + FragSpace -= size_t(F) - End + sizeof(MCFragment); + } else { + F = allocFragSpace(0); + } + new (F) MCFragment(); + F->setParent(Section); + auto &Subsections = Section->Subsections; size_t I = 0, E = Subsections.size(); while (I != E && Subsections[I].first < Subsection) @@ -267,13 +339,16 @@ void MCObjectStreamer::changeSection(MCSection *Section, uint32_t Subsection) { // If the subsection number is not in the sorted Subsections list, create a // new fragment list. if (I == E || Subsections[I].first != Subsection) { - auto *F = getContext().allocFragment<MCFragment>(); - F->setParent(Section); Subsections.insert(Subsections.begin() + I, {Subsection, MCSection::FragList{F, F}}); + Section->CurFragList = &Subsections[I].second; + CurFrag = F; + } else { + Section->CurFragList = &Subsections[I].second; + CurFrag = Subsections[I].second.Tail; + // Ensure CurFrag is associated with FragSpace. + addFragment(F); } - Section->CurFragList = &Subsections[I].second; - CurFrag = Section->CurFragList->Tail; // Define the section symbol at subsection 0's initial fragment if required. if (!NewSec) @@ -344,11 +419,15 @@ void MCObjectStreamer::emitInstToData(const MCInst &Inst, MCFragment *F = getCurrentFragment(); // Append the instruction to the data fragment. - size_t CodeOffset = F->getContents().size(); + size_t CodeOffset = getCurFragSize(); + SmallString<16> Content; SmallVector<MCFixup, 1> Fixups; - getAssembler().getEmitter().encodeInstruction( - Inst, F->getContentsForAppending(), Fixups, STI); - F->doneAppending(); + getAssembler().getEmitter().encodeInstruction(Inst, Content, Fixups, STI); + appendContents(Content); + if (CurFrag != F) { + F = CurFrag; + CodeOffset = 0; + } F->setHasInstructions(STI); if (Fixups.empty()) diff --git a/llvm/lib/MC/MCSection.cpp b/llvm/lib/MC/MCSection.cpp index 4f28267..27ca131 100644 --- a/llvm/lib/MC/MCSection.cpp +++ b/llvm/lib/MC/MCSection.cpp @@ -83,12 +83,14 @@ void MCFragment::appendFixups(ArrayRef<MCFixup> Fixups) { } void MCFragment::setVarFixups(ArrayRef<MCFixup> Fixups) { + assert(Fixups.size() < 256 && + "variable-size tail cannot have more than 256 fixups"); auto &S = getParent()->FixupStorage; - if (VarFixupStart + Fixups.size() > VarFixupEnd) { + if (Fixups.size() > VarFixupSize) { VarFixupStart = S.size(); S.resize_for_overwrite(S.size() + Fixups.size()); } - VarFixupEnd = VarFixupStart + Fixups.size(); + VarFixupSize = Fixups.size(); // Source fixup offsets are relative to the variable part's start. Add the // fixed part size to make them relative to the fixed part's start. std::transform(Fixups.begin(), Fixups.end(), S.begin() + VarFixupStart, diff --git a/llvm/lib/MC/MCWin64EH.cpp b/llvm/lib/MC/MCWin64EH.cpp index 72a8dd7..a87648a 100644 --- a/llvm/lib/MC/MCWin64EH.cpp +++ b/llvm/lib/MC/MCWin64EH.cpp @@ -318,6 +318,9 @@ static void EmitUnwindInfo(MCStreamer &streamer, WinEH::FrameInfo *info) { // Emit the epilog instructions. if (EnableUnwindV2) { + // Ensure the fixups and appended content apply to the same fragment. + OS->ensureHeadroom(info->EpilogMap.size() * 2); + bool IsLast = true; for (const auto &Epilog : llvm::reverse(info->EpilogMap)) { if (IsLast) { diff --git a/llvm/lib/MC/MCWinCOFFStreamer.cpp b/llvm/lib/MC/MCWinCOFFStreamer.cpp index 1ffe25c..8be5054 100644 --- a/llvm/lib/MC/MCWinCOFFStreamer.cpp +++ b/llvm/lib/MC/MCWinCOFFStreamer.cpp @@ -280,6 +280,7 @@ void MCWinCOFFStreamer::emitCOFFSymbolIndex(MCSymbol const *Symbol) { void MCWinCOFFStreamer::emitCOFFSectionIndex(const MCSymbol *Symbol) { visitUsedSymbol(*Symbol); const MCSymbolRefExpr *SRE = MCSymbolRefExpr::create(Symbol, getContext()); + ensureHeadroom(2); addFixup(SRE, FK_SecRel_2); appendContents(2, 0); } @@ -293,6 +294,7 @@ void MCWinCOFFStreamer::emitCOFFSecRel32(const MCSymbol *Symbol, if (Offset) MCE = MCBinaryExpr::createAdd( MCE, MCConstantExpr::create(Offset, getContext()), getContext()); + ensureHeadroom(4); addFixup(MCE, FK_SecRel_4); // Emit 4 bytes (zeros) to the object file. appendContents(4, 0); @@ -308,6 +310,7 @@ void MCWinCOFFStreamer::emitCOFFImgRel32(const MCSymbol *Symbol, if (Offset) MCE = MCBinaryExpr::createAdd( MCE, MCConstantExpr::create(Offset, getContext()), getContext()); + ensureHeadroom(4); addFixup(MCE, FK_Data_4); // Emit 4 bytes (zeros) to the object file. appendContents(4, 0); @@ -318,6 +321,7 @@ void MCWinCOFFStreamer::emitCOFFSecNumber(MCSymbol const *Symbol) { // Create Symbol for section number. const MCExpr *MCE = MCCOFFSectionNumberTargetExpr::create( *Symbol, this->getWriter(), getContext()); + ensureHeadroom(4); addFixup(MCE, FK_Data_4); // Emit 4 bytes (zeros) to the object file. appendContents(4, 0); @@ -328,6 +332,7 @@ void MCWinCOFFStreamer::emitCOFFSecOffset(MCSymbol const *Symbol) { // Create Symbol for section offset. const MCExpr *MCE = MCCOFFSectionOffsetTargetExpr::create(*Symbol, getContext()); + ensureHeadroom(4); addFixup(MCE, FK_Data_4); // Emit 4 bytes (zeros) to the object file. appendContents(4, 0); diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp index 6912caf..7a2b679 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp @@ -79,8 +79,7 @@ public: } void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const override; @@ -421,9 +420,8 @@ static bool shouldForceRelocation(const MCFixup &Fixup) { } void AArch64AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { if (shouldForceRelocation(Fixup)) IsResolved = false; maybeAddReloc(F, Fixup, Target, Value, IsResolved); @@ -460,8 +458,8 @@ void AArch64AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // Shift the value into position. Value <<= Info.TargetOffset; - unsigned Offset = Fixup.getOffset(); - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); // Used to point to big endian bytes. unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind()); @@ -471,15 +469,16 @@ void AArch64AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, if (FulleSizeInBytes == 0) { // Handle as little-endian for (unsigned i = 0; i != NumBytes; ++i) { - Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); + Data[i] |= uint8_t((Value >> (i * 8)) & 0xff); } } else { // Handle as big-endian - assert((Offset + FulleSizeInBytes) <= Data.size() && "Invalid fixup size!"); + assert(Fixup.getOffset() + FulleSizeInBytes <= F.getSize() && + "Invalid fixup size!"); assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!"); for (unsigned i = 0; i != NumBytes; ++i) { unsigned Idx = FulleSizeInBytes - 1 - i; - Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); + Data[Idx] |= uint8_t((Value >> (i * 8)) & 0xff); } } @@ -492,9 +491,9 @@ void AArch64AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // If the immediate is negative, generate MOVN else MOVZ. // (Bit 30 = 0) ==> MOVN, (Bit 30 = 1) ==> MOVZ. if (SignedValue < 0) - Data[Offset + 3] &= ~(1 << 6); + Data[3] &= ~(1 << 6); else - Data[Offset + 3] |= (1 << 6); + Data[3] |= (1 << 6); } } diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 8a0c4ac..18f3c47 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -1160,6 +1160,12 @@ def FeatureTanhInsts : SubtargetFeature<"tanh-insts", "Has v_tanh_f32/f16 instructions" >; +def FeatureTensorCvtLutInsts : SubtargetFeature<"tensor-cvt-lut-insts", + "HasTensorCvtLutInsts", + "true", + "Has v_perm_pk16* instructions" +>; + def FeatureTransposeLoadF4F6Insts : SubtargetFeature<"transpose-load-f4f6-insts", "HasTransposeLoadF4F6Insts", "true", @@ -2030,6 +2036,7 @@ def FeatureISAVersion12_50 : FeatureSet< FeatureDPPSrc1SGPR, FeatureBitOp3Insts, FeatureTanhInsts, + FeatureTensorCvtLutInsts, FeatureTransposeLoadF4F6Insts, FeatureBF16TransInsts, FeatureBF16ConversionInsts, @@ -2785,6 +2792,9 @@ def HasBitOp3Insts : Predicate<"Subtarget->hasBitOp3Insts()">, def HasTanhInsts : Predicate<"Subtarget->hasTanhInsts()">, AssemblerPredicate<(all_of FeatureTanhInsts)>; +def HasTensorCvtLutInsts : Predicate<"Subtarget->hasTensorCvtLutInsts()">, + AssemblerPredicate<(all_of FeatureTensorCvtLutInsts)>; + def HasTransposeLoadF4F6Insts : Predicate<"Subtarget->hasTransposeLoadF4F6Insts()">, AssemblerPredicate<(all_of FeatureTransposeLoadF4F6Insts)>; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 31c4f62..d059480 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -367,6 +367,18 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, setTruncStoreAction(MVT::v4f64, MVT::v4bf16, Expand); setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand); + setTruncStoreAction(MVT::v5i32, MVT::v5i1, Expand); + setTruncStoreAction(MVT::v5i32, MVT::v5i8, Expand); + setTruncStoreAction(MVT::v5i32, MVT::v5i16, Expand); + + setTruncStoreAction(MVT::v6i32, MVT::v6i1, Expand); + setTruncStoreAction(MVT::v6i32, MVT::v6i8, Expand); + setTruncStoreAction(MVT::v6i32, MVT::v6i16, Expand); + + setTruncStoreAction(MVT::v7i32, MVT::v7i1, Expand); + setTruncStoreAction(MVT::v7i32, MVT::v7i8, Expand); + setTruncStoreAction(MVT::v7i32, MVT::v7i16, Expand); + setTruncStoreAction(MVT::v8f64, MVT::v8f32, Expand); setTruncStoreAction(MVT::v8f64, MVT::v8bf16, Expand); setTruncStoreAction(MVT::v8f64, MVT::v8f16, Expand); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 5aa0ebf..d11e5a3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -4603,6 +4603,42 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case Intrinsic::amdgcn_cvt_scale_pk8_f32_fp8: case Intrinsic::amdgcn_cvt_scale_pk8_f32_bf8: case Intrinsic::amdgcn_cvt_scale_pk8_f32_fp4: + case Intrinsic::amdgcn_cvt_scale_pk16_f16_fp6: + case Intrinsic::amdgcn_cvt_scale_pk16_bf16_fp6: + case Intrinsic::amdgcn_cvt_scale_pk16_f16_bf6: + case Intrinsic::amdgcn_cvt_scale_pk16_bf16_bf6: + case Intrinsic::amdgcn_cvt_scale_pk16_f32_fp6: + case Intrinsic::amdgcn_cvt_scale_pk16_f32_bf6: + case Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_bf16: + case Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_bf16: + case Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f16: + case Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f16: + case Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f32: + case Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f32: + case Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f32: + case Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f16: + case Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_bf16: + case Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f32: + case Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f32: + case Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f16: + case Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f16: + case Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_bf16: + case Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_bf16: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_bf16: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_bf16: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f16: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f16: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f32: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f32: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f32: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f16: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_bf16: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f32: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f32: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f16: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f16: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_bf16: + case Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_bf16: case Intrinsic::amdgcn_sat_pk4_i4_i8: case Intrinsic::amdgcn_sat_pk4_u4_u8: case Intrinsic::amdgcn_fmed3: @@ -4777,6 +4813,9 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_fp8: case Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_bf8: case Intrinsic::amdgcn_swmmac_i32_16x16x128_iu8: + case Intrinsic::amdgcn_perm_pk16_b4_u4: + case Intrinsic::amdgcn_perm_pk16_b6_u4: + case Intrinsic::amdgcn_perm_pk16_b8_u4: return getDefaultMappingVOP(MI); case Intrinsic::amdgcn_log: case Intrinsic::amdgcn_exp2: diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index 6fe3abc..c84ba1a 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -236,6 +236,7 @@ protected: bool Has64BitLiterals = false; bool HasBitOp3Insts = false; bool HasTanhInsts = false; + bool HasTensorCvtLutInsts = false; bool HasTransposeLoadF4F6Insts = false; bool HasPrngInst = false; bool HasBVHDualAndBVH8Insts = false; @@ -1411,6 +1412,8 @@ public: bool hasTanhInsts() const { return HasTanhInsts; } + bool hasTensorCvtLutInsts() const { return HasTensorCvtLutInsts; } + bool hasAddPC64Inst() const { return GFX1250Insts; } bool hasMinimum3Maximum3PKF16() const { diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp index 86d56855..4e4660c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -33,8 +33,7 @@ public: AMDGPUAsmBackend(const Target &T) : MCAsmBackend(llvm::endianness::little) {} void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const override; @@ -129,9 +128,8 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, } void AMDGPUAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { if (Target.getSpecifier()) IsResolved = false; maybeAddReloc(F, Fixup, Target, Value, IsResolved); @@ -148,13 +146,13 @@ void AMDGPUAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, Value <<= Info.TargetOffset; unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); - uint32_t Offset = Fixup.getOffset(); - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); // For each byte of the fragment that the fixup touches, mask in the bits from // the fixup value. for (unsigned i = 0; i != NumBytes; ++i) - Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff); + Data[i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff); } std::optional<MCFixupKind> diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index a3e20ba..4698a58 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1774,6 +1774,7 @@ class getVALUDstForVT<ValueType VT, bit IsTrue16 = 0, bit IsVOP3Encoding = 0> { !eq(VT.Size, 256) : VOPDstOperand<VReg_256>, !eq(VT.Size, 192) : VOPDstOperand<VReg_192>, !eq(VT.Size, 128) : VOPDstOperand<VReg_128>, + !eq(VT.Size, 96) : VOPDstOperand<VReg_96>, !eq(VT.Size, 64) : VOPDstOperand<VReg_64>, !eq(VT.Size, 32) : VOPDstOperand<VGPR_32>, !eq(VT.Size, 16) : op16, @@ -1924,6 +1925,7 @@ class getVOP3DPPSrcForVT<ValueType VT, bit IsFake16 = 1> { !eq(VT, v2f16) : VCSrc_v2f16, !eq(VT, v2bf16) : VCSrc_v2bf16, !eq(VT, f32) : VCSrc_f32, + !eq(VT, v2i32) : VCSrc_v2b32, 1 : VCSrc_b32); } @@ -2935,6 +2937,9 @@ def VOP_V2BF16_F32_F32_I32 : VOPProfile <[v2bf16, f32, f32, i32]>; def VOP_V2F16_F32_F32_I32 : VOPProfile <[v2f16, f32, f32, i32]>; def VOP_V6I32_V32F16_F32 : VOPProfile<[v6i32, v32f16, f32, untyped]>; def VOP_V6I32_V32BF16_F32 : VOPProfile<[v6i32, v32bf16, f32, untyped]>; +def VOP_V3I32_V16F16_F32 : VOPProfile<[v3i32, v16f16, f32, untyped]>; +def VOP_V3I32_V16BF16_F32 : VOPProfile<[v3i32, v16bf16, f32, untyped]>; +def VOP_V3I32_V16F32_F32 : VOPProfile<[v3i32, v16f32, f32, untyped]>; def VOP_V6I32_V16F32_V16F32_F32 : VOPProfile<[v6i32, v16f32, v16f32, f32]>; def VOP_V2F16_I32_F32 : VOPProfile<[v2f16, i32, f32, untyped]>; def VOP_V2I16_F32_F32_F32 : VOPProfile<[v2i16, f32, f32, f32]>; @@ -2948,6 +2953,8 @@ def VOP_BF16_F32_I32 : VOPProfile<[bf16, f32, i32, untyped]>; def VOP_F16_F32_I32 : VOPProfile<[f16, f32, i32, untyped]>; def VOP_I32_BF16_I32_F32 : VOPProfile<[i32, bf16, i32, f32]>; def VOP_I32_F16_I32_F32 : VOPProfile<[i32, f16, i32, f32]>; +def VOP_V16F16_V3I32_I32 : VOPProfile<[v16f16, v3i32, i32, untyped]>; +def VOP_V16BF16_V3I32_I32 : VOPProfile<[v16bf16, v3i32, i32, untyped]>; def VOP_V8F16_V2I32_I32 : VOPProfile<[v8f16, v2i32, i32, untyped]>; def VOP_V8BF16_V2I32_I32 : VOPProfile<[v8bf16, v2i32, i32, untyped]>; def VOP_V8F16_I32_I32 : VOPProfile<[v8f16, i32, i32, untyped]>; @@ -2955,11 +2962,26 @@ def VOP_V8BF16_I32_I32 : VOPProfile<[v8bf16, i32, i32, untyped]>; def VOP_V16F32_V3I32_I32 : VOPProfile<[v16f32, v3i32, i32, untyped]>; def VOP_V8F32_V2I32_I32 : VOPProfile<[v8f32, v2i32, i32, untyped]>; def VOP_V8F32_I32_I32 : VOPProfile<[v8f32, i32, i32, untyped]>; +def VOP_V2I32_V8BF16_F32 : VOPProfile<[v2i32, v8bf16, f32, untyped]>; +def VOP_V2I32_V8F16_F32 : VOPProfile<[v2i32, v8f16, f32, untyped]>; +def VOP_V2I32_V8F32_F32 : VOPProfile<[v2i32, v8f32, f32, untyped]>; +def VOP_I32_V8F32_F32 : VOPProfile<[i32, v8f32, f32, untyped]>; +def VOP_I32_V8F16_F32 : VOPProfile<[i32, v8f16, f32, untyped]>; +def VOP_I32_V8BF16_F32 : VOPProfile<[i32, v8bf16, f32, untyped]>; def VOP_I32_F32_I32_F32 : VOPProfile<[i32, f32, i32, f32]>; def VOP_V6I32_V32BF16_I32_F32 : VOPProfile<[v6i32, v32bf16, i32, f32]>; def VOP_V6I32_V32F16_I32_F32 : VOPProfile<[v6i32, v32f16, i32, f32]>; def VOP_V6I32_V32F32_I32_F32 : VOPProfile<[v6i32, v32f32, i32, f32]>; +def VOP_V3I32_V16F16_I32_F32 : VOPProfile<[v3i32, v16f16, i32, f32]>; +def VOP_V3I32_V16BF16_I32_F32 : VOPProfile<[v3i32, v16bf16, i32, f32]>; +def VOP_V3I32_V16F32_I32_F32 : VOPProfile<[v3i32, v16f32, i32, f32]>; +def VOP_V2I32_V8BF16_I32_F32 : VOPProfile<[v2i32, v8bf16, i32, f32]>; +def VOP_V2I32_V8F16_I32_F32 : VOPProfile<[v2i32, v8f16, i32, f32]>; +def VOP_V2I32_V8F32_I32_F32 : VOPProfile<[v2i32, v8f32, i32, f32]>; +def VOP_I32_V8F32_I32_F32 : VOPProfile<[i32, v8f32, i32, f32]>; +def VOP_I32_V8F16_I32_F32 : VOPProfile<[i32, v8f16, i32, f32]>; +def VOP_I32_V8BF16_I32_F32 : VOPProfile<[i32, v8bf16, i32, f32]>; def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>; def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 36d1a3b..08d07c9 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -1302,6 +1302,7 @@ def VCSrc_f64 : SrcRegOrImm9 <VS_64, "OPERAND_REG_INLINE_C_FP64">; def VCSrc_v2b16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_V2INT16">; def VCSrc_v2bf16: SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_V2BF16">; def VCSrc_v2f16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_V2FP16">; +def VCSrc_v2b32 : SrcRegOrImm9 <VS_64, "OPERAND_REG_INLINE_C_V2INT32">; // True 16 Operands def VCSrcT_b16 : SrcRegOrImm9_t16 <"OPERAND_REG_INLINE_C_INT16">; diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index 19ce7f5..f4b6af6 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -1726,6 +1726,12 @@ multiclass VOP3CvtScaleSelInst<string OpName, VOPProfile P, SDPatternOperator no } } +let HasExtVOP3DPP = 0, HasModifiers = 0 in { +def VOP3_V2I32_I32_I32_V2I32 : VOP3_Profile<VOPProfile<[v2i32, i32, i32, v2i32]>>; +def VOP3_V3I32_I32_I64_V2I32 : VOP3_Profile<VOPProfile<[v3i32, i32, i64, v2i32]>>; +def VOP3_V4I32_I64_I64_V2I32 : VOP3_Profile<VOPProfile<[v4i32, i64, i64, v2i32]>>; +} + let Src0RC64 = VSrc_NoInline_v2f16 in { def VOP3_CVT_PK_F8_F16_Profile : VOP3_Profile<VOP_I16_V2F16>; def VOP3_CVT_PK_F8_F16_True16_Profile : VOP3_Profile_True16<VOP3_CVT_PK_F8_F16_Profile>; @@ -1771,6 +1777,12 @@ let SubtargetPredicate = isGFX1250Plus in { defm V_CVT_SCALE_PK8_BF16_BF8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_bf16_bf8", VOP_V8BF16_V2I32_I32, int_amdgcn_cvt_scale_pk8_bf16_bf8>; defm V_CVT_SCALE_PK8_F32_FP8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f32_fp8", VOP_V8F32_V2I32_I32, int_amdgcn_cvt_scale_pk8_f32_fp8>; defm V_CVT_SCALE_PK8_F32_BF8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f32_bf8", VOP_V8F32_V2I32_I32, int_amdgcn_cvt_scale_pk8_f32_bf8>; + defm V_CVT_SCALE_PK16_F16_FP6 : VOP3CvtScaleSelInst<"v_cvt_scale_pk16_f16_fp6", VOP_V16F16_V3I32_I32, int_amdgcn_cvt_scale_pk16_f16_fp6>; + defm V_CVT_SCALE_PK16_BF16_FP6 : VOP3CvtScaleSelInst<"v_cvt_scale_pk16_bf16_fp6", VOP_V16BF16_V3I32_I32, int_amdgcn_cvt_scale_pk16_bf16_fp6>; + defm V_CVT_SCALE_PK16_F16_BF6 : VOP3CvtScaleSelInst<"v_cvt_scale_pk16_f16_bf6", VOP_V16F16_V3I32_I32, int_amdgcn_cvt_scale_pk16_f16_bf6>; + defm V_CVT_SCALE_PK16_BF16_BF6 : VOP3CvtScaleSelInst<"v_cvt_scale_pk16_bf16_bf6", VOP_V16BF16_V3I32_I32, int_amdgcn_cvt_scale_pk16_bf16_bf6>; + defm V_CVT_SCALE_PK16_F32_FP6 : VOP3CvtScaleSelInst<"v_cvt_scale_pk16_f32_fp6", VOP_V16F32_V3I32_I32, int_amdgcn_cvt_scale_pk16_f32_fp6>; + defm V_CVT_SCALE_PK16_F32_BF6 : VOP3CvtScaleSelInst<"v_cvt_scale_pk16_f32_bf6", VOP_V16F32_V3I32_I32, int_amdgcn_cvt_scale_pk16_f32_bf6>; } // End Constraints = "@earlyclobber $vdst" defm V_CVT_SCALE_PK8_F16_FP4 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f16_fp4", VOP_V8F16_I32_I32, int_amdgcn_cvt_scale_pk8_f16_fp4>; @@ -1778,6 +1790,44 @@ let SubtargetPredicate = isGFX1250Plus in { defm V_CVT_SCALE_PK8_F32_FP4 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f32_fp4", VOP_V8F32_I32_I32, int_amdgcn_cvt_scale_pk8_f32_fp4>; } // End ReadsModeReg = 0 + let Constraints = "@earlyclobber $vdst" in { + let WaveSizePredicate = isWave32 in { + defm V_CVT_SCALEF32_PK8_FP8_BF16 : VOP3Inst<"v_cvt_scalef32_pk8_fp8_bf16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8BF16_F32>, int_amdgcn_cvt_scalef32_pk8_fp8_bf16>; + defm V_CVT_SCALEF32_PK8_BF8_BF16 : VOP3Inst<"v_cvt_scalef32_pk8_bf8_bf16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8BF16_F32>, int_amdgcn_cvt_scalef32_pk8_bf8_bf16>; + defm V_CVT_SCALEF32_PK8_FP8_F16 : VOP3Inst<"v_cvt_scalef32_pk8_fp8_f16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8F16_F32>, int_amdgcn_cvt_scalef32_pk8_fp8_f16>; + defm V_CVT_SCALEF32_PK8_BF8_F16 : VOP3Inst<"v_cvt_scalef32_pk8_bf8_f16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8F16_F32>, int_amdgcn_cvt_scalef32_pk8_bf8_f16>; + defm V_CVT_SCALEF32_PK8_FP8_F32 : VOP3Inst<"v_cvt_scalef32_pk8_fp8_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8F32_F32>, int_amdgcn_cvt_scalef32_pk8_fp8_f32>; + defm V_CVT_SCALEF32_PK8_BF8_F32 : VOP3Inst<"v_cvt_scalef32_pk8_bf8_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8F32_F32>, int_amdgcn_cvt_scalef32_pk8_bf8_f32>; + defm V_CVT_SCALEF32_PK8_FP4_F32 : VOP3Inst<"v_cvt_scalef32_pk8_fp4_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_I32_V8F32_F32>, int_amdgcn_cvt_scalef32_pk8_fp4_f32>; + defm V_CVT_SCALEF32_PK8_FP4_F16 : VOP3Inst<"v_cvt_scalef32_pk8_fp4_f16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_I32_V8F16_F32>, int_amdgcn_cvt_scalef32_pk8_fp4_f16>; + defm V_CVT_SCALEF32_PK8_FP4_BF16 : VOP3Inst<"v_cvt_scalef32_pk8_fp4_bf16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_I32_V8BF16_F32>, int_amdgcn_cvt_scalef32_pk8_fp4_bf16>; + } // End WaveSizePredicate = isWave32 + defm V_CVT_SCALEF32_PK16_FP6_F32 : VOP3Inst<"v_cvt_scalef32_pk16_fp6_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16F32_F32>, int_amdgcn_cvt_scalef32_pk16_fp6_f32>; + defm V_CVT_SCALEF32_PK16_BF6_F32 : VOP3Inst<"v_cvt_scalef32_pk16_bf6_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16F32_F32>, int_amdgcn_cvt_scalef32_pk16_bf6_f32>; + defm V_CVT_SCALEF32_PK16_FP6_F16 : VOP3Inst<"v_cvt_scalef32_pk16_fp6_f16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16F16_F32>, int_amdgcn_cvt_scalef32_pk16_fp6_f16>; + defm V_CVT_SCALEF32_PK16_BF6_F16 : VOP3Inst<"v_cvt_scalef32_pk16_bf6_f16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16F16_F32>, int_amdgcn_cvt_scalef32_pk16_bf6_f16>; + defm V_CVT_SCALEF32_PK16_FP6_BF16 : VOP3Inst<"v_cvt_scalef32_pk16_fp6_bf16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16BF16_F32>, int_amdgcn_cvt_scalef32_pk16_fp6_bf16>; + defm V_CVT_SCALEF32_PK16_BF6_BF16 : VOP3Inst<"v_cvt_scalef32_pk16_bf6_bf16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16BF16_F32>, int_amdgcn_cvt_scalef32_pk16_bf6_bf16>; + + let WaveSizePredicate = isWave32 in { + defm V_CVT_SCALEF32_SR_PK8_FP8_BF16 : VOP3Inst<"v_cvt_scalef32_sr_pk8_fp8_bf16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8BF16_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk8_fp8_bf16>; + defm V_CVT_SCALEF32_SR_PK8_BF8_BF16 : VOP3Inst<"v_cvt_scalef32_sr_pk8_bf8_bf16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8BF16_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk8_bf8_bf16>; + defm V_CVT_SCALEF32_SR_PK8_FP8_F16 : VOP3Inst<"v_cvt_scalef32_sr_pk8_fp8_f16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8F16_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk8_fp8_f16>; + defm V_CVT_SCALEF32_SR_PK8_BF8_F16 : VOP3Inst<"v_cvt_scalef32_sr_pk8_bf8_f16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8F16_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk8_bf8_f16>; + defm V_CVT_SCALEF32_SR_PK8_FP8_F32 : VOP3Inst<"v_cvt_scalef32_sr_pk8_fp8_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8F32_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk8_fp8_f32>; + defm V_CVT_SCALEF32_SR_PK8_BF8_F32 : VOP3Inst<"v_cvt_scalef32_sr_pk8_bf8_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V2I32_V8F32_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk8_bf8_f32>; + defm V_CVT_SCALEF32_SR_PK8_FP4_F32 : VOP3Inst<"v_cvt_scalef32_sr_pk8_fp4_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_I32_V8F32_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk8_fp4_f32>; + defm V_CVT_SCALEF32_SR_PK8_FP4_F16 : VOP3Inst<"v_cvt_scalef32_sr_pk8_fp4_f16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_I32_V8F16_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk8_fp4_f16>; + defm V_CVT_SCALEF32_SR_PK8_FP4_BF16 : VOP3Inst<"v_cvt_scalef32_sr_pk8_fp4_bf16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_I32_V8BF16_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk8_fp4_bf16>; + } // End WaveSizePredicate = isWave32 + defm V_CVT_SCALEF32_SR_PK16_BF6_BF16 : VOP3Inst<"v_cvt_scalef32_sr_pk16_bf6_bf16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16BF16_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk16_bf6_bf16>; + defm V_CVT_SCALEF32_SR_PK16_BF6_F16 : VOP3Inst<"v_cvt_scalef32_sr_pk16_bf6_f16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16F16_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk16_bf6_f16>; + defm V_CVT_SCALEF32_SR_PK16_BF6_F32 : VOP3Inst<"v_cvt_scalef32_sr_pk16_bf6_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16F32_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk16_bf6_f32>; + defm V_CVT_SCALEF32_SR_PK16_FP6_BF16 : VOP3Inst<"v_cvt_scalef32_sr_pk16_fp6_bf16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16BF16_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk16_fp6_bf16>; + defm V_CVT_SCALEF32_SR_PK16_FP6_F16 : VOP3Inst<"v_cvt_scalef32_sr_pk16_fp6_f16", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16F16_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk16_fp6_f16>; + defm V_CVT_SCALEF32_SR_PK16_FP6_F32 : VOP3Inst<"v_cvt_scalef32_sr_pk16_fp6_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V3I32_V16F32_I32_F32>, int_amdgcn_cvt_scalef32_sr_pk16_fp6_f32>; + } // End Constraints = "@earlyclobber $vdst" + let True16Predicate = UseRealTrue16Insts in { def : Cvt_SR_F8_ByteSel_Pat<int_amdgcn_cvt_sr_fp8_f16, V_CVT_SR_FP8_F16_t16_e64, f16>; def : Cvt_SR_F8_ByteSel_Pat<int_amdgcn_cvt_sr_bf8_f16, V_CVT_SR_BF8_F16_t16_e64, f16>; @@ -1788,6 +1838,12 @@ let SubtargetPredicate = isGFX1250Plus in { } } // End SubtargetPredicate = isGFX1250Plus +let SubtargetPredicate = HasTensorCvtLutInsts in { + defm V_PERM_PK16_B4_U4 : VOP3Inst<"v_perm_pk16_b4_u4", VOP3_V2I32_I32_I32_V2I32, int_amdgcn_perm_pk16_b4_u4>; + defm V_PERM_PK16_B6_U4 : VOP3Inst<"v_perm_pk16_b6_u4", VOP3_V3I32_I32_I64_V2I32, int_amdgcn_perm_pk16_b6_u4>; + defm V_PERM_PK16_B8_U4 : VOP3Inst<"v_perm_pk16_b8_u4", VOP3_V4I32_I64_I64_V2I32, int_amdgcn_perm_pk16_b8_u4>; +} // End SubtargetPredicate = HasTensorCvtLutInsts + class Cvt_Scale_Sr_F32ToBF16F16_Pat<SDPatternOperator node, VOP3_Pseudo inst, ValueType DstTy> : GCNPat< (DstTy (node DstTy:$vdst_in, f32:$src0, i32:$src1, timm:$word_sel)), (inst (DstSelToOpSelXForm $word_sel), $src0, 0, $src1, VGPR_32:$vdst_in) @@ -2186,6 +2242,9 @@ let AssemblerPredicate = isGFX11Plus in { } // These instructions differ from GFX12 variant by supporting DPP: +defm V_PERM_PK16_B4_U4 : VOP3Only_Real_Base_gfx1250<0x23f>; +defm V_PERM_PK16_B6_U4 : VOP3Only_Real_Base_gfx1250<0x242>; +defm V_PERM_PK16_B8_U4 : VOP3Only_Real_Base_gfx1250<0x243>; defm V_LSHL_ADD_U64 : VOP3Only_Realtriple_gfx1250<0x252>; defm V_ASHR_PK_I8_I32 : VOP3Only_Realtriple_gfx1250<0x290>; defm V_ASHR_PK_U8_I32 : VOP3Only_Realtriple_gfx1250<0x291>; @@ -2198,6 +2257,42 @@ defm V_CVT_SCALE_PK8_F32_FP8 : VOP3Only_ScaleSel_Real_gfx1250<0x2aa>; defm V_CVT_SCALE_PK8_F16_BF8 : VOP3Only_ScaleSel_Real_gfx1250<0x2ab>; defm V_CVT_SCALE_PK8_BF16_BF8 : VOP3Only_ScaleSel_Real_gfx1250<0x2ac>; defm V_CVT_SCALE_PK8_F32_BF8 : VOP3Only_ScaleSel_Real_gfx1250<0x2ad>; +defm V_CVT_SCALEF32_PK8_FP4_F32 : VOP3Only_Real_Base_gfx1250<0x2b0>; +defm V_CVT_SCALEF32_PK8_FP4_F16 : VOP3Only_Real_Base_gfx1250<0x2b3>; +defm V_CVT_SCALEF32_PK8_FP8_BF16 : VOP3Only_Real_Base_gfx1250<0x2b4>; +defm V_CVT_SCALEF32_PK8_BF8_BF16 : VOP3Only_Real_Base_gfx1250<0x2b5>; +defm V_CVT_SCALEF32_PK8_FP4_BF16 : VOP3Only_Real_Base_gfx1250<0x2b8>; +defm V_CVT_SCALEF32_PK8_FP8_F32 : VOP3Only_Real_Base_gfx1250<0x2c3>; +defm V_CVT_SCALEF32_PK8_FP8_F16 : VOP3Only_Real_Base_gfx1250<0x2c4>; +defm V_CVT_SCALEF32_PK8_BF8_F32 : VOP3Only_Real_Base_gfx1250<0x2c5>; +defm V_CVT_SCALEF32_PK8_BF8_F16 : VOP3Only_Real_Base_gfx1250<0x2c6>; +defm V_CVT_SCALE_PK16_F16_FP6 : VOP3Only_ScaleSel_Real_gfx1250<0x2c7>; +defm V_CVT_SCALE_PK16_BF16_FP6 : VOP3Only_ScaleSel_Real_gfx1250<0x2c8>; +defm V_CVT_SCALE_PK16_F32_FP6 : VOP3Only_ScaleSel_Real_gfx1250<0x2c9>; +defm V_CVT_SCALE_PK16_F16_BF6 : VOP3Only_ScaleSel_Real_gfx1250<0x2ca>; +defm V_CVT_SCALE_PK16_BF16_BF6 : VOP3Only_ScaleSel_Real_gfx1250<0x2cb>; +defm V_CVT_SCALE_PK16_F32_BF6 : VOP3Only_ScaleSel_Real_gfx1250<0x2cc>; +defm V_CVT_SCALEF32_PK16_FP6_F32 : VOP3Only_Real_Base_gfx1250<0x2cd>; +defm V_CVT_SCALEF32_PK16_BF6_F32 : VOP3Only_Real_Base_gfx1250<0x2ce>; +defm V_CVT_SCALEF32_PK16_FP6_F16 : VOP3Only_Real_Base_gfx1250<0x2cf>; +defm V_CVT_SCALEF32_PK16_BF6_F16 : VOP3Only_Real_Base_gfx1250<0x2d0>; +defm V_CVT_SCALEF32_PK16_FP6_BF16 : VOP3Only_Real_Base_gfx1250<0x2d1>; +defm V_CVT_SCALEF32_PK16_BF6_BF16 : VOP3Only_Real_Base_gfx1250<0x2d2>; +defm V_CVT_SCALEF32_SR_PK16_FP6_F32 : VOP3Only_Real_Base_gfx1250<0x2d3>; +defm V_CVT_SCALEF32_SR_PK16_BF6_F32 : VOP3Only_Real_Base_gfx1250<0x2d4>; +defm V_CVT_SCALEF32_SR_PK16_FP6_F16 : VOP3Only_Real_Base_gfx1250<0x2d5>; +defm V_CVT_SCALEF32_SR_PK16_BF6_F16 : VOP3Only_Real_Base_gfx1250<0x2d6>; +defm V_CVT_SCALEF32_SR_PK16_FP6_BF16 : VOP3Only_Real_Base_gfx1250<0x2d7>; +defm V_CVT_SCALEF32_SR_PK16_BF6_BF16 : VOP3Only_Real_Base_gfx1250<0x2d8>; +defm V_CVT_SCALEF32_SR_PK8_FP4_F32 : VOP3Only_Real_Base_gfx1250<0x297>; +defm V_CVT_SCALEF32_SR_PK8_FP8_F32 : VOP3Only_Real_Base_gfx1250<0x298>; +defm V_CVT_SCALEF32_SR_PK8_BF8_F32 : VOP3Only_Real_Base_gfx1250<0x299>; +defm V_CVT_SCALEF32_SR_PK8_FP4_F16 : VOP3Only_Real_Base_gfx1250<0x2b9>; +defm V_CVT_SCALEF32_SR_PK8_FP4_BF16 : VOP3Only_Real_Base_gfx1250<0x2bc>; +defm V_CVT_SCALEF32_SR_PK8_FP8_F16 : VOP3Only_Real_Base_gfx1250<0x2bf>; +defm V_CVT_SCALEF32_SR_PK8_FP8_BF16 : VOP3Only_Real_Base_gfx1250<0x2c0>; +defm V_CVT_SCALEF32_SR_PK8_BF8_F16 : VOP3Only_Real_Base_gfx1250<0x2c1>; +defm V_CVT_SCALEF32_SR_PK8_BF8_BF16 : VOP3Only_Real_Base_gfx1250<0x2c2>; defm V_CVT_PK_BF16_F32 : VOP3Only_Realtriple_gfx1250<0x36d>; defm V_CVT_SR_PK_BF16_F32 : VOP3Only_Realtriple_gfx1250<0x36e>; defm V_CVT_PK_F16_F32 : VOP3Only_Realtriple_gfx1250<0x36f>; diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index dfa3de3c..c221d22 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -1108,9 +1108,8 @@ std::optional<bool> ARMAsmBackend::evaluateFixup(const MCFragment &F, } void ARMAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { if (IsResolved && shouldForceRelocation(Fixup, Target)) IsResolved = false; maybeAddReloc(F, Fixup, Target, Value, IsResolved); @@ -1124,14 +1123,15 @@ void ARMAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, return; // Doesn't change encoding. const unsigned NumBytes = getFixupKindNumBytes(Kind); - unsigned Offset = Fixup.getOffset(); - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); // Used to point to big endian bytes. unsigned FullSizeBytes; if (Endian == llvm::endianness::big) { FullSizeBytes = getFixupKindContainerSizeBytes(Kind); - assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!"); + assert(Fixup.getOffset() + FullSizeBytes <= F.getSize() && + "Invalid fixup size!"); assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); } @@ -1141,7 +1141,7 @@ void ARMAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, for (unsigned i = 0; i != NumBytes; ++i) { unsigned Idx = Endian == llvm::endianness::little ? i : (FullSizeBytes - 1 - i); - Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); + Data[Idx] |= uint8_t((Value >> (i * 8)) & 0xff); } } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h index 07d2cf7..2844232 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -40,8 +40,7 @@ public: std::optional<bool> evaluateFixup(const MCFragment &, MCFixup &, MCValue &, uint64_t &) override; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const; diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp index 38444f9..05a7d03 100644 --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp @@ -368,9 +368,8 @@ AVRAsmBackend::createObjectTargetWriter() const { } void AVRAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { // AVR sets the fixup value to bypass the assembly time overflow with a // relocation. if (IsResolved) { @@ -397,14 +396,14 @@ void AVRAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // Shift the value into position. Value <<= Info.TargetOffset; - unsigned Offset = Fixup.getOffset(); - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); // For each byte of the fragment that the fixup touches, mask in the // bits from the fixup value. for (unsigned i = 0; i < NumBytes; ++i) { uint8_t mask = (((Value >> (i * 8)) & 0xff)); - Data[Offset + i] |= mask; + Data[i] |= mask; } } diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h index 68c839e..9633669 100644 --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h @@ -38,8 +38,7 @@ public: createObjectTargetWriter() const override; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; std::optional<MCFixupKind> getFixupKind(StringRef Name) const override; MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override; diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp index dda8753..53933f9 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp @@ -27,8 +27,7 @@ public: ~BPFAsmBackend() override = default; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; std::unique_ptr<MCObjectTargetWriter> createObjectTargetWriter() const override; @@ -66,35 +65,32 @@ bool BPFAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, } void BPFAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { maybeAddReloc(F, Fixup, Target, Value, IsResolved); if (Fixup.getKind() == FK_SecRel_8) { // The Value is 0 for global variables, and the in-section offset // for static variables. Write to the immediate field of the inst. assert(Value <= UINT32_MAX); - support::endian::write<uint32_t>(&Data[Fixup.getOffset() + 4], - static_cast<uint32_t>(Value), + support::endian::write<uint32_t>(Data + 4, static_cast<uint32_t>(Value), Endian); } else if (Fixup.getKind() == FK_Data_4 && !Fixup.isPCRel()) { - support::endian::write<uint32_t>(&Data[Fixup.getOffset()], Value, Endian); + support::endian::write<uint32_t>(Data, Value, Endian); } else if (Fixup.getKind() == FK_Data_8) { - support::endian::write<uint64_t>(&Data[Fixup.getOffset()], Value, Endian); + support::endian::write<uint64_t>(Data, Value, Endian); } else if (Fixup.getKind() == FK_Data_4 && Fixup.isPCRel()) { Value = (uint32_t)((Value - 8) / 8); if (Endian == llvm::endianness::little) { - Data[Fixup.getOffset() + 1] = 0x10; - support::endian::write32le(&Data[Fixup.getOffset() + 4], Value); + Data[1] = 0x10; + support::endian::write32le(Data + 4, Value); } else { - Data[Fixup.getOffset() + 1] = 0x1; - support::endian::write32be(&Data[Fixup.getOffset() + 4], Value); + Data[1] = 0x1; + support::endian::write32be(Data + 4, Value); } } else if (Fixup.getKind() == BPF::FK_BPF_PCRel_4) { // The input Value represents the number of bytes. Value = (uint32_t)((Value - 8) / 8); - support::endian::write<uint32_t>(&Data[Fixup.getOffset() + 4], Value, - Endian); + support::endian::write<uint32_t>(Data + 4, Value, Endian); } else { assert(Fixup.getKind() == FK_Data_2 && Fixup.isPCRel()); @@ -103,8 +99,7 @@ void BPFAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, report_fatal_error("Branch target out of insn range"); Value = (uint16_t)((Value - 8) / 8); - support::endian::write<uint16_t>(&Data[Fixup.getOffset() + 2], Value, - Endian); + support::endian::write<uint16_t>(Data + 2, Value, Endian); } } diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp index 1bd82fad..6964998 100644 --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp @@ -197,9 +197,8 @@ std::optional<bool> CSKYAsmBackend::evaluateFixup(const MCFragment &F, } void CSKYAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { if (IsResolved && shouldForceRelocation(Fixup, Target)) IsResolved = false; maybeAddReloc(F, Fixup, Target, Value, IsResolved); @@ -217,10 +216,10 @@ void CSKYAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // Shift the value into position. Value <<= Info.TargetOffset; - unsigned Offset = Fixup.getOffset(); unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8; - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); // For each byte of the fragment that the fixup touches, mask in the // bits from the fixup value. @@ -228,14 +227,14 @@ void CSKYAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, bool IsInstFixup = (Kind >= FirstTargetFixupKind); if (IsLittleEndian && IsInstFixup && (NumBytes == 4)) { - Data[Offset + 0] |= uint8_t((Value >> 16) & 0xff); - Data[Offset + 1] |= uint8_t((Value >> 24) & 0xff); - Data[Offset + 2] |= uint8_t(Value & 0xff); - Data[Offset + 3] |= uint8_t((Value >> 8) & 0xff); + Data[0] |= uint8_t((Value >> 16) & 0xff); + Data[1] |= uint8_t((Value >> 24) & 0xff); + Data[2] |= uint8_t(Value & 0xff); + Data[3] |= uint8_t((Value >> 8) & 0xff); } else { for (unsigned I = 0; I != NumBytes; I++) { unsigned Idx = IsLittleEndian ? I : (NumBytes - 1 - I); - Data[Offset + Idx] |= uint8_t((Value >> (I * 8)) & 0xff); + Data[Idx] |= uint8_t((Value >> (I * 8)) & 0xff); } } } diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h index 1c8516f..5d8826a 100644 --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h @@ -25,8 +25,7 @@ public: std::optional<bool> evaluateFixup(const MCFragment &, MCFixup &, MCValue &, uint64_t &) override; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override; diff --git a/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp b/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp index 5323be6..9a14c01 100644 --- a/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp +++ b/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp @@ -78,8 +78,7 @@ public: ~DXILAsmBackend() override = default; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override {} + uint8_t *Data, uint64_t Value, bool IsResolved) override {} std::unique_ptr<MCObjectTargetWriter> createObjectTargetWriter() const override { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index d5b7a75..1a0f1ab 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -402,8 +402,7 @@ public: } void applyFixup(const MCFragment &, const MCFixup &, const MCValue &, - MutableArrayRef<char> Data, uint64_t FixupValue, - bool IsResolved) override; + uint8_t *Data, uint64_t FixupValue, bool IsResolved) override; bool isInstRelaxable(MCInst const &HMI) const { const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); @@ -649,8 +648,7 @@ public: } // namespace void HexagonAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, + const MCValue &Target, uint8_t *InstAddr, uint64_t FixupValue, bool IsResolved) { if (IsResolved && shouldForceRelocation(Fixup)) IsResolved = false; @@ -667,10 +665,9 @@ void HexagonAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // LLVM gives us an encoded value, we have to convert it back // to a real offset before we can use it. - uint32_t Offset = Fixup.getOffset(); unsigned NumBytes = getFixupKindNumBytes(Kind); - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); - char *InstAddr = Data.data() + Offset; + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); Value = adjustFixupValue(Kind, FixupValue); if (!Value) @@ -757,8 +754,8 @@ void HexagonAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x"; - dbgs().write_hex(FixupValue) - << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x"; + dbgs().write_hex(FixupValue) << ": Offset=" << Fixup.getOffset() + << ": Size=" << F.getSize() << ": OInst=0x"; dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc);); // For each byte of the fragment that the fixup touches, mask in the diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp index 83d1697..3112dea 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp @@ -48,8 +48,7 @@ public: : MCAsmBackend(llvm::endianness::big), OSType(OST) {} void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; std::unique_ptr<MCObjectTargetWriter> createObjectTargetWriter() const override; @@ -72,9 +71,8 @@ bool LanaiAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, } void LanaiAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { if (!IsResolved) Asm->getWriter().recordRelocation(F, Fixup, Target, Value); @@ -85,7 +83,6 @@ void LanaiAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // Where in the object and where the number of bytes that need // fixing up - unsigned Offset = Fixup.getOffset(); unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; unsigned FullSize = 4; @@ -95,8 +92,7 @@ void LanaiAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // Load instruction and apply value for (unsigned i = 0; i != NumBytes; ++i) { unsigned Idx = (FullSize - 1 - i); - CurVal |= static_cast<uint64_t>(static_cast<uint8_t>(Data[Offset + Idx])) - << (i * 8); + CurVal |= static_cast<uint64_t>(static_cast<uint8_t>(Data[Idx])) << (i * 8); } uint64_t Mask = @@ -106,7 +102,7 @@ void LanaiAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // Write out the fixed up bytes back to the code/data bits. for (unsigned i = 0; i != NumBytes; ++i) { unsigned Idx = (FullSize - 1 - i); - Data[Offset + Idx] = static_cast<uint8_t>((CurVal >> (i * 8)) & 0xff); + Data[Idx] = static_cast<uint8_t>((CurVal >> (i * 8)) & 0xff); } } diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp index 858f3d0..fda9d97 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp @@ -131,19 +131,18 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, } } -static void fixupLeb128(MCContext &Ctx, const MCFixup &Fixup, - MutableArrayRef<char> Data, uint64_t Value) { +static void fixupLeb128(MCContext &Ctx, const MCFixup &Fixup, uint8_t *Data, + uint64_t Value) { unsigned I; - for (I = 0; I != Data.size() && Value; ++I, Value >>= 7) + for (I = 0; Value; ++I, Value >>= 7) Data[I] |= uint8_t(Value & 0x7f); if (Value) Ctx.reportError(Fixup.getLoc(), "Invalid uleb128 value!"); } void LoongArchAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { if (IsResolved && shouldForceRelocation(Fixup, Target)) IsResolved = false; IsResolved = addReloc(F, Fixup, Target, Value, IsResolved); @@ -166,14 +165,14 @@ void LoongArchAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // Shift the value into position. Value <<= Info.TargetOffset; - unsigned Offset = Fixup.getOffset(); unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8; - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); // For each byte of the fragment that the fixup touches, mask in the // bits from the fixup value. for (unsigned I = 0; I != NumBytes; ++I) { - Data[Offset + I] |= uint8_t((Value >> (I * 8)) & 0xff); + Data[I] |= uint8_t((Value >> (I * 8)) & 0xff); } } @@ -274,15 +273,14 @@ bool LoongArchAsmBackend::relaxDwarfLineAddr(MCFragment &F, int64_t LineDelta = F.getDwarfLineDelta(); const MCExpr &AddrDelta = F.getDwarfAddrDelta(); - SmallVector<MCFixup, 1> Fixups; size_t OldSize = F.getVarSize(); int64_t Value; if (AddrDelta.evaluateAsAbsolute(Value, *Asm)) return false; - bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, *Asm); - assert(IsAbsolute && "CFA with invalid expression"); - (void)IsAbsolute; + [[maybe_unused]] bool IsAbsolute = + AddrDelta.evaluateKnownAbsolute(Value, *Asm); + assert(IsAbsolute); SmallVector<char> Data; raw_svector_ostream OS(Data); @@ -293,33 +291,23 @@ bool LoongArchAsmBackend::relaxDwarfLineAddr(MCFragment &F, encodeSLEB128(LineDelta, OS); } - unsigned Offset; - std::pair<MCFixupKind, MCFixupKind> FK; - // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode // takes a single unsigned half (unencoded) operand. The maximum encodable // value is therefore 65535. Set a conservative upper bound for relaxation. + unsigned PCBytes; if (Value > 60000) { unsigned PtrSize = C.getAsmInfo()->getCodePointerSize(); - - OS << uint8_t(dwarf::DW_LNS_extended_op); - encodeULEB128(PtrSize + 1, OS); - - OS << uint8_t(dwarf::DW_LNE_set_address); - Offset = OS.tell(); assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size"); - FK = getRelocPairForSize(PtrSize == 4 ? 32 : 64); + PCBytes = PtrSize; + OS << uint8_t(dwarf::DW_LNS_extended_op) << uint8_t(PtrSize + 1) + << uint8_t(dwarf::DW_LNE_set_address); OS.write_zeros(PtrSize); } else { + PCBytes = 2; OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc); - Offset = OS.tell(); - FK = getRelocPairForSize(16); support::endian::write<uint16_t>(OS, 0, llvm::endianness::little); } - - const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta); - Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(FK))); - Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(FK))); + auto Offset = OS.tell() - PCBytes; if (LineDelta == INT64_MAX) { OS << uint8_t(dwarf::DW_LNS_extended_op); @@ -330,7 +318,8 @@ bool LoongArchAsmBackend::relaxDwarfLineAddr(MCFragment &F, } F.setVarContents(Data); - F.setVarFixups(Fixups); + F.setVarFixups({MCFixup::create(Offset, &AddrDelta, + MCFixup::getDataKindForSize(PCBytes))}); WasRelaxed = OldSize != Data.size(); return true; } diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h index 3d929fc..1f13601 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h @@ -42,8 +42,7 @@ public: uint64_t &FixedValue, bool IsResolved); void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; bool shouldForceRelocation(const MCFixup &Fixup, const MCValue &Target); diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp index 7ef705d..fe83dc6 100644 --- a/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp +++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp @@ -53,8 +53,7 @@ public: .Default(false)) {} void applyFixup(const MCFragment &, const MCFixup &, const MCValue &, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; bool mayNeedRelaxation(unsigned Opcode, ArrayRef<MCOperand> Operands, const MCSubtargetInfo &STI) const override; @@ -78,9 +77,8 @@ public: } // end anonymous namespace void M68kAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { if (!IsResolved) Asm->getWriter().recordRelocation(F, Fixup, Target, Value); @@ -95,8 +93,7 @@ void M68kAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // Write in Big Endian for (unsigned i = 0; i != Size; ++i) - Data[Fixup.getOffset() + i] = - uint8_t(static_cast<int64_t>(Value) >> ((Size - i - 1) * 8)); + Data[i] = uint8_t(static_cast<int64_t>(Value) >> ((Size - i - 1) * 8)); } /// cc—Carry clear GE—Greater than or equal diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp index b513503..d892b3a 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp @@ -36,8 +36,7 @@ public: ~MSP430AsmBackend() override = default; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; std::unique_ptr<MCObjectTargetWriter> createObjectTargetWriter() const override { @@ -105,9 +104,8 @@ uint64_t MSP430AsmBackend::adjustFixupValue(const MCFixup &Fixup, } void MSP430AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { maybeAddReloc(F, Fixup, Target, Value, IsResolved); Value = adjustFixupValue(Fixup, Value, getContext()); MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind()); @@ -117,15 +115,14 @@ void MSP430AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // Shift the value into position. Value <<= Info.TargetOffset; - unsigned Offset = Fixup.getOffset(); unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8; - - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); // For each byte of the fragment that the fixup touches, mask in the // bits from the fixup value. for (unsigned i = 0; i != NumBytes; ++i) { - Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); + Data[i] |= uint8_t((Value >> (i * 8)) & 0xff); } } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index c2169be..33aab71 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -283,9 +283,8 @@ static bool shouldForceRelocation(const MCFixup &Fixup) { /// data fragment, at the offset specified by the fixup and following the /// fixup kind as appropriate. void MipsAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { if (shouldForceRelocation(Fixup)) IsResolved = false; maybeAddReloc(F, Fixup, Target, Value, IsResolved); @@ -297,7 +296,6 @@ void MipsAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, return; // Doesn't change encoding. // Where do we start in the object - unsigned Offset = Fixup.getOffset(); // Number of bytes we need to fixup unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; // Used to point to big endian bytes @@ -328,7 +326,7 @@ void MipsAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, unsigned Idx = Endian == llvm::endianness::little ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i) : (FullSize - 1 - i); - CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); + CurVal |= (uint64_t)((uint8_t)Data[Idx]) << (i * 8); } uint64_t Mask = ((uint64_t)(-1) >> @@ -340,7 +338,7 @@ void MipsAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, unsigned Idx = Endian == llvm::endianness::little ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i) : (FullSize - 1 - i); - Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); + Data[Idx] = (uint8_t)((CurVal >> (i * 8)) & 0xff); } } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h index 816626d..40b5853 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -40,8 +40,7 @@ public: createObjectTargetWriter() const override; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; std::optional<MCFixupKind> getFixupKind(StringRef Name) const override; MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp index d9680c7..7a8395a 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -1034,12 +1034,14 @@ MCELFStreamer &MipsTargetELFStreamer::getStreamer() { void MipsTargetELFStreamer::emitGPRel32Value(const MCExpr *Value) { auto &S = getStreamer(); + S.ensureHeadroom(4); S.addFixup(Value, Mips::fixup_Mips_GPREL32); S.appendContents(4, 0); } void MipsTargetELFStreamer::emitGPRel64Value(const MCExpr *Value) { auto &S = getStreamer(); + S.ensureHeadroom(8); // fixup_Mips_GPREL32 desginates R_MIPS_GPREL32+R_MIPS_64 on MIPS64. S.addFixup(Value, Mips::fixup_Mips_GPREL32); S.appendContents(8, 0); @@ -1047,24 +1049,28 @@ void MipsTargetELFStreamer::emitGPRel64Value(const MCExpr *Value) { void MipsTargetELFStreamer::emitDTPRel32Value(const MCExpr *Value) { auto &S = getStreamer(); + S.ensureHeadroom(4); S.addFixup(Value, Mips::fixup_Mips_DTPREL32); S.appendContents(4, 0); } void MipsTargetELFStreamer::emitDTPRel64Value(const MCExpr *Value) { auto &S = getStreamer(); + S.ensureHeadroom(8); S.addFixup(Value, Mips::fixup_Mips_DTPREL64); S.appendContents(8, 0); } void MipsTargetELFStreamer::emitTPRel32Value(const MCExpr *Value) { auto &S = getStreamer(); + S.ensureHeadroom(4); S.addFixup(Value, Mips::fixup_Mips_TPREL32); S.appendContents(4, 0); } void MipsTargetELFStreamer::emitTPRel64Value(const MCExpr *Value) { auto &S = getStreamer(); + S.ensureHeadroom(8); S.addFixup(Value, Mips::fixup_Mips_TPREL64); S.appendContents(8, 0); } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index 0e8828f..ec97e2e 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -93,8 +93,8 @@ public: MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override; void applyFixup(const MCFragment &, const MCFixup &Fixup, - const MCValue &Target, MutableArrayRef<char> Data, - uint64_t Value, bool IsResolved) override; + const MCValue &Target, uint8_t *Data, uint64_t Value, + bool IsResolved) override; bool shouldForceRelocation(const MCFixup &Fixup, const MCValue &Target) { // If there is a @ specifier, unless it is optimized out (e.g. constant @l), @@ -185,9 +185,8 @@ MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { } void PPCAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &TargetVal, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &TargetVal, uint8_t *Data, + uint64_t Value, bool IsResolved) { // In PPC64 ELFv1, .quad .TOC.@tocbase in the .opd section is expected to // reference the null symbol. auto Target = TargetVal; @@ -205,7 +204,6 @@ void PPCAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, if (!Value) return; // Doesn't change encoding. - unsigned Offset = Fixup.getOffset(); unsigned NumBytes = getFixupKindNumBytes(Kind); // For each byte of the fragment that the fixup touches, mask in the bits @@ -213,7 +211,7 @@ void PPCAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // bitfields above. for (unsigned i = 0; i != NumBytes; ++i) { unsigned Idx = Endian == llvm::endianness::little ? i : (NumBytes - 1 - i); - Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff); + Data[i] |= uint8_t((Value >> (Idx * 8)) & 0xff); } } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index 9538b20..eb7460e 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -327,19 +327,19 @@ bool RISCVAsmBackend::relaxAlign(MCFragment &F, unsigned &Size) { bool RISCVAsmBackend::relaxDwarfLineAddr(MCFragment &F, bool &WasRelaxed) const { - MCContext &C = getContext(); - int64_t LineDelta = F.getDwarfLineDelta(); const MCExpr &AddrDelta = F.getDwarfAddrDelta(); - SmallVector<MCFixup, 1> Fixups; size_t OldSize = F.getVarSize(); int64_t Value; + // If the label difference can be resolved, use the default handling, which + // utilizes a shorter special opcode. + if (AddrDelta.evaluateAsAbsolute(Value, *Asm)) + return false; [[maybe_unused]] bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, *Asm); assert(IsAbsolute && "CFA with invalid expression"); - Fixups.clear(); SmallVector<char> Data; raw_svector_ostream OS(Data); @@ -349,33 +349,21 @@ bool RISCVAsmBackend::relaxDwarfLineAddr(MCFragment &F, encodeSLEB128(LineDelta, OS); } - unsigned Offset; - std::pair<MCFixupKind, MCFixupKind> Fixup; - // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode // takes a single unsigned half (unencoded) operand. The maximum encodable // value is therefore 65535. Set a conservative upper bound for relaxation. + unsigned PCBytes; if (Value > 60000) { - unsigned PtrSize = C.getAsmInfo()->getCodePointerSize(); - - OS << uint8_t(dwarf::DW_LNS_extended_op); - encodeULEB128(PtrSize + 1, OS); - - OS << uint8_t(dwarf::DW_LNE_set_address); - Offset = OS.tell(); - assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size"); - Fixup = RISCV::getRelocPairForSize(PtrSize); - OS.write_zeros(PtrSize); + PCBytes = getContext().getAsmInfo()->getCodePointerSize(); + OS << uint8_t(dwarf::DW_LNS_extended_op) << uint8_t(PCBytes + 1) + << uint8_t(dwarf::DW_LNE_set_address); + OS.write_zeros(PCBytes); } else { + PCBytes = 2; OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc); - Offset = OS.tell(); - Fixup = RISCV::getRelocPairForSize(2); support::endian::write<uint16_t>(OS, 0, llvm::endianness::little); } - - const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta); - Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(Fixup))); - Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(Fixup))); + auto Offset = OS.tell() - PCBytes; if (LineDelta == INT64_MAX) { OS << uint8_t(dwarf::DW_LNS_extended_op); @@ -386,7 +374,8 @@ bool RISCVAsmBackend::relaxDwarfLineAddr(MCFragment &F, } F.setVarContents(Data); - F.setVarFixups(Fixups); + F.setVarFixups({MCFixup::create(Offset, &AddrDelta, + MCFixup::getDataKindForSize(PCBytes))}); WasRelaxed = OldSize != Data.size(); return true; } @@ -881,9 +870,8 @@ bool RISCVAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup, } void RISCVAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { IsResolved = addReloc(F, Fixup, Target, Value, IsResolved); MCFixupKind Kind = Fixup.getKind(); if (mc::isRelocation(Kind)) @@ -898,15 +886,14 @@ void RISCVAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, // Shift the value into position. Value <<= Info.TargetOffset; - unsigned Offset = Fixup.getOffset(); unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8; - - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); // For each byte of the fragment that the fixup touches, mask in the // bits from the fixup value. for (unsigned i = 0; i != NumBytes; ++i) { - Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); + Data[i] |= uint8_t((Value >> (i * 8)) & 0xff); } } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h index d97d632..adec1ec 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h @@ -46,8 +46,7 @@ public: void maybeAddVendorReloc(const MCFragment &, const MCFixup &); void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; std::unique_ptr<MCObjectTargetWriter> createObjectTargetWriter() const override; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h index f816561c..98c8738 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h @@ -68,27 +68,6 @@ enum Fixups { fixup_riscv_invalid, NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind }; - -static inline std::pair<MCFixupKind, MCFixupKind> -getRelocPairForSize(unsigned Size) { - switch (Size) { - default: - llvm_unreachable("unsupported fixup size"); - case 1: - return std::make_pair(FirstLiteralRelocationKind + ELF::R_RISCV_ADD8, - FirstLiteralRelocationKind + ELF::R_RISCV_SUB8); - case 2: - return std::make_pair(FirstLiteralRelocationKind + ELF::R_RISCV_ADD16, - FirstLiteralRelocationKind + ELF::R_RISCV_SUB16); - case 4: - return std::make_pair(FirstLiteralRelocationKind + ELF::R_RISCV_ADD32, - FirstLiteralRelocationKind + ELF::R_RISCV_SUB32); - case 8: - return std::make_pair(FirstLiteralRelocationKind + ELF::R_RISCV_ADD64, - FirstLiteralRelocationKind + ELF::R_RISCV_SUB64); - } -} - } // end namespace llvm::RISCV #endif diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td index a250ac8..5a5a9ed 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -206,8 +206,6 @@ let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in { //===----------------------------------------------------------------------===// defvar I32IntegerVectors = !filter(vti, AllIntegerVectors, !eq(vti.SEW, 32)); -defvar I32I64IntegerVectors = !filter(vti, AllIntegerVectors, - !or(!eq(vti.SEW, 32), !eq(vti.SEW, 64))); class ZvkI32IntegerVectors<string vd_lmul> { list<VTypeInfo> vs2_types = !cond(!eq(vd_lmul, "M8") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 32)), @@ -1126,16 +1124,16 @@ let Predicates = [HasStdExtZvkned] in { defm : VPatUnaryV_S_NoMaskVectorCrypto<"int_riscv_vaesz", "PseudoVAESZ", I32IntegerVectors>; } // Predicates = [HasStdExtZvkned] -let Predicates = [HasStdExtZvknha] in { +let Predicates = [HasStdExtZvknhaOrZvknhb] in { defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I32IntegerVectors>; - defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CH", I32IntegerVectors>; + defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I32IntegerVectors>; defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32IntegerVectors, isSEWAware=true>; } // Predicates = [HasStdExtZvknha] let Predicates = [HasStdExtZvknhb] in { - defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I32I64IntegerVectors>; - defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CH", I32I64IntegerVectors>; - defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32I64IntegerVectors, isSEWAware=true>; + defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I64IntegerVectors>; + defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I64IntegerVectors>; + defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I64IntegerVectors, isSEWAware=true>; } // Predicates = [HasStdExtZvknhb] let Predicates = [HasStdExtZvksed] in { diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp index ef84d43..5710cf2 100644 --- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp +++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp @@ -21,8 +21,7 @@ public: SPIRVAsmBackend(llvm::endianness Endian) : MCAsmBackend(Endian) {} void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override {} + uint8_t *Data, uint64_t Value, bool IsResolved) override {} std::unique_ptr<MCObjectTargetWriter> createObjectTargetWriter() const override { diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index ba023af..bc60842 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -127,8 +127,7 @@ public: std::optional<MCFixupKind> getFixupKind(StringRef Name) const override; MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override { @@ -253,21 +252,19 @@ MCFixupKindInfo SparcAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { } void SparcAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { maybeAddReloc(F, Fixup, Target, Value, IsResolved); if (!IsResolved) return; Value = adjustFixupValue(Fixup.getKind(), Value); unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); - unsigned Offset = Fixup.getOffset(); // For each byte of the fragment that the fixup touches, mask in the // bits from the fixup value. for (unsigned i = 0; i != NumBytes; ++i) { unsigned Idx = Endian == llvm::endianness::little ? i : (NumBytes - 1) - i; - Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); + Data[Idx] |= uint8_t((Value >> (i * 8)) & 0xff); } } diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp index b2cfd04..d692cbe 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp @@ -113,8 +113,7 @@ public: std::optional<MCFixupKind> getFixupKind(StringRef Name) const override; MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override; }; @@ -152,20 +151,18 @@ MCFixupKindInfo SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { } void SystemZMCAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { if (Target.getSpecifier()) IsResolved = false; maybeAddReloc(F, Fixup, Target, Value, IsResolved); MCFixupKind Kind = Fixup.getKind(); if (mc::isRelocation(Kind)) return; - unsigned Offset = Fixup.getOffset(); unsigned BitSize = getFixupKindInfo(Kind).TargetSize; unsigned Size = (BitSize + 7) / 8; - assert(Offset + Size <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + Size <= F.getSize() && "Invalid fixup offset!"); // Big-endian insertion of Size bytes. Value = extractBitsForFixup(Kind, Value, Fixup, getContext()); @@ -173,7 +170,7 @@ void SystemZMCAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, Value &= ((uint64_t)1 << BitSize) - 1; unsigned ShiftValue = (Size * 8) - 8; for (unsigned I = 0; I != Size; ++I) { - Data[Offset + I] |= uint8_t(Value >> ShiftValue); + Data[I] |= uint8_t(Value >> ShiftValue); ShiftValue -= 8; } } diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp index b02b6af..c1b9d9f 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp +++ b/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp @@ -112,8 +112,7 @@ public: } void applyFixup(const MCFragment &, const MCFixup &, const MCValue &, - MutableArrayRef<char>, uint64_t Value, - bool IsResolved) override; + uint8_t *, uint64_t Value, bool IsResolved) override; bool mayNeedRelaxation(unsigned Opcode, ArrayRef<MCOperand> Operands, const MCSubtargetInfo &STI) const override { @@ -152,7 +151,7 @@ public: } // end anonymous namespace void VEAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, MutableArrayRef<char> Data, + const MCValue &Target, uint8_t *Data, uint64_t Value, bool IsResolved) { switch (Fixup.getKind()) { case VE::fixup_ve_tls_gd_hi32: @@ -173,14 +172,14 @@ void VEAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, Value <<= Info.TargetOffset; unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); - unsigned Offset = Fixup.getOffset(); - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); // For each byte of the fragment that the fixup touches, mask in the bits // from the fixup value. The Value has been "split up" into the // appropriate bitfields above. for (unsigned i = 0; i != NumBytes; ++i) { unsigned Idx = Endian == llvm::endianness::little ? i : (NumBytes - 1) - i; - Data[Offset + Idx] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff); + Data[Idx] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff); } } diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp index 84eb15f..eecef31 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp @@ -39,7 +39,7 @@ public: MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, bool) override; + uint8_t *Data, uint64_t Value, bool) override; std::unique_ptr<MCObjectTargetWriter> createObjectTargetWriter() const override; @@ -80,8 +80,7 @@ bool WebAssemblyAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, void WebAssemblyAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, + const MCValue &Target, uint8_t *Data, uint64_t Value, bool IsResolved) { if (!IsResolved) Asm->getWriter().recordRelocation(F, Fixup, Target, Value); @@ -96,13 +95,13 @@ void WebAssemblyAsmBackend::applyFixup(const MCFragment &F, // Shift the value into position. Value <<= Info.TargetOffset; - unsigned Offset = Fixup.getOffset(); - assert(Offset + NumBytes <= F.getSize() && "Invalid fixup offset!"); + assert(Fixup.getOffset() + NumBytes <= F.getSize() && + "Invalid fixup offset!"); // For each byte of the fragment that the fixup touches, mask in the // bits from the fixup value. for (unsigned I = 0; I != NumBytes; ++I) - Data[Offset + I] |= uint8_t((Value >> (I * 8)) & 0xff); + Data[I] |= uint8_t((Value >> (I * 8)) & 0xff); } std::unique_ptr<MCObjectTargetWriter> diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp index 1efef83..1f02e56 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -174,8 +174,7 @@ public: std::optional<bool> evaluateFixup(const MCFragment &, MCFixup &, MCValue &, uint64_t &) override; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; bool mayNeedRelaxation(unsigned Opcode, ArrayRef<MCOperand> Operands, const MCSubtargetInfo &STI) const override; @@ -676,9 +675,8 @@ std::optional<bool> X86AsmBackend::evaluateFixup(const MCFragment &, } void X86AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { // Force relocation when there is a specifier. This might be too conservative // - GAS doesn't emit a relocation for call local@plt; local:. if (Target.getSpecifier()) @@ -710,7 +708,7 @@ void X86AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, } for (unsigned i = 0; i != Size; ++i) - Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8)); + Data[i] = uint8_t(Value >> (i * 8)); } bool X86AsmBackend::mayNeedRelaxation(unsigned Opcode, diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp index 95ed590..cba7843 100644 --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -24,6 +24,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/CodeGen/WinEHFuncInfo.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/EHPersonalities.h" @@ -2678,7 +2679,7 @@ StackOffset X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, // object. // We need to factor in additional offsets applied during the prologue to the // frame, base, and stack pointer depending on which is used. - int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea(); + int64_t Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea(); const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); unsigned CSSize = X86FI->getCalleeSavedFrameSize(); uint64_t StackSize = MFI.getStackSize(); @@ -4212,6 +4213,14 @@ void X86FrameLowering::processFunctionBeforeFrameFinalized( // emitPrologue if it gets called and emits CFI. MF.setHasWinCFI(false); + MachineFrameInfo &MFI = MF.getFrameInfo(); + // If the frame is big enough that we might need to scavenge a register to + // handle huge offsets, reserve a stack slot for that now. + if (!isInt<32>(MFI.estimateStackSize(MF))) { + int FI = MFI.CreateStackObject(SlotSize, Align(SlotSize), false); + RS->addScavengingFrameIndex(FI); + } + // If we are using Windows x64 CFI, ensure that the stack is always 8 byte // aligned. The format doesn't support misaligned stack adjustments. if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index bbbb1d9..ce4c061 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23486,7 +23486,6 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC, } // Try to shrink i64 compares if the input has enough zero bits. - // TODO: Add sign-bits equivalent for isX86CCSigned(X86CC)? if (CmpVT == MVT::i64 && !isX86CCSigned(X86CC) && Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. DAG.MaskedValueIsZero(Op1, APInt::getHighBitsSet(64, 32)) && @@ -23496,6 +23495,16 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC, Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1); } + // Try to shrink all i64 compares if the inputs are representable as signed + // i32. + if (CmpVT == MVT::i64 && + Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. + DAG.ComputeNumSignBits(Op1) > 32 && DAG.ComputeNumSignBits(Op0) > 32) { + CmpVT = MVT::i32; + Op0 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op0); + Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1); + } + // 0-x == y --> x+y == 0 // 0-x != y --> x+y != 0 if (Op0.getOpcode() == ISD::SUB && isNullConstant(Op0.getOperand(0)) && diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index 83b11ee..6480183 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "X86RegisterInfo.h" +#include "MCTargetDesc/X86BaseInfo.h" #include "X86FrameLowering.h" #include "X86MachineFunctionInfo.h" #include "X86Subtarget.h" @@ -21,8 +22,8 @@ #include "llvm/ADT/SmallSet.h" #include "llvm/CodeGen/LiveRegMatrix.h" #include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TileShapeInfo.h" @@ -907,7 +908,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); // Determine base register and offset. - int FIOffset; + int64_t FIOffset; Register BasePtr; if (MI.isReturn()) { assert((!hasStackRealignment(MF) || @@ -958,11 +959,37 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } if (MI.getOperand(FIOperandNum+3).isImm()) { - // Offset is a 32-bit integer. - int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm()); - int Offset = FIOffset + Imm; - assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) && - "Requesting 64-bit offset in 32-bit immediate!"); + int64_t Imm = MI.getOperand(FIOperandNum + 3).getImm(); + int64_t Offset = FIOffset + Imm; + bool FitsIn32Bits = isInt<32>(Offset); + // If the offset will not fit in a 32-bit displacement, then for 64-bit + // targets, scavenge a register to hold it. Otherwise... + if (Is64Bit && !FitsIn32Bits) { + assert(RS && "RegisterScavenger was NULL"); + const X86InstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo(); + const DebugLoc &DL = MI.getDebugLoc(); + + RS->enterBasicBlockEnd(MBB); + RS->backward(std::next(II)); + + Register ScratchReg = RS->scavengeRegisterBackwards( + X86::GR64RegClass, II, /*RestoreAfter=*/false, /*SPAdj=*/0, + /*AllowSpill=*/true); + assert(ScratchReg != 0 && "scratch reg was 0"); + RS->setRegUsed(ScratchReg); + + BuildMI(MBB, II, DL, TII->get(X86::MOV64ri), ScratchReg).addImm(Offset); + + MI.getOperand(FIOperandNum + 3).setImm(0); + MI.getOperand(FIOperandNum + 2).setReg(ScratchReg); + + return false; + } + + // ... for 32-bit targets, this is a bug! + if (!Is64Bit && !FitsIn32Bits) + MI.emitGenericError(("64-bit offset calculated but target is 32-bit")); + if (Offset != 0 || !tryOptimizeLEAtoMOV(II)) MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset); } else { diff --git a/llvm/lib/Target/X86/X86RegisterInfo.h b/llvm/lib/Target/X86/X86RegisterInfo.h index 19b409a..2f4c55c 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.h +++ b/llvm/lib/Target/X86/X86RegisterInfo.h @@ -13,6 +13,7 @@ #ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H #define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #define GET_REGINFO_HEADER @@ -180,6 +181,10 @@ public: constrainRegClassToNonRex2(const TargetRegisterClass *RC) const; bool isNonRex2RegClass(const TargetRegisterClass *RC) const; + + bool requiresRegisterScavenging(const MachineFunction &MF) const override { + return true; + } }; } // End llvm namespace diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp index 9167794..08936ad 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp @@ -37,8 +37,7 @@ public: std::optional<bool> evaluateFixup(const MCFragment &, MCFixup &, MCValue &, uint64_t &) override; void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) override; + uint8_t *Data, uint64_t Value, bool IsResolved) override; bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override; @@ -153,9 +152,8 @@ std::optional<bool> XtensaAsmBackend::evaluateFixup(const MCFragment &F, } void XtensaAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, - const MCValue &Target, - MutableArrayRef<char> Data, uint64_t Value, - bool IsResolved) { + const MCValue &Target, uint8_t *Data, + uint64_t Value, bool IsResolved) { maybeAddReloc(F, Fixup, Target, Value, IsResolved); MCContext &Ctx = getContext(); MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind()); @@ -168,11 +166,10 @@ void XtensaAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup, if (!Value) return; // Doesn't change encoding. - unsigned Offset = Fixup.getOffset(); unsigned FullSize = getSize(Fixup.getKind()); for (unsigned i = 0; i != FullSize; ++i) { - Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); + Data[i] |= uint8_t((Value >> (i * 8)) & 0xff); } } diff --git a/llvm/lib/TargetParser/TargetParser.cpp b/llvm/lib/TargetParser/TargetParser.cpp index 126be71..e5d2e1c 100644 --- a/llvm/lib/TargetParser/TargetParser.cpp +++ b/llvm/lib/TargetParser/TargetParser.cpp @@ -444,6 +444,7 @@ void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple &T, Features["bitop3-insts"] = true; Features["prng-inst"] = true; Features["tanh-insts"] = true; + Features["tensor-cvt-lut-insts"] = true; Features["transpose-load-f4f6-insts"] = true; Features["bf16-trans-insts"] = true; Features["bf16-cvt-insts"] = true; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index b268fea..d4f83ec 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -113,10 +113,16 @@ Instruction *InstCombinerImpl::foldCmpLoadFromIndexedGlobal( LoadInst *LI, GetElementPtrInst *GEP, GlobalVariable *GV, CmpInst &ICI, ConstantInt *AndCst) { if (LI->isVolatile() || LI->getType() != GEP->getResultElementType() || - GV->getValueType() != GEP->getSourceElementType() || !GV->isConstant() || + !GV->getValueType()->isArrayTy() || !GV->isConstant() || !GV->hasDefinitiveInitializer()) return nullptr; + Type *GEPSrcEltTy = GEP->getSourceElementType(); + if (GEPSrcEltTy->isArrayTy()) + GEPSrcEltTy = GEPSrcEltTy->getArrayElementType(); + if (GV->getValueType()->getArrayElementType() != GEPSrcEltTy) + return nullptr; + Constant *Init = GV->getInitializer(); if (!isa<ConstantArray>(Init) && !isa<ConstantDataArray>(Init)) return nullptr; @@ -127,12 +133,19 @@ Instruction *InstCombinerImpl::foldCmpLoadFromIndexedGlobal( return nullptr; // There are many forms of this optimization we can handle, for now, just do - // the simple index into a single-dimensional array. + // the simple index into a single-dimensional array or elements of equal size. // - // Require: GEP GV, 0, i {{, constant indices}} - if (GEP->getNumOperands() < 3 || !isa<ConstantInt>(GEP->getOperand(1)) || - !cast<ConstantInt>(GEP->getOperand(1))->isZero() || - isa<Constant>(GEP->getOperand(2))) + // Require: GEP [n x i8] GV, 0, Idx {{, constant indices}} + // Or: GEP i8 GV, Idx + + unsigned GEPIdxOp = 1; + if (GEP->getSourceElementType()->isArrayTy()) { + GEPIdxOp = 2; + if (!match(GEP->getOperand(1), m_ZeroInt())) + return nullptr; + } + if (GEP->getNumOperands() < GEPIdxOp + 1 || + isa<Constant>(GEP->getOperand(GEPIdxOp))) return nullptr; // Check that indices after the variable are constants and in-range for the @@ -141,7 +154,7 @@ Instruction *InstCombinerImpl::foldCmpLoadFromIndexedGlobal( SmallVector<unsigned, 4> LaterIndices; Type *EltTy = Init->getType()->getArrayElementType(); - for (unsigned i = 3, e = GEP->getNumOperands(); i != e; ++i) { + for (unsigned i = GEPIdxOp + 1, e = GEP->getNumOperands(); i != e; ++i) { ConstantInt *Idx = dyn_cast<ConstantInt>(GEP->getOperand(i)); if (!Idx) return nullptr; // Variable index. @@ -163,7 +176,7 @@ Instruction *InstCombinerImpl::foldCmpLoadFromIndexedGlobal( LaterIndices.push_back(IdxVal); } - Value *Idx = GEP->getOperand(2); + Value *Idx = GEP->getOperand(GEPIdxOp); // If the index type is non-canonical, wait for it to be canonicalized. if (Idx->getType() != DL.getIndexType(GEP->getType())) return nullptr; diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index b4ea70e..d04317b 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -7302,6 +7302,7 @@ DenseMap<const SCEV *, Value *> LoopVectorizationPlanner::executePlan( // Retrieving VectorPH now when it's easier while VPlan still has Regions. VPBasicBlock *VectorPH = cast<VPBasicBlock>(BestVPlan.getVectorPreheader()); + VPlanTransforms::optimizeForVFAndUF(BestVPlan, BestVF, BestUF, PSE); VPlanTransforms::simplifyRecipes(BestVPlan, *Legal->getWidestInductionType()); VPlanTransforms::removeBranchOnConst(BestVPlan); @@ -7317,6 +7318,8 @@ DenseMap<const SCEV *, Value *> LoopVectorizationPlanner::executePlan( VPlanTransforms::dissolveLoopRegions(BestVPlan); // Canonicalize EVL loops after regions are dissolved. VPlanTransforms::canonicalizeEVLLoops(BestVPlan); + VPlanTransforms::materializeBackedgeTakenCount(BestVPlan, VectorPH); + // Perform the actual loop transformation. VPTransformState State(&TTI, BestVF, LI, DT, ILV.AC, ILV.Builder, &BestVPlan, OrigLoop->getParentLoop(), @@ -7373,7 +7376,6 @@ DenseMap<const SCEV *, Value *> LoopVectorizationPlanner::executePlan( // 2. Copy and widen instructions from the old loop into the new loop. BestVPlan.prepareToExecute( - ILV.getTripCount(), ILV.getOrCreateVectorTripCount(ILV.LoopVectorPreHeader), State); replaceVPBBWithIRVPBB(VectorPH, State.CFG.PrevBB); diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp index 25b9616..2138b41 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp @@ -951,17 +951,7 @@ VPlan::~VPlan() { delete BackedgeTakenCount; } -void VPlan::prepareToExecute(Value *TripCountV, Value *VectorTripCountV, - VPTransformState &State) { - Type *TCTy = TripCountV->getType(); - // Check if the backedge taken count is needed, and if so build it. - if (BackedgeTakenCount && BackedgeTakenCount->getNumUsers()) { - IRBuilder<> Builder(State.CFG.PrevBB->getTerminator()); - auto *TCMO = Builder.CreateSub(TripCountV, ConstantInt::get(TCTy, 1), - "trip.count.minus.1"); - BackedgeTakenCount->setUnderlyingValue(TCMO); - } - +void VPlan::prepareToExecute(Value *VectorTripCountV, VPTransformState &State) { if (!VectorTripCount.getUnderlyingValue()) VectorTripCount.setUnderlyingValue(VectorTripCountV); else @@ -969,6 +959,7 @@ void VPlan::prepareToExecute(Value *TripCountV, Value *VectorTripCountV, "VectorTripCount set earlier must much VectorTripCountV"); IRBuilder<> Builder(State.CFG.PrevBB->getTerminator()); + Type *TCTy = VectorTripCountV->getType(); // FIXME: Model VF * UF computation completely in VPlan. unsigned UF = getUF(); if (VF.getNumUsers()) { diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index a5de593..6f547a3 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -3958,8 +3958,7 @@ public: } /// Prepare the plan for execution, setting up the required live-in values. - void prepareToExecute(Value *TripCount, Value *VectorTripCount, - VPTransformState &State); + void prepareToExecute(Value *VectorTripCount, VPTransformState &State); /// Generate the IR code for this VPlan. void execute(VPTransformState *State); diff --git a/llvm/lib/Transforms/Vectorize/VPlanCFG.h b/llvm/lib/Transforms/Vectorize/VPlanCFG.h index b77aa9d..c79485c 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanCFG.h +++ b/llvm/lib/Transforms/Vectorize/VPlanCFG.h @@ -231,6 +231,13 @@ vp_post_order_shallow(VPBlockBase *G) { } /// Returns an iterator range to traverse the graph starting at \p G in +/// post order while traversing through region blocks. +inline iterator_range<po_iterator<VPBlockDeepTraversalWrapper<VPBlockBase *>>> +vp_post_order_deep(VPBlockBase *G) { + return post_order(VPBlockDeepTraversalWrapper<VPBlockBase *>(G)); +} + +/// Returns an iterator range to traverse the graph starting at \p G in /// depth-first order while traversing through region blocks. inline iterator_range<df_iterator<VPBlockDeepTraversalWrapper<VPBlockBase *>>> vp_depth_first_deep(VPBlockBase *G) { diff --git a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp index 6c1f53b..a66c4a7 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp @@ -671,13 +671,12 @@ bool VPlanTransforms::handleMaxMinNumReductions(VPlan &Plan) { Intrinsic::ID RdxIntrinsicId = RedPhiR->getRecurrenceKind() == RecurKind::FMaxNum ? Intrinsic::maxnum : Intrinsic::minnum; - assert((isa<VPWidenIntrinsicRecipe>(MinMaxR) && - cast<VPWidenIntrinsicRecipe>(MinMaxR)->getVectorIntrinsicID() == - RdxIntrinsicId) || - (RepR && - cast<IntrinsicInst>(RepR->getUnderlyingInstr())->getIntrinsicID() == - RdxIntrinsicId) && - "Intrinsic did not match recurrence kind"); + assert(((isa<VPWidenIntrinsicRecipe>(MinMaxR) && + cast<VPWidenIntrinsicRecipe>(MinMaxR)->getVectorIntrinsicID() == + RdxIntrinsicId) || + (RepR && cast<IntrinsicInst>(RepR->getUnderlyingInstr()) + ->getIntrinsicID() == RdxIntrinsicId)) && + "Intrinsic did not match recurrence kind"); #endif if (MinMaxR->getOperand(0) == RedPhiR) diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index 11b4677..98d11f0 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -2836,12 +2836,12 @@ static void scalarizeInstruction(const Instruction *Instr, Instruction *Cloned = Instr->clone(); if (!IsVoidRetTy) { Cloned->setName(Instr->getName() + ".cloned"); -#if !defined(NDEBUG) - // Verify that VPlan type inference results agree with the type of the - // generated values. - assert(State.TypeAnalysis.inferScalarType(RepRecipe) == Cloned->getType() && - "inferred type and type from generated instructions do not match"); -#endif + Type *ResultTy = State.TypeAnalysis.inferScalarType(RepRecipe); + // The operands of the replicate recipe may have been narrowed, resulting in + // a narrower result type. Update the type of the cloned instruction to the + // correct type. + if (ResultTy != Cloned->getType()) + Cloned->mutateType(ResultTy); } RepRecipe->applyFlags(*Cloned); diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index fcbc86f..3ecffc7 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -545,10 +545,8 @@ static bool isDeadRecipe(VPRecipeBase &R) { } void VPlanTransforms::removeDeadRecipes(VPlan &Plan) { - ReversePostOrderTraversal<VPBlockDeepTraversalWrapper<VPBlockBase *>> RPOT( - Plan.getEntry()); - - for (VPBasicBlock *VPBB : reverse(VPBlockUtils::blocksOnly<VPBasicBlock>(RPOT))) { + for (VPBasicBlock *VPBB : VPBlockUtils::blocksOnly<VPBasicBlock>( + vp_post_order_deep(Plan.getEntry()))) { // The recipes in the block are processed in reverse order, to catch chains // of dead recipes. for (VPRecipeBase &R : make_early_inc_range(reverse(*VPBB))) { @@ -1431,15 +1429,15 @@ static bool isConditionTrueViaVFAndUF(VPValue *Cond, VPlan &Plan, // count is not conveniently available as SCEV so far, so we compare directly // against the original trip count. This is stricter than necessary, as we // will only return true if the trip count == vector trip count. - // TODO: Use SCEV for vector trip count once available, to cover cases where - // vector trip count == UF * VF, but original trip count != UF * VF. - const SCEV *TripCount = - vputils::getSCEVExprForVPValue(Plan.getTripCount(), SE); - assert(!isa<SCEVCouldNotCompute>(TripCount) && + const SCEV *VectorTripCount = + vputils::getSCEVExprForVPValue(&Plan.getVectorTripCount(), SE); + if (isa<SCEVCouldNotCompute>(VectorTripCount)) + VectorTripCount = vputils::getSCEVExprForVPValue(Plan.getTripCount(), SE); + assert(!isa<SCEVCouldNotCompute>(VectorTripCount) && "Trip count SCEV must be computable"); ElementCount NumElements = BestVF.multiplyCoefficientBy(BestUF); - const SCEV *C = SE.getElementCount(TripCount->getType(), NumElements); - return SE.isKnownPredicate(CmpInst::ICMP_EQ, TripCount, C); + const SCEV *C = SE.getElementCount(VectorTripCount->getType(), NumElements); + return SE.isKnownPredicate(CmpInst::ICMP_EQ, VectorTripCount, C); } /// Try to simplify the branch condition of \p Plan. This may restrict the @@ -3178,6 +3176,21 @@ void VPlanTransforms::materializeVectorTripCount( Plan.getVectorTripCount().setUnderlyingValue(NewC->getValue()); } +void VPlanTransforms::materializeBackedgeTakenCount(VPlan &Plan, + VPBasicBlock *VectorPH) { + VPValue *BTC = Plan.getOrCreateBackedgeTakenCount(); + if (BTC->getNumUsers() == 0) + return; + + VPBuilder Builder(VectorPH, VectorPH->begin()); + auto *TCTy = VPTypeAnalysis(Plan).inferScalarType(Plan.getTripCount()); + auto *TCMO = Builder.createNaryOp( + Instruction::Sub, + {Plan.getTripCount(), Plan.getOrAddLiveIn(ConstantInt::get(TCTy, 1))}, + DebugLoc::getCompilerGenerated(), "trip.count.minus.1"); + BTC->replaceAllUsesWith(TCMO); +} + /// Returns true if \p V is VPWidenLoadRecipe or VPInterleaveRecipe that can be /// converted to a narrower recipe. \p V is used by a wide recipe that feeds a /// store interleave group at index \p Idx, \p WideMember0 is the recipe feeding diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h index 880159f..5943684 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h @@ -256,6 +256,11 @@ struct VPlanTransforms { unsigned BestUF, PredicatedScalarEvolution &PSE); + /// Materialize the backedge-taken count to be computed explicitly using + /// VPInstructions. + static void materializeBackedgeTakenCount(VPlan &Plan, + VPBasicBlock *VectorPH); + /// Try to convert a plan with interleave groups with VF elements to a plan /// with the interleave groups replaced by wide loads and stores processing VF /// elements, if all transformed interleave groups access the full vector diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp index 81bd21b..14f20c6 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp @@ -73,8 +73,11 @@ bool vputils::isHeaderMask(const VPValue *V, VPlan &Plan) { } const SCEV *vputils::getSCEVExprForVPValue(VPValue *V, ScalarEvolution &SE) { - if (V->isLiveIn()) - return SE.getSCEV(V->getLiveInIRValue()); + if (V->isLiveIn()) { + if (Value *LiveIn = V->getLiveInIRValue()) + return SE.getSCEV(LiveIn); + return SE.getCouldNotCompute(); + } // TODO: Support constructing SCEVs for more recipes as needed. return TypeSwitch<const VPRecipeBase *, const SCEV *>(V->getDefiningRecipe()) diff --git a/llvm/test/CodeGen/AMDGPU/ctpop16.ll b/llvm/test/CodeGen/AMDGPU/ctpop16.ll index 1b9b508..cefcbdd 100644 --- a/llvm/test/CodeGen/AMDGPU/ctpop16.ll +++ b/llvm/test/CodeGen/AMDGPU/ctpop16.ll @@ -457,27 +457,58 @@ define amdgpu_kernel void @v_ctpop_v4i16(ptr addrspace(1) noalias %out, ptr addr ; ; EG-LABEL: v_ctpop_v4i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 3, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 7, @11, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T6.X, 1 +; EG-NEXT: ALU 37, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XY, T0.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 +; EG-NEXT: VTX_READ_64 T8.XY, T0.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: LSHL * T0.W, T0.X, literal.x, +; EG-NEXT: MOV T0.Y, T4.X, +; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, -; EG-NEXT: ALU clause starting at 11: -; EG-NEXT: LSHR * T0.W, T0.X, literal.x, +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: AND_INT * T0.W, T8.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: LSHR * T0.W, T8.X, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: BCNT_INT T0.Y, PV.W, -; EG-NEXT: AND_INT * T0.W, T0.X, literal.x, +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.X, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: BCNT_INT T0.X, PV.W, -; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV * T0.X, T5.X, +; EG-NEXT: AND_INT * T0.W, T8.Y, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, T0.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: LSHR * T0.W, T8.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T8.Y, T1.W, PV.W, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.Y, +; EG-NEXT: MOV * T8.X, T4.X, %tid = call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr <4 x i16>, ptr addrspace(1) %in, i32 %tid %val = load <4 x i16>, ptr addrspace(1) %in.gep, align 16 @@ -570,33 +601,94 @@ define amdgpu_kernel void @v_ctpop_v8i16(ptr addrspace(1) noalias %out, ptr addr ; ; EG-LABEL: v_ctpop_v8i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 3, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 13, @11, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T8.X, 1 +; EG-NEXT: ALU 73, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T12.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 +; EG-NEXT: VTX_READ_128 T12.XYZW, T0.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: LSHL * T0.W, T0.X, literal.x, +; EG-NEXT: MOV T0.Y, T4.X, +; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212 ; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00) ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, -; EG-NEXT: ALU clause starting at 11: -; EG-NEXT: LSHR * T0.W, T0.Z, literal.x, +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: LSHR * T0.W, T12.X, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BCNT_INT * T0.W, PV.W, +; EG-NEXT: LSHL T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T0.W, T12.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV * T0.X, T5.X, +; EG-NEXT: LSHR * T0.W, T12.Y, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) ; EG-NEXT: BCNT_INT T0.W, PV.W, -; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.X, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: BCNT_INT T0.Z, PS, -; EG-NEXT: LSHR * T1.W, T0.X, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T0.W, T12.Y, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.Y, PS, PV.W, +; EG-NEXT: MOV T5.X, PV.Y, +; EG-NEXT: MOV * T0.X, T8.X, +; EG-NEXT: LSHR * T0.W, T12.Z, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: BCNT_INT T0.Y, PV.W, +; EG-NEXT: BCNT_INT T0.W, PV.W, ; EG-NEXT: AND_INT * T1.W, T0.X, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: BCNT_INT T0.X, PV.W, -; EG-NEXT: LSHR * T8.X, KC0[2].Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T0.W, T12.Z, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV * T0.X, T9.X, +; EG-NEXT: LSHR * T0.W, T12.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, T0.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T0.W, T12.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: LSHR T12.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T0.W, PS, PV.W, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T9.X, PV.W, +; EG-NEXT: MOV * T0.X, T4.X, +; EG-NEXT: MOV * T0.Z, T8.X, %tid = call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr <8 x i16>, ptr addrspace(1) %in, i32 %tid %val = load <8 x i16>, ptr addrspace(1) %in.gep, align 32 @@ -745,46 +837,174 @@ define amdgpu_kernel void @v_ctpop_v16i16(ptr addrspace(1) noalias %out, ptr add ; ; EG-LABEL: v_ctpop_v16i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 2, @10, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 1 @6 -; EG-NEXT: ALU 25, @13, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T14.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T13.X, 1 +; EG-NEXT: ALU 3, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @8 +; EG-NEXT: ALU 114, @16, KC0[], KC1[] +; EG-NEXT: ALU 34, @131, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T22.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T21.X, 1 ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_128 T12.XYZW, T0.X, 16, #1 -; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 -; EG-NEXT: ALU clause starting at 10: -; EG-NEXT: LSHL * T0.W, T0.X, literal.x, +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T20.XYZW, T0.X, 16, #1 +; EG-NEXT: VTX_READ_128 T21.XYZW, T0.X, 0, #1 +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV T0.Y, T4.X, +; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212 ; EG-NEXT: 5(7.006492e-45), 0(0.000000e+00) ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, -; EG-NEXT: ALU clause starting at 13: -; EG-NEXT: LSHR * T0.W, T12.Z, literal.x, +; EG-NEXT: ALU clause starting at 16: +; EG-NEXT: LSHR * T0.W, T20.X, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: BCNT_INT T12.W, PV.W, -; EG-NEXT: AND_INT * T0.W, T12.Z, literal.x, +; EG-NEXT: BCNT_INT * T0.W, PV.W, +; EG-NEXT: LSHL T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T0.W, T20.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV * T0.X, T5.X, +; EG-NEXT: LSHR * T0.W, T20.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, T0.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T0.W, T20.Y, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.Y, PS, PV.W, +; EG-NEXT: MOV T5.X, PV.Y, +; EG-NEXT: MOV * T0.X, T8.X, +; EG-NEXT: LSHR * T0.W, T20.Z, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, T0.X, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: BCNT_INT T12.Z, PS, -; EG-NEXT: LSHR T0.W, T0.Z, literal.x, -; EG-NEXT: LSHR * T1.W, T12.X, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T0.W, T20.Z, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV * T0.X, T9.X, +; EG-NEXT: LSHR * T0.W, T20.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, T0.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: BCNT_INT T12.Y, PS, -; EG-NEXT: AND_INT T0.Z, T0.Z, literal.x, +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T0.W, T20.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) ; EG-NEXT: BCNT_INT T0.W, PV.W, -; EG-NEXT: AND_INT * T1.W, T12.X, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV T9.X, PV.W, +; EG-NEXT: MOV * T0.X, T12.X, +; EG-NEXT: LSHR * T1.W, T21.X, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T1.W, PV.W, +; EG-NEXT: AND_INT * T2.W, T0.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T1.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, +; EG-NEXT: MOV * T12.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T1.W, T21.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T1.W, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PS, PV.W, +; EG-NEXT: MOV T12.X, PV.W, +; EG-NEXT: MOV * T0.X, T13.X, +; EG-NEXT: LSHR * T1.W, T21.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T1.W, PV.W, +; EG-NEXT: AND_INT * T2.W, T0.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T1.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, +; EG-NEXT: MOV * T13.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T1.W, T21.Y, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T1.W, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T20.Y, PS, PV.W, +; EG-NEXT: MOV T13.X, PV.Y, +; EG-NEXT: MOV * T0.X, T16.X, +; EG-NEXT: LSHR * T1.W, T21.Z, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T1.W, PV.W, +; EG-NEXT: AND_INT * T2.W, T0.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T1.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, +; EG-NEXT: ALU clause starting at 131: +; EG-NEXT: MOV * T16.X, T1.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT * T1.W, T21.Z, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T1.W, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PS, PV.W, +; EG-NEXT: MOV T16.X, PV.W, +; EG-NEXT: MOV * T0.X, T17.X, +; EG-NEXT: LSHR * T1.W, T21.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BCNT_INT T1.W, PV.W, +; EG-NEXT: AND_INT * T2.W, T0.X, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: BCNT_INT T12.X, PS, -; EG-NEXT: BCNT_INT T0.Z, PV.Z, -; EG-NEXT: LSHR T1.W, T0.X, literal.x, -; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x, +; EG-NEXT: LSHL * T1.W, PV.W, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T13.X, PS, literal.x, -; EG-NEXT: BCNT_INT T0.Y, PV.W, -; EG-NEXT: AND_INT * T1.W, T0.X, literal.y, -; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41) -; EG-NEXT: BCNT_INT T0.X, PV.W, -; EG-NEXT: LSHR * T14.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, +; EG-NEXT: MOV * T17.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: AND_INT T1.W, T21.W, literal.x, +; EG-NEXT: LSHR * T21.X, KC0[2].Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), 2(2.802597e-45) +; EG-NEXT: AND_INT T0.Z, PV.X, literal.x, +; EG-NEXT: BCNT_INT T1.W, PV.W, +; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y, +; EG-NEXT: -65536(nan), 16(2.242078e-44) +; EG-NEXT: LSHR T22.X, PS, literal.x, +; EG-NEXT: OR_INT * T20.W, PV.Z, PV.W, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T17.X, PV.W, +; EG-NEXT: MOV * T0.X, T4.X, +; EG-NEXT: MOV * T0.Z, T8.X, +; EG-NEXT: MOV T20.X, T12.X, +; EG-NEXT: MOV * T20.Z, T16.X, BS:VEC_120/SCL_212 %tid = call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr <16 x i16>, ptr addrspace(1) %in, i32 %tid %val = load <16 x i16>, ptr addrspace(1) %in.gep, align 32 @@ -1292,7 +1512,7 @@ define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace( ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB14_4: -; SI-NEXT: ; implicit-def: $vgpr0 +; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: s_branch .LBB14_2 ; ; VI-LABEL: ctpop_i16_in_br: diff --git a/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll b/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll index ceacdf5..cbda062 100644 --- a/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll @@ -1,45 +1,184 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -mattr=+fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-FLUSH,GCN-FLUSH-MAD,SI %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=ieee -mattr=+fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-DENORM-STRICT,SI-DENORM,GCN-DENORM-FASTFMA,SI %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=preserve-sign -mattr=-fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-FLUSH,GCN-FLUSH-MAD,SI-FLUSH,SI %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=ieee -mattr=-fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-DENORM-STRICT,SI-DENORM,GCN-DENORM-SLOWFMA,SI %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -mattr=+fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=preserve-sign -mattr=-fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=ieee -mattr=+fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-FASTFMA,SI-DENORM-FASTFMA-STRICT %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=ieee -mattr=-fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-SLOWFMA %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -mattr=+fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-FLUSH,GCN-FLUSH-MAD,SI-FLUSH,SI %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=ieee -mattr=+fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI-DENORM,GCN-DENORM-FASTFMA,GCN-DENORM-FASTFMA-CONTRACT,SI %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=preserve-sign -mattr=-fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-FLUSH,GCN-FLUSH-MAD,SI-FLUSH,SI %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=ieee -mattr=-fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI-DENORM,GCN-DENORM-SLOWFMA,GCN-DENORM-SLOWFMA-CONTRACT,SI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -mattr=+fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=preserve-sign -mattr=-fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=ieee -mattr=+fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-FASTFMA,SI-DENORM-FASTFMA-CONTRACT %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=ieee -mattr=-fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-SLOWFMA %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-FLUSH,GFX9-FLUSH-MAD %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -denormal-fp-math-f32=ieee -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-DENORM,GFX9-DENORM-FASTFMA-MAD %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-FLUSH,GCN-FLUSH-MAD %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -denormal-fp-math-f32=ieee -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-DENORM-STRICT,GCN-DENORM-FASTFMA %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx906 -denormal-fp-math-f32=preserve-sign -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-FLUSH,GFX9-FLUSH-FMAC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx906 -denormal-fp-math-f32=ieee -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-DENORM,GFX9-DENORM-FASTFMA-FMAC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx906 -denormal-fp-math-f32=preserve-sign -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-FLUSH,GCN-FLUSH-FMAC %s - -; FIXME: Should probably test this, but sometimes selecting fmac is painful to match. -; XUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx906 -denormal-fp-math-f32=ieee -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-DENORM-STRICT,GCN-DENORM-FASTFMA %s - -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx1030 -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-FLUSH,GCN-FLUSH-FMAC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx1030 -denormal-fp-math-f32=ieee -mattr=+mad-mac-f32-insts -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-DENORM-STRICT %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx1030 -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX10-FLUSH %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx1030 -denormal-fp-math-f32=ieee -mattr=+mad-mac-f32-insts -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX10-DENORM %s ; Test all permutations of: fp32 denormals, fast fp contract, fp contract enabled for fmuladd, fmaf fast/slow. target triple = "amdgcn--" - declare i32 @llvm.amdgcn.workitem.id.x() #1 declare float @llvm.fmuladd.f32(float, float, float) #1 declare half @llvm.fmuladd.f16(half, half, half) #1 declare float @llvm.fabs.f32(float) #1 -; GCN-LABEL: {{^}}fmuladd_f32: -; GCN-FLUSH-MAD: v_mac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} -; GCN-FLUSH-FMAC: v_fmac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} - -; GCN-DENORM-FASTFMA: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+}} - -; GCN-DENORM-SLOWFMA: v_mul_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} -; GCN-DENORM-SLOWFMA: v_add_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} -define amdgpu_kernel void @fmuladd_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, - ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 { +define amdgpu_kernel void @fmuladd_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 { +; SI-FLUSH-LABEL: fmuladd_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s11, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s10, -1 +; SI-FLUSH-NEXT: s_mov_b32 s14, s10 +; SI-FLUSH-NEXT: s_mov_b32 s15, s11 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: s_mov_b32 s12, s2 +; SI-FLUSH-NEXT: s_mov_b32 s13, s3 +; SI-FLUSH-NEXT: s_mov_b32 s16, s4 +; SI-FLUSH-NEXT: s_mov_b32 s17, s5 +; SI-FLUSH-NEXT: s_mov_b32 s18, s10 +; SI-FLUSH-NEXT: s_mov_b32 s19, s11 +; SI-FLUSH-NEXT: s_mov_b32 s4, s6 +; SI-FLUSH-NEXT: s_mov_b32 s5, s7 +; SI-FLUSH-NEXT: s_mov_b32 s6, s10 +; SI-FLUSH-NEXT: s_mov_b32 s7, s11 +; SI-FLUSH-NEXT: buffer_load_dword v0, off, s[12:15], 0 +; SI-FLUSH-NEXT: buffer_load_dword v1, off, s[16:19], 0 +; SI-FLUSH-NEXT: buffer_load_dword v2, off, s[4:7], 0 +; SI-FLUSH-NEXT: s_mov_b32 s8, s0 +; SI-FLUSH-NEXT: s_mov_b32 s9, s1 +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mac_f32_e32 v2, v0, v1 +; SI-FLUSH-NEXT: buffer_store_dword v2, off, s[8:11], 0 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-LABEL: fmuladd_f32: +; SI-DENORM-FASTFMA: ; %bb.0: +; SI-DENORM-FASTFMA-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s11, 0xf000 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s10, -1 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s14, s10 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s15, s11 +; SI-DENORM-FASTFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s12, s2 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s13, s3 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s16, s4 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s17, s5 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s18, s10 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s19, s11 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s4, s6 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s5, s7 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s6, s10 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s7, s11 +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v0, off, s[12:15], 0 +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v1, off, s[16:19], 0 +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v2, off, s[4:7], 0 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s8, s0 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s9, s1 +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: v_fma_f32 v0, v0, v1, v2 +; SI-DENORM-FASTFMA-NEXT: buffer_store_dword v0, off, s[8:11], 0 +; SI-DENORM-FASTFMA-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fmuladd_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s11, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s10, -1 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s14, s10 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s15, s11 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s12, s2 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s13, s3 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s16, s4 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s17, s5 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s18, s10 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s19, s11 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s4, s6 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s5, s7 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s6, s10 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s7, s11 +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v0, off, s[12:15], 0 +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v1, off, s[16:19], 0 +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, off, s[4:7], 0 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s8, s0 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s9, s1 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(1) +; SI-DENORM-SLOWFMA-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v0, off, s[8:11], 0 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; GFX9-FLUSH-MAD-LABEL: fmuladd_f32: +; GFX9-FLUSH-MAD: ; %bb.0: +; GFX9-FLUSH-MAD-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX9-FLUSH-MAD-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-FLUSH-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v1, v0, s[10:11] +; GFX9-FLUSH-MAD-NEXT: global_load_dword v2, v0, s[12:13] +; GFX9-FLUSH-MAD-NEXT: global_load_dword v3, v0, s[14:15] +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: v_mac_f32_e32 v3, v1, v2 +; GFX9-FLUSH-MAD-NEXT: global_store_dword v0, v3, s[8:9] +; GFX9-FLUSH-MAD-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-MAD-LABEL: fmuladd_f32: +; GFX9-DENORM-FASTFMA-MAD: ; %bb.0: +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v1, v0, s[10:11] +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v2, v0, s[12:13] +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v3, v0, s[14:15] +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_fma_f32 v1, v1, v2, v3 +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_store_dword v0, v1, s[8:9] +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_endpgm +; +; GFX9-FLUSH-FMAC-LABEL: fmuladd_f32: +; GFX9-FLUSH-FMAC: ; %bb.0: +; GFX9-FLUSH-FMAC-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX9-FLUSH-FMAC-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v1, v0, s[10:11] +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v2, v0, s[12:13] +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v3, v0, s[14:15] +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: v_fmac_f32_e32 v3, v1, v2 +; GFX9-FLUSH-FMAC-NEXT: global_store_dword v0, v3, s[8:9] +; GFX9-FLUSH-FMAC-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-FMAC-LABEL: fmuladd_f32: +; GFX9-DENORM-FASTFMA-FMAC: ; %bb.0: +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v1, v0, s[10:11] +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v2, v0, s[12:13] +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v3, v0, s[14:15] +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_fmac_f32_e32 v3, v1, v2 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_store_dword v0, v3, s[8:9] +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_endpgm +; +; GFX10-LABEL: fmuladd_f32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_clause 0x2 +; GFX10-NEXT: global_load_dword v1, v0, s[2:3] +; GFX10-NEXT: global_load_dword v2, v0, s[4:5] +; GFX10-NEXT: global_load_dword v3, v0, s[6:7] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_fmac_f32_e32 v3, v1, v2 +; GFX10-NEXT: global_store_dword v0, v3, s[0:1] +; GFX10-NEXT: s_endpgm %r0 = load float, ptr addrspace(1) %in1 %r1 = load float, ptr addrspace(1) %in2 %r2 = load float, ptr addrspace(1) %in3 @@ -48,18 +187,190 @@ define amdgpu_kernel void @fmuladd_f32(ptr addrspace(1) %out, ptr addrspace(1) % ret void } -; GCN-LABEL: {{^}}fmul_fadd_f32: -; GCN-FLUSH: v_mac_f32 - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 - -; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 -; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 - -; GCN-DENORM-STRICT: v_mul_f32_e32 -; GCN-DENORM-STRICT: v_add_f32_e32 -define amdgpu_kernel void @fmul_fadd_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, - ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 { +define amdgpu_kernel void @fmul_fadd_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 { +; SI-FLUSH-LABEL: fmul_fadd_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s11, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s10, -1 +; SI-FLUSH-NEXT: s_mov_b32 s14, s10 +; SI-FLUSH-NEXT: s_mov_b32 s15, s11 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: s_mov_b32 s12, s2 +; SI-FLUSH-NEXT: s_mov_b32 s13, s3 +; SI-FLUSH-NEXT: s_mov_b32 s16, s4 +; SI-FLUSH-NEXT: s_mov_b32 s17, s5 +; SI-FLUSH-NEXT: s_mov_b32 s18, s10 +; SI-FLUSH-NEXT: s_mov_b32 s19, s11 +; SI-FLUSH-NEXT: s_mov_b32 s4, s6 +; SI-FLUSH-NEXT: s_mov_b32 s5, s7 +; SI-FLUSH-NEXT: s_mov_b32 s6, s10 +; SI-FLUSH-NEXT: s_mov_b32 s7, s11 +; SI-FLUSH-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v1, off, s[16:19], 0 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, off, s[4:7], 0 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: s_mov_b32 s8, s0 +; SI-FLUSH-NEXT: s_mov_b32 s9, s1 +; SI-FLUSH-NEXT: v_mac_f32_e32 v2, v0, v1 +; SI-FLUSH-NEXT: buffer_store_dword v2, off, s[8:11], 0 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: fmul_fadd_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s11, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s10, -1 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s14, s10 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s15, s11 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s12, s2 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s13, s3 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s16, s4 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s17, s5 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s18, s10 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s19, s11 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s4, s6 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s5, s7 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s6, s10 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s7, s11 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v1, off, s[16:19], 0 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, off, s[4:7], 0 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s8, s0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s9, s1 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_add_f32_e32 v0, v0, v2 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v0, off, s[8:11], 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fmul_fadd_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s11, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s10, -1 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s14, s10 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s15, s11 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s12, s2 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s13, s3 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s16, s4 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s17, s5 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s18, s10 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s19, s11 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s4, s6 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s5, s7 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s6, s10 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s7, s11 +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v1, off, s[16:19], 0 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, off, s[4:7], 0 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s8, s0 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s9, s1 +; SI-DENORM-SLOWFMA-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v0, off, s[8:11], 0 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: fmul_fadd_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s11, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s10, -1 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s14, s10 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s15, s11 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s12, s2 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s13, s3 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s16, s4 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s17, s5 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s18, s10 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s19, s11 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s4, s6 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s5, s7 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s6, s10 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s7, s11 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v1, off, s[16:19], 0 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, off, s[4:7], 0 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s8, s0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s9, s1 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v0, v0, v1, v2 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v0, off, s[8:11], 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: fmul_fadd_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[10:11] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[12:13] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v3, v0, s[14:15] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v3, v1, v2 +; GFX9-FLUSH-NEXT: global_store_dword v0, v3, s[8:9] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: fmul_fadd_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[10:11] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[12:13] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v3, v0, s[14:15] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v3 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[8:9] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: fmul_fadd_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[4:5] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v3, v0, s[6:7] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mac_f32_e32 v3, v1, v2 +; GFX10-FLUSH-NEXT: global_store_dword v0, v3, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: fmul_fadd_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[4:5] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v3, v0, s[6:7] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v3 +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %r0 = load volatile float, ptr addrspace(1) %in1 %r1 = load volatile float, ptr addrspace(1) %in2 %r2 = load volatile float, ptr addrspace(1) %in3 @@ -69,15 +380,172 @@ define amdgpu_kernel void @fmul_fadd_f32(ptr addrspace(1) %out, ptr addrspace(1) ret void } -; GCN-LABEL: {{^}}fmul_fadd_contract_f32: -; GCN-FLUSH-FMAC: v_fmac_f32_e32 - -; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 -; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 - -; GCN-DENORM-FASTFMA: v_fma_f32 -define amdgpu_kernel void @fmul_fadd_contract_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, - ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 { +define amdgpu_kernel void @fmul_fadd_contract_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 { +; SI-FLUSH-LABEL: fmul_fadd_contract_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s11, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s10, -1 +; SI-FLUSH-NEXT: s_mov_b32 s14, s10 +; SI-FLUSH-NEXT: s_mov_b32 s15, s11 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: s_mov_b32 s12, s2 +; SI-FLUSH-NEXT: s_mov_b32 s13, s3 +; SI-FLUSH-NEXT: s_mov_b32 s16, s4 +; SI-FLUSH-NEXT: s_mov_b32 s17, s5 +; SI-FLUSH-NEXT: s_mov_b32 s18, s10 +; SI-FLUSH-NEXT: s_mov_b32 s19, s11 +; SI-FLUSH-NEXT: s_mov_b32 s4, s6 +; SI-FLUSH-NEXT: s_mov_b32 s5, s7 +; SI-FLUSH-NEXT: s_mov_b32 s6, s10 +; SI-FLUSH-NEXT: s_mov_b32 s7, s11 +; SI-FLUSH-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v1, off, s[16:19], 0 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, off, s[4:7], 0 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: s_mov_b32 s8, s0 +; SI-FLUSH-NEXT: s_mov_b32 s9, s1 +; SI-FLUSH-NEXT: v_mac_f32_e32 v2, v0, v1 +; SI-FLUSH-NEXT: buffer_store_dword v2, off, s[8:11], 0 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-LABEL: fmul_fadd_contract_f32: +; SI-DENORM-FASTFMA: ; %bb.0: +; SI-DENORM-FASTFMA-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s11, 0xf000 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s10, -1 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s14, s10 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s15, s11 +; SI-DENORM-FASTFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s12, s2 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s13, s3 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s16, s4 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s17, s5 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s18, s10 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s19, s11 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s4, s6 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s5, s7 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s6, s10 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s7, s11 +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v1, off, s[16:19], 0 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v2, off, s[4:7], 0 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s8, s0 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s9, s1 +; SI-DENORM-FASTFMA-NEXT: v_fma_f32 v0, v0, v1, v2 +; SI-DENORM-FASTFMA-NEXT: buffer_store_dword v0, off, s[8:11], 0 +; SI-DENORM-FASTFMA-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fmul_fadd_contract_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s11, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s10, -1 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s14, s10 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s15, s11 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s12, s2 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s13, s3 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s16, s4 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s17, s5 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s18, s10 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s19, s11 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s4, s6 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s5, s7 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s6, s10 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s7, s11 +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v1, off, s[16:19], 0 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, off, s[4:7], 0 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s8, s0 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s9, s1 +; SI-DENORM-SLOWFMA-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v0, off, s[8:11], 0 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; GFX9-FLUSH-MAD-LABEL: fmul_fadd_contract_f32: +; GFX9-FLUSH-MAD: ; %bb.0: +; GFX9-FLUSH-MAD-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX9-FLUSH-MAD-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-FLUSH-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v1, v0, s[10:11] glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v2, v0, s[12:13] glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v3, v0, s[14:15] glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: v_mac_f32_e32 v3, v1, v2 +; GFX9-FLUSH-MAD-NEXT: global_store_dword v0, v3, s[8:9] +; GFX9-FLUSH-MAD-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-MAD-LABEL: fmul_fadd_contract_f32: +; GFX9-DENORM-FASTFMA-MAD: ; %bb.0: +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v1, v0, s[10:11] glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v2, v0, s[12:13] glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v3, v0, s[14:15] glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_fma_f32 v1, v1, v2, v3 +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_store_dword v0, v1, s[8:9] +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_endpgm +; +; GFX9-FLUSH-FMAC-LABEL: fmul_fadd_contract_f32: +; GFX9-FLUSH-FMAC: ; %bb.0: +; GFX9-FLUSH-FMAC-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX9-FLUSH-FMAC-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v1, v0, s[10:11] glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v2, v0, s[12:13] glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v3, v0, s[14:15] glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: v_fmac_f32_e32 v3, v1, v2 +; GFX9-FLUSH-FMAC-NEXT: global_store_dword v0, v3, s[8:9] +; GFX9-FLUSH-FMAC-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-FMAC-LABEL: fmul_fadd_contract_f32: +; GFX9-DENORM-FASTFMA-FMAC: ; %bb.0: +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v1, v0, s[10:11] glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v2, v0, s[12:13] glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v3, v0, s[14:15] glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_fmac_f32_e32 v3, v1, v2 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_store_dword v0, v3, s[8:9] +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_endpgm +; +; GFX10-LABEL: fmul_fadd_contract_f32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_load_dword v2, v0, s[4:5] glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_load_dword v3, v0, s[6:7] glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_fmac_f32_e32 v3, v1, v2 +; GFX10-NEXT: global_store_dword v0, v3, s[0:1] +; GFX10-NEXT: s_endpgm %r0 = load volatile float, ptr addrspace(1) %in1 %r1 = load volatile float, ptr addrspace(1) %in2 %r2 = load volatile float, ptr addrspace(1) %in3 @@ -87,23 +555,120 @@ define amdgpu_kernel void @fmul_fadd_contract_f32(ptr addrspace(1) %out, ptr add ret void } -; GCN-LABEL: {{^}}fmuladd_2.0_a_b_f32 -; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]], -; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]], - -; GCN-FLUSH-MAD: v_mac_f32_e32 [[R2]], 2.0, [[R1]] -; GCN-FLUSH-FMAC: v_fmac_f32_e32 [[R2]], 2.0, [[R1]] -; SI-FLUSH: buffer_store_dword [[R2]] -; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]] - -; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]] - -; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]] - -; SI-DENORM: buffer_store_dword [[RESULT]] -; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @fmuladd_2.0_a_b_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-FLUSH-LABEL: fmuladd_2.0_a_b_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s3, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s2, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mac_f32_e32 v3, 2.0, v2 +; SI-FLUSH-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-LABEL: fmuladd_2.0_a_b_f32: +; SI-DENORM-FASTFMA: ; %bb.0: +; SI-DENORM-FASTFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: v_fma_f32 v2, v2, 2.0, v3 +; SI-DENORM-FASTFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fmuladd_2.0_a_b_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v3 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; GFX9-FLUSH-MAD-LABEL: fmuladd_2.0_a_b_f32: +; GFX9-FLUSH-MAD: ; %bb.0: +; GFX9-FLUSH-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: v_mac_f32_e32 v2, 2.0, v1 +; GFX9-FLUSH-MAD-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-MAD-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-MAD-LABEL: fmuladd_2.0_a_b_f32: +; GFX9-DENORM-FASTFMA-MAD: ; %bb.0: +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_fma_f32 v1, v1, 2.0, v2 +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_endpgm +; +; GFX9-FLUSH-FMAC-LABEL: fmuladd_2.0_a_b_f32: +; GFX9-FLUSH-FMAC: ; %bb.0: +; GFX9-FLUSH-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: v_fmac_f32_e32 v2, 2.0, v1 +; GFX9-FLUSH-FMAC-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-FMAC-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-FMAC-LABEL: fmuladd_2.0_a_b_f32: +; GFX9-DENORM-FASTFMA-FMAC: ; %bb.0: +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_fmac_f32_e32 v2, 2.0, v1 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_endpgm +; +; GFX10-LABEL: fmuladd_2.0_a_b_f32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_fmac_f32_e32 v2, 2.0, v1 +; GFX10-NEXT: global_store_dword v0, v2, s[0:1] +; GFX10-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1 @@ -117,24 +682,120 @@ define amdgpu_kernel void @fmuladd_2.0_a_b_f32(ptr addrspace(1) %out, ptr addrsp ret void } -; GCN-LABEL: {{^}}fmuladd_a_2.0_b_f32 -; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]], -; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]], - -; GCN-FLUSH-MAD: v_mac_f32_e32 [[R2]], 2.0, [[R1]] -; GCN-FLUSH-FMAC: v_fmac_f32_e32 [[R2]], 2.0, [[R1]] - -; SI-FLUSH: buffer_store_dword [[R2]] -; VI-FLUSH: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]] - -; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]] - -; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]] - -; SI-DENORM: buffer_store_dword [[RESULT]] -; VI-DENORM: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @fmuladd_a_2.0_b_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-FLUSH-LABEL: fmuladd_a_2.0_b_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s3, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s2, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mac_f32_e32 v3, 2.0, v2 +; SI-FLUSH-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-LABEL: fmuladd_a_2.0_b_f32: +; SI-DENORM-FASTFMA: ; %bb.0: +; SI-DENORM-FASTFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: v_fma_f32 v2, v2, 2.0, v3 +; SI-DENORM-FASTFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fmuladd_a_2.0_b_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v3 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; GFX9-FLUSH-MAD-LABEL: fmuladd_a_2.0_b_f32: +; GFX9-FLUSH-MAD: ; %bb.0: +; GFX9-FLUSH-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: v_mac_f32_e32 v2, 2.0, v1 +; GFX9-FLUSH-MAD-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-MAD-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-MAD-LABEL: fmuladd_a_2.0_b_f32: +; GFX9-DENORM-FASTFMA-MAD: ; %bb.0: +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_fma_f32 v1, v1, 2.0, v2 +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_endpgm +; +; GFX9-FLUSH-FMAC-LABEL: fmuladd_a_2.0_b_f32: +; GFX9-FLUSH-FMAC: ; %bb.0: +; GFX9-FLUSH-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: v_fmac_f32_e32 v2, 2.0, v1 +; GFX9-FLUSH-FMAC-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-FMAC-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-FMAC-LABEL: fmuladd_a_2.0_b_f32: +; GFX9-DENORM-FASTFMA-FMAC: ; %bb.0: +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_fmac_f32_e32 v2, 2.0, v1 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_endpgm +; +; GFX10-LABEL: fmuladd_a_2.0_b_f32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_fmac_f32_e32 v2, 2.0, v1 +; GFX10-NEXT: global_store_dword v0, v2, s[0:1] +; GFX10-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1 @@ -148,28 +809,126 @@ define amdgpu_kernel void @fmuladd_a_2.0_b_f32(ptr addrspace(1) %out, ptr addrsp ret void } -; GCN-LABEL: {{^}}fadd_a_a_b_f32: -; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]], -; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]], - -; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]] - -; SI-FLUSH: buffer_store_dword [[R2]] -; VI-FLUSH: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]] - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]] - -; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]] - -; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-STRICT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]] - -; SI-DENORM: buffer_store_dword [[RESULT]] -; VI-DENORM: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] -define amdgpu_kernel void @fadd_a_a_b_f32(ptr addrspace(1) %out, - ptr addrspace(1) %in1, - ptr addrspace(1) %in2) #0 { +define amdgpu_kernel void @fadd_a_a_b_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { +; SI-FLUSH-LABEL: fadd_a_a_b_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s3, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s2, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mac_f32_e32 v3, 2.0, v2 +; SI-FLUSH-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: fadd_a_a_b_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_add_f32_e32 v2, v2, v3 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fadd_a_a_b_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v3 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: fadd_a_a_b_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v2, v2, 2.0, v3 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: fadd_a_a_b_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v2, 2.0, v1 +; GFX9-FLUSH-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: fadd_a_a_b_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v1 +; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: fadd_a_a_b_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mac_f32_e32 v2, 2.0, v1 +; GFX10-FLUSH-NEXT: global_store_dword v0, v2, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: fadd_a_a_b_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v1 +; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1 @@ -184,28 +943,126 @@ define amdgpu_kernel void @fadd_a_a_b_f32(ptr addrspace(1) %out, ret void } -; GCN-LABEL: {{^}}fadd_b_a_a_f32: -; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]], -; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]], - -; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]] - -; SI-FLUSH: buffer_store_dword [[R2]] -; VI-FLUSH: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]] - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]] - -; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]] - -; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-STRICT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]] - -; SI-DENORM: buffer_store_dword [[RESULT]] -; VI-DENORM: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] -define amdgpu_kernel void @fadd_b_a_a_f32(ptr addrspace(1) %out, - ptr addrspace(1) %in1, - ptr addrspace(1) %in2) #0 { +define amdgpu_kernel void @fadd_b_a_a_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { +; SI-FLUSH-LABEL: fadd_b_a_a_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s3, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s2, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mac_f32_e32 v3, 2.0, v2 +; SI-FLUSH-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: fadd_b_a_a_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_add_f32_e32 v2, v3, v2 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fadd_b_a_a_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v3, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: fadd_b_a_a_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v2, v2, 2.0, v3 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: fadd_b_a_a_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v2, 2.0, v1 +; GFX9-FLUSH-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: fadd_b_a_a_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v1 +; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v2, v1 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: fadd_b_a_a_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mac_f32_e32 v2, 2.0, v1 +; GFX10-FLUSH-NEXT: global_store_dword v0, v2, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: fadd_b_a_a_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v1 +; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v2, v1 +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1 @@ -220,20 +1077,120 @@ define amdgpu_kernel void @fadd_b_a_a_f32(ptr addrspace(1) %out, ret void } -; GCN-LABEL: {{^}}fmuladd_neg_2.0_a_b_f32 -; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]], -; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]], -; GCN-FLUSH-MAD: v_mac_f32_e32 [[R2]], -2.0, [[R1]] -; GCN-FLUSH-FMAC: v_fmac_f32_e32 [[R2]], -2.0, [[R1]] - -; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]] - -; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-SLOWFMA: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]] - -; SI-DENORM: buffer_store_dword [[RESULT]] -; VI-DENORM: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @fmuladd_neg_2.0_a_b_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-FLUSH-LABEL: fmuladd_neg_2.0_a_b_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s3, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s2, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mac_f32_e32 v3, -2.0, v2 +; SI-FLUSH-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-LABEL: fmuladd_neg_2.0_a_b_f32: +; SI-DENORM-FASTFMA: ; %bb.0: +; SI-DENORM-FASTFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: v_fma_f32 v2, v2, -2.0, v3 +; SI-DENORM-FASTFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fmuladd_neg_2.0_a_b_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-SLOWFMA-NEXT: v_sub_f32_e32 v2, v3, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; GFX9-FLUSH-MAD-LABEL: fmuladd_neg_2.0_a_b_f32: +; GFX9-FLUSH-MAD: ; %bb.0: +; GFX9-FLUSH-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: v_mac_f32_e32 v2, -2.0, v1 +; GFX9-FLUSH-MAD-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-MAD-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-MAD-LABEL: fmuladd_neg_2.0_a_b_f32: +; GFX9-DENORM-FASTFMA-MAD: ; %bb.0: +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_fma_f32 v1, v1, -2.0, v2 +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_endpgm +; +; GFX9-FLUSH-FMAC-LABEL: fmuladd_neg_2.0_a_b_f32: +; GFX9-FLUSH-FMAC: ; %bb.0: +; GFX9-FLUSH-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: v_fmac_f32_e32 v2, -2.0, v1 +; GFX9-FLUSH-FMAC-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-FMAC-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-FMAC-LABEL: fmuladd_neg_2.0_a_b_f32: +; GFX9-DENORM-FASTFMA-FMAC: ; %bb.0: +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_fmac_f32_e32 v2, -2.0, v1 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_endpgm +; +; GFX10-LABEL: fmuladd_neg_2.0_a_b_f32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_fmac_f32_e32 v2, -2.0, v1 +; GFX10-NEXT: global_store_dword v0, v2, s[0:1] +; GFX10-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1 @@ -247,25 +1204,120 @@ define amdgpu_kernel void @fmuladd_neg_2.0_a_b_f32(ptr addrspace(1) %out, ptr ad ret void } -; XXX -; GCN-LABEL: {{^}}fmuladd_neg_2.0_neg_a_b_f32 -; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]], -; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]], - -; GCN-FLUSH-MAD: v_mac_f32_e32 [[R2]], 2.0, [[R1]] -; GCN-FLUSH-FMAC: v_fmac_f32_e32 [[R2]], 2.0, [[R1]] - -; SI-FLUSH: buffer_store_dword [[R2]] -; VI-FLUSH: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]] - -; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]] - -; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]] - -; SI-DENORM: buffer_store_dword [[RESULT]] -; VI-DENORM: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @fmuladd_neg_2.0_neg_a_b_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-FLUSH-LABEL: fmuladd_neg_2.0_neg_a_b_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s3, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s2, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mac_f32_e32 v3, 2.0, v2 +; SI-FLUSH-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-LABEL: fmuladd_neg_2.0_neg_a_b_f32: +; SI-DENORM-FASTFMA: ; %bb.0: +; SI-DENORM-FASTFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: v_fma_f32 v2, v2, 2.0, v3 +; SI-DENORM-FASTFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fmuladd_neg_2.0_neg_a_b_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v3, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; GFX9-FLUSH-MAD-LABEL: fmuladd_neg_2.0_neg_a_b_f32: +; GFX9-FLUSH-MAD: ; %bb.0: +; GFX9-FLUSH-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: v_mac_f32_e32 v2, 2.0, v1 +; GFX9-FLUSH-MAD-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-MAD-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-MAD-LABEL: fmuladd_neg_2.0_neg_a_b_f32: +; GFX9-DENORM-FASTFMA-MAD: ; %bb.0: +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_fma_f32 v1, v1, 2.0, v2 +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_endpgm +; +; GFX9-FLUSH-FMAC-LABEL: fmuladd_neg_2.0_neg_a_b_f32: +; GFX9-FLUSH-FMAC: ; %bb.0: +; GFX9-FLUSH-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: v_fmac_f32_e32 v2, 2.0, v1 +; GFX9-FLUSH-FMAC-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-FMAC-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-FMAC-LABEL: fmuladd_neg_2.0_neg_a_b_f32: +; GFX9-DENORM-FASTFMA-FMAC: ; %bb.0: +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_fmac_f32_e32 v2, 2.0, v1 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_endpgm +; +; GFX10-LABEL: fmuladd_neg_2.0_neg_a_b_f32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_fmac_f32_e32 v2, 2.0, v1 +; GFX10-NEXT: global_store_dword v0, v2, s[0:1] +; GFX10-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1 @@ -281,24 +1333,120 @@ define amdgpu_kernel void @fmuladd_neg_2.0_neg_a_b_f32(ptr addrspace(1) %out, pt ret void } -; GCN-LABEL: {{^}}fmuladd_2.0_neg_a_b_f32: -; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]], -; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]], - -; GCN-FLUSH-MAD: v_mac_f32_e32 [[R2]], -2.0, [[R1]] -; GCN-FLUSH-FMAC: v_fmac_f32_e32 [[R2]], -2.0, [[R1]] - -; SI-FLUSH: buffer_store_dword [[R2]] -; VI-FLUSH: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]] - -; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]] - -; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-SLOWFMA: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]] - -; SI-DENORM: buffer_store_dword [[RESULT]] -; VI-DENORM: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @fmuladd_2.0_neg_a_b_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-FLUSH-LABEL: fmuladd_2.0_neg_a_b_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s3, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s2, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mac_f32_e32 v3, -2.0, v2 +; SI-FLUSH-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-LABEL: fmuladd_2.0_neg_a_b_f32: +; SI-DENORM-FASTFMA: ; %bb.0: +; SI-DENORM-FASTFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: v_fma_f32 v2, v2, -2.0, v3 +; SI-DENORM-FASTFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fmuladd_2.0_neg_a_b_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-SLOWFMA-NEXT: v_sub_f32_e32 v2, v3, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; GFX9-FLUSH-MAD-LABEL: fmuladd_2.0_neg_a_b_f32: +; GFX9-FLUSH-MAD: ; %bb.0: +; GFX9-FLUSH-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: v_mac_f32_e32 v2, -2.0, v1 +; GFX9-FLUSH-MAD-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-MAD-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-MAD-LABEL: fmuladd_2.0_neg_a_b_f32: +; GFX9-DENORM-FASTFMA-MAD: ; %bb.0: +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-MAD-NEXT: v_fma_f32 v1, v1, -2.0, v2 +; GFX9-DENORM-FASTFMA-MAD-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-FASTFMA-MAD-NEXT: s_endpgm +; +; GFX9-FLUSH-FMAC-LABEL: fmuladd_2.0_neg_a_b_f32: +; GFX9-FLUSH-FMAC: ; %bb.0: +; GFX9-FLUSH-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: v_fmac_f32_e32 v2, -2.0, v1 +; GFX9-FLUSH-FMAC-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-FMAC-NEXT: s_endpgm +; +; GFX9-DENORM-FASTFMA-FMAC-LABEL: fmuladd_2.0_neg_a_b_f32: +; GFX9-DENORM-FASTFMA-FMAC: ; %bb.0: +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-FASTFMA-FMAC-NEXT: v_fmac_f32_e32 v2, -2.0, v1 +; GFX9-DENORM-FASTFMA-FMAC-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-DENORM-FASTFMA-FMAC-NEXT: s_endpgm +; +; GFX10-LABEL: fmuladd_2.0_neg_a_b_f32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_fmac_f32_e32 v2, -2.0, v1 +; GFX10-NEXT: global_store_dword v0, v2, s[0:1] +; GFX10-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1 @@ -314,23 +1462,107 @@ define amdgpu_kernel void @fmuladd_2.0_neg_a_b_f32(ptr addrspace(1) %out, ptr ad ret void } -; GCN-LABEL: {{^}}fmuladd_2.0_a_neg_b_f32: -; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]], -; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]], -; GCN-FLUSH-MAD: v_mad_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]] -; GCN-FLUSH-FMAC: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]] - -; SI-FLUSH: buffer_store_dword [[RESULT]] -; VI-FLUSH: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] - -; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]] - -; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-SLOWFMA: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]] - -; SI-DENORM: buffer_store_dword [[RESULT]] -; VI-DENORM: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @fmuladd_2.0_a_neg_b_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-FLUSH-LABEL: fmuladd_2.0_a_neg_b_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s3, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s2, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mad_f32 v2, v2, 2.0, -v3 +; SI-FLUSH-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-LABEL: fmuladd_2.0_a_neg_b_f32: +; SI-DENORM-FASTFMA: ; %bb.0: +; SI-DENORM-FASTFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-NEXT: v_fma_f32 v2, v2, 2.0, -v3 +; SI-DENORM-FASTFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fmuladd_2.0_a_neg_b_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-SLOWFMA-NEXT: v_sub_f32_e32 v2, v2, v3 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; GFX9-FLUSH-MAD-LABEL: fmuladd_2.0_a_neg_b_f32: +; GFX9-FLUSH-MAD: ; %bb.0: +; GFX9-FLUSH-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-MAD-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-MAD-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-MAD-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-MAD-NEXT: v_mad_f32 v1, v1, 2.0, -v2 +; GFX9-FLUSH-MAD-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-FLUSH-MAD-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: fmuladd_2.0_a_neg_b_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_fma_f32 v1, v1, 2.0, -v2 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX9-FLUSH-FMAC-LABEL: fmuladd_2.0_a_neg_b_f32: +; GFX9-FLUSH-FMAC: ; %bb.0: +; GFX9-FLUSH-FMAC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-FMAC-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-FMAC-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-FMAC-NEXT: v_fma_f32 v1, v1, 2.0, -v2 +; GFX9-FLUSH-FMAC-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-FLUSH-FMAC-NEXT: s_endpgm +; +; GFX10-LABEL: fmuladd_2.0_a_neg_b_f32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_fma_f32 v1, v1, 2.0, -v2 +; GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1 @@ -346,23 +1578,150 @@ define amdgpu_kernel void @fmuladd_2.0_a_neg_b_f32(ptr addrspace(1) %out, ptr ad ret void } -; GCN-LABEL: {{^}}mad_sub_f32: -; GCN: {{buffer|flat|global}}_load_dword [[REGA:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGB:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGC:v[0-9]+]] -; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]] - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]] - -; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]] -; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]] - -; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]] -; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]] - -; SI: buffer_store_dword [[RESULT]] -; VI: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @mad_sub_f32(ptr addrspace(1) noalias nocapture %out, ptr addrspace(1) noalias nocapture readonly %ptr) #0 { +; SI-FLUSH-LABEL: mad_sub_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s7, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s6, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-FLUSH-NEXT: v_mad_f32 v2, v2, v3, -v4 +; SI-FLUSH-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: mad_sub_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_sub_f32_e32 v2, v2, v4 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: mad_sub_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-SLOWFMA-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-DENORM-SLOWFMA-NEXT: v_sub_f32_e32 v2, v2, v4 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: mad_sub_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v2, v2, v3, -v4 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: mad_sub_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mad_f32 v1, v1, v2, -v3 +; GFX9-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: mad_sub_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v3 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: mad_sub_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mad_f32 v1, v1, v2, -v3 +; GFX10-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: mad_sub_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX10-DENORM-NEXT: v_sub_f32_e32 v1, v1, v3 +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, ptr addrspace(1) %ptr, i64 %tid.ext @@ -380,24 +1739,150 @@ define amdgpu_kernel void @mad_sub_f32(ptr addrspace(1) noalias nocapture %out, ret void } -; GCN-LABEL: {{^}}mad_sub_inv_f32: -; GCN: {{buffer|flat|global}}_load_dword [[REGA:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGB:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGC:v[0-9]+]] - -; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]] - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]] - -; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]] -; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]] - -; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]] -; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]] - -; SI: buffer_store_dword [[RESULT]] -; VI: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @mad_sub_inv_f32(ptr addrspace(1) noalias nocapture %out, ptr addrspace(1) noalias nocapture readonly %ptr) #0 { +; SI-FLUSH-LABEL: mad_sub_inv_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s7, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s6, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-FLUSH-NEXT: v_mad_f32 v2, -v2, v3, v4 +; SI-FLUSH-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: mad_sub_inv_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_sub_f32_e32 v2, v4, v2 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: mad_sub_inv_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-SLOWFMA-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-DENORM-SLOWFMA-NEXT: v_sub_f32_e32 v2, v4, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: mad_sub_inv_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v2, -v2, v3, v4 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: mad_sub_inv_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mad_f32 v1, -v1, v2, v3 +; GFX9-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: mad_sub_inv_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v1 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: mad_sub_inv_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mad_f32 v1, -v1, v2, v3 +; GFX10-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: mad_sub_inv_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX10-DENORM-NEXT: v_sub_f32_e32 v1, v3, v1 +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, ptr addrspace(1) %ptr, i64 %tid.ext @@ -415,23 +1900,150 @@ define amdgpu_kernel void @mad_sub_inv_f32(ptr addrspace(1) noalias nocapture %o ret void } -; GCN-LABEL: {{^}}mad_sub_fabs_f32: -; GCN: {{buffer|flat|global}}_load_dword [[REGA:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGB:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGC:v[0-9]+]] -; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]| - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]| - -; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]] -; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e64 [[RESULT:v[0-9]+]], [[TMP]], |[[REGC]]| - -; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]] -; GCN-DENORM-STRICT: v_sub_f32_e64 [[RESULT:v[0-9]+]], [[TMP]], |[[REGC]]| - -; SI: buffer_store_dword [[RESULT]] -; VI: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @mad_sub_fabs_f32(ptr addrspace(1) noalias nocapture %out, ptr addrspace(1) noalias nocapture readonly %ptr) #0 { +; SI-FLUSH-LABEL: mad_sub_fabs_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s7, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s6, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-FLUSH-NEXT: v_mad_f32 v2, v2, v3, -|v4| +; SI-FLUSH-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: mad_sub_fabs_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_sub_f32_e64 v2, v2, |v4| +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: mad_sub_fabs_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-SLOWFMA-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-DENORM-SLOWFMA-NEXT: v_sub_f32_e64 v2, v2, |v4| +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: mad_sub_fabs_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v2, v2, v3, -|v4| +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: mad_sub_fabs_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mad_f32 v1, v1, v2, -|v3| +; GFX9-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: mad_sub_fabs_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX9-DENORM-NEXT: v_sub_f32_e64 v1, v1, |v3| +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: mad_sub_fabs_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mad_f32 v1, v1, v2, -|v3| +; GFX10-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: mad_sub_fabs_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX10-DENORM-NEXT: v_sub_f32_e64 v1, v1, |v3| +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, ptr addrspace(1) %ptr, i64 %tid.ext @@ -450,24 +2062,150 @@ define amdgpu_kernel void @mad_sub_fabs_f32(ptr addrspace(1) noalias nocapture % ret void } -; GCN-LABEL: {{^}}mad_sub_fabs_inv_f32: -; GCN: {{buffer|flat|global}}_load_dword [[REGA:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGB:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGC:v[0-9]+]] -; GCN-FLUSH-MAD: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]| -; GCN-FLUSH-FMA: v_fma_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]| - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]| - -; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]] -; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e64 [[RESULT:v[0-9]+]], |[[REGC]]|, [[TMP]] - -; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]] -; GCN-DENORM-STRICT: v_sub_f32_e64 [[RESULT:v[0-9]+]], |[[REGC]]|, [[TMP]] - -; SI: buffer_store_dword [[RESULT]] -; VI: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @mad_sub_fabs_inv_f32(ptr addrspace(1) noalias nocapture %out, ptr addrspace(1) noalias nocapture readonly %ptr) #0 { +; SI-FLUSH-LABEL: mad_sub_fabs_inv_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s7, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s6, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-FLUSH-NEXT: v_mad_f32 v2, -v2, v3, |v4| +; SI-FLUSH-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: mad_sub_fabs_inv_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_sub_f32_e64 v2, |v4|, v2 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: mad_sub_fabs_inv_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-SLOWFMA-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-DENORM-SLOWFMA-NEXT: v_sub_f32_e64 v2, |v4|, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: mad_sub_fabs_inv_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v2, -v2, v3, |v4| +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: mad_sub_fabs_inv_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mad_f32 v1, -v1, v2, |v3| +; GFX9-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: mad_sub_fabs_inv_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX9-DENORM-NEXT: v_sub_f32_e64 v1, |v3|, v1 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: mad_sub_fabs_inv_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mad_f32 v1, -v1, v2, |v3| +; GFX10-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: mad_sub_fabs_inv_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX10-DENORM-NEXT: v_sub_f32_e64 v1, |v3|, v1 +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, ptr addrspace(1) %ptr, i64 %tid.ext @@ -486,26 +2224,150 @@ define amdgpu_kernel void @mad_sub_fabs_inv_f32(ptr addrspace(1) noalias nocaptu ret void } -; GCN-LABEL: {{^}}neg_neg_mad_f32: -; GCN: {{buffer|flat|global}}_load_dword [[REGA:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGB:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGC:v[0-9]+]] - -; GCN-FLUSH: v_mac_f32_e32 [[REGC]], [[REGA]], [[REGB]] -; SI-FLUSH: buffer_store_dword [[REGC]] -; VI-FLUSH: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REGC]] - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], [[REGC]] - -; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]] -; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]] - -; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]] -; GCN-DENORM-STRICT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]] - -; SI-DENORM: buffer_store_dword [[RESULT]] -; VI-DENORM: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @neg_neg_mad_f32(ptr addrspace(1) noalias nocapture %out, ptr addrspace(1) noalias nocapture readonly %ptr) #0 { +; SI-FLUSH-LABEL: neg_neg_mad_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s7, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s6, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-FLUSH-NEXT: v_mac_f32_e32 v4, v2, v3 +; SI-FLUSH-NEXT: buffer_store_dword v4, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: neg_neg_mad_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_add_f32_e32 v2, v4, v2 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: neg_neg_mad_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-SLOWFMA-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v4, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: neg_neg_mad_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v2, v2, v3, v4 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: neg_neg_mad_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v3, v1, v2 +; GFX9-FLUSH-NEXT: global_store_dword v0, v3, s[0:1] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: neg_neg_mad_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v3, v1 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: neg_neg_mad_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mac_f32_e32 v3, v1, v2 +; GFX10-FLUSH-NEXT: global_store_dword v0, v3, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: neg_neg_mad_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v3, v1 +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, ptr addrspace(1) %ptr, i64 %tid.ext @@ -525,23 +2387,150 @@ define amdgpu_kernel void @neg_neg_mad_f32(ptr addrspace(1) noalias nocapture %o ret void } -; GCN-LABEL: {{^}}mad_fabs_sub_f32: -; GCN: {{buffer|flat|global}}_load_dword [[REGA:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGB:v[0-9]+]] -; GCN: {{buffer|flat|global}}_load_dword [[REGC:v[0-9]+]] -; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]] - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]] - -; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e64 [[TMP:v[0-9]+]], [[REGA]], |[[REGB]]| -; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]] - -; GCN-DENORM-STRICT: v_mul_f32_e64 [[TMP:v[0-9]+]], [[REGA]], |[[REGB]]| -; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]] - -; SI: buffer_store_dword [[RESULT]] -; VI: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @mad_fabs_sub_f32(ptr addrspace(1) noalias nocapture %out, ptr addrspace(1) noalias nocapture readonly %ptr) #0 { +; SI-FLUSH-LABEL: mad_fabs_sub_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s7, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s6, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-FLUSH-NEXT: v_mad_f32 v2, v2, |v3|, -v4 +; SI-FLUSH-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: mad_fabs_sub_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mul_f32_e64 v2, v2, |v3| +; SI-DENORM-FASTFMA-STRICT-NEXT: v_sub_f32_e32 v2, v2, v4 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: mad_fabs_sub_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-SLOWFMA-NEXT: v_mul_f32_e64 v2, v2, |v3| +; SI-DENORM-SLOWFMA-NEXT: v_sub_f32_e32 v2, v2, v4 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: mad_fabs_sub_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s7, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s6, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64 offset:8 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v2, v2, |v3|, -v4 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: mad_fabs_sub_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mad_f32 v1, v1, |v2|, -v3 +; GFX9-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: mad_fabs_sub_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_mul_f32_e64 v1, v1, |v2| +; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v3 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: mad_fabs_sub_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mad_f32 v1, v1, |v2|, -v3 +; GFX10-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: mad_fabs_sub_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[2:3] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[2:3] offset:4 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v3, v0, s[2:3] offset:8 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_mul_f32_e64 v1, v1, |v2| +; GFX10-DENORM-NEXT: v_sub_f32_e32 v1, v1, v3 +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, ptr addrspace(1) %ptr, i64 %tid.ext @@ -560,24 +2549,126 @@ define amdgpu_kernel void @mad_fabs_sub_f32(ptr addrspace(1) noalias nocapture % ret void } -; GCN-LABEL: {{^}}fsub_c_fadd_a_a_f32: -; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]], -; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]], -; GCN-FLUSH: v_mac_f32_e32 [[R2]], -2.0, [[R1]] -; SI-FLUSH: buffer_store_dword [[R2]] -; VI-FLUSH: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]] - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]] - -; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]] - -; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]] - -; SI-DENORM: buffer_store_dword [[RESULT]] -; VI-DENORM: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @fsub_c_fadd_a_a_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-FLUSH-LABEL: fsub_c_fadd_a_a_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s3, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s2, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mac_f32_e32 v3, -2.0, v2 +; SI-FLUSH-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: fsub_c_fadd_a_a_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_sub_f32_e32 v2, v3, v2 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fsub_c_fadd_a_a_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-SLOWFMA-NEXT: v_sub_f32_e32 v2, v3, v2 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: fsub_c_fadd_a_a_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v2, v2, -2.0, v3 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: fsub_c_fadd_a_a_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v2, -2.0, v1 +; GFX9-FLUSH-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: fsub_c_fadd_a_a_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v1 +; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v2, v1 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: fsub_c_fadd_a_a_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mac_f32_e32 v2, -2.0, v1 +; GFX10-FLUSH-NEXT: global_store_dword v0, v2, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: fsub_c_fadd_a_a_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v1 +; GFX10-DENORM-NEXT: v_sub_f32_e32 v1, v2, v1 +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1 @@ -593,22 +2684,126 @@ define amdgpu_kernel void @fsub_c_fadd_a_a_f32(ptr addrspace(1) %out, ptr addrsp ret void } -; GCN-LABEL: {{^}}fsub_fadd_a_a_c_f32: -; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]], -; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]], -; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]] - -; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]] - -; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]] - -; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]] -; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]] - -; SI: buffer_store_dword [[RESULT]] -; VI: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @fsub_fadd_a_a_c_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +; SI-FLUSH-LABEL: fsub_fadd_a_a_c_f32: +; SI-FLUSH: ; %bb.0: +; SI-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-FLUSH-NEXT: s_mov_b32 s3, 0xf000 +; SI-FLUSH-NEXT: s_mov_b32 s2, 0 +; SI-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-FLUSH-NEXT: v_mov_b32_e32 v1, 0 +; SI-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-FLUSH-NEXT: s_waitcnt vmcnt(0) +; SI-FLUSH-NEXT: v_mad_f32 v2, v2, 2.0, -v3 +; SI-FLUSH-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-FLUSH-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-STRICT-LABEL: fsub_fadd_a_a_c_f32: +; SI-DENORM-FASTFMA-STRICT: ; %bb.0: +; SI-DENORM-FASTFMA-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-STRICT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-STRICT-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-FASTFMA-STRICT-NEXT: v_sub_f32_e32 v2, v2, v3 +; SI-DENORM-FASTFMA-STRICT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-STRICT-NEXT: s_endpgm +; +; SI-DENORM-SLOWFMA-LABEL: fsub_fadd_a_a_c_f32: +; SI-DENORM-SLOWFMA: ; %bb.0: +; SI-DENORM-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-SLOWFMA-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-SLOWFMA-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-SLOWFMA-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-SLOWFMA-NEXT: v_add_f32_e32 v2, v2, v2 +; SI-DENORM-SLOWFMA-NEXT: v_sub_f32_e32 v2, v2, v3 +; SI-DENORM-SLOWFMA-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-SLOWFMA-NEXT: s_endpgm +; +; SI-DENORM-FASTFMA-CONTRACT-LABEL: fsub_fadd_a_a_c_f32: +; SI-DENORM-FASTFMA-CONTRACT: ; %bb.0: +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s3, 0xf000 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_mov_b32 s2, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_mov_b32_e32 v1, 0 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt lgkmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_waitcnt vmcnt(0) +; SI-DENORM-FASTFMA-CONTRACT-NEXT: v_fma_f32 v2, v2, 2.0, -v3 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-DENORM-FASTFMA-CONTRACT-NEXT: s_endpgm +; +; GFX9-FLUSH-LABEL: fsub_fadd_a_a_c_f32: +; GFX9-FLUSH: ; %bb.0: +; GFX9-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLUSH-NEXT: v_mad_f32 v1, v1, 2.0, -v2 +; GFX9-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-FLUSH-NEXT: s_endpgm +; +; GFX9-DENORM-LABEL: fsub_fadd_a_a_c_f32: +; GFX9-DENORM: ; %bb.0: +; GFX9-DENORM-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc +; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v1 +; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v2 +; GFX9-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-DENORM-NEXT: s_endpgm +; +; GFX10-FLUSH-LABEL: fsub_fadd_a_a_c_f32: +; GFX10-FLUSH: ; %bb.0: +; GFX10-FLUSH-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-FLUSH-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) +; GFX10-FLUSH-NEXT: v_mad_f32 v1, v1, 2.0, -v2 +; GFX10-FLUSH-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-FLUSH-NEXT: s_endpgm +; +; GFX10-DENORM-LABEL: fsub_fadd_a_a_c_f32: +; GFX10-DENORM: ; %bb.0: +; GFX10-DENORM-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10-DENORM-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v1, v0, s[0:1] glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc dlc +; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) +; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v1 +; GFX10-DENORM-NEXT: v_sub_f32_e32 v1, v1, v2 +; GFX10-DENORM-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DENORM-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1 diff --git a/llvm/test/CodeGen/AMDGPU/kernel-args.ll b/llvm/test/CodeGen/AMDGPU/kernel-args.ll index bad2e60..a2da887 100644 --- a/llvm/test/CodeGen/AMDGPU/kernel-args.ll +++ b/llvm/test/CodeGen/AMDGPU/kernel-args.ll @@ -1025,67 +1025,74 @@ define amdgpu_kernel void @v3i16_arg(ptr addrspace(1) nocapture %out, <3 x i16> ; ; EG-LABEL: v3i16_arg: ; EG: ; %bb.0: ; %entry -; EG-NEXT: ALU 0, @10, KC0[], KC1[] -; EG-NEXT: TEX 1 @6 -; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T3.X, 0 -; EG-NEXT: MEM_RAT MSKOR T2.XW, T0.X +; EG-NEXT: ALU 0, @12, KC0[], KC1[] +; EG-NEXT: TEX 2 @6 +; EG-NEXT: ALU 19, @13, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T7.X, 0 +; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X ; EG-NEXT: CF_END ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_16 T1.X, T0.X, 44, #3 -; EG-NEXT: VTX_READ_16 T0.X, T0.X, 48, #3 -; EG-NEXT: ALU clause starting at 10: -; EG-NEXT: MOV * T0.X, 0.0, -; EG-NEXT: ALU clause starting at 11: +; EG-NEXT: VTX_READ_16 T6.X, T5.X, 44, #3 +; EG-NEXT: VTX_READ_16 T7.X, T5.X, 46, #3 +; EG-NEXT: VTX_READ_16 T5.X, T5.X, 48, #3 +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T5.X, 0.0, +; EG-NEXT: ALU clause starting at 13: ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, ; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00) ; EG-NEXT: AND_INT T1.W, PV.W, literal.x, -; EG-NEXT: AND_INT * T2.W, T0.X, literal.y, +; EG-NEXT: AND_INT * T2.W, T5.X, literal.y, ; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41) ; EG-NEXT: LSHL * T1.W, PV.W, literal.x, ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) -; EG-NEXT: LSHL T2.X, T2.W, PV.W, -; EG-NEXT: LSHL * T2.W, literal.x, PV.W, +; EG-NEXT: LSHL T5.X, T2.W, PV.W, +; EG-NEXT: LSHL * T5.W, literal.x, PV.W, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: MOV T2.Y, 0.0, -; EG-NEXT: MOV * T2.Z, 0.0, -; EG-NEXT: LSHR T0.X, T0.W, literal.x, -; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, +; EG-NEXT: MOV T5.Y, 0.0, +; EG-NEXT: MOV * T5.Z, 0.0, +; EG-NEXT: LSHR T8.X, T0.W, literal.x, +; EG-NEXT: LSHL T0.W, T7.X, literal.y, +; EG-NEXT: AND_INT * T1.W, T6.X, literal.z, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT T6.X, PV.W, PS, +; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; ; CM-LABEL: v3i16_arg: ; CM: ; %bb.0: ; %entry ; CM-NEXT: ALU 0, @12, KC0[], KC1[] -; CM-NEXT: TEX 0 @8 -; CM-NEXT: ALU 13, @13, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT MSKOR T1.XW, T2.X -; CM-NEXT: ALU 1, @27, KC0[CB0:0-32], KC1[] -; CM-NEXT: TEX 0 @10 -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: TEX 2 @6 +; CM-NEXT: ALU 19, @13, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT MSKOR T5.XW, T8.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T6.X, T7.X ; CM-NEXT: CF_END -; CM-NEXT: Fetch clause starting at 8: -; CM-NEXT: VTX_READ_16 T1.X, T0.X, 48, #3 -; CM-NEXT: Fetch clause starting at 10: -; CM-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3 +; CM-NEXT: Fetch clause starting at 6: +; CM-NEXT: VTX_READ_16 T6.X, T5.X, 44, #3 +; CM-NEXT: VTX_READ_16 T7.X, T5.X, 46, #3 +; CM-NEXT: VTX_READ_16 T5.X, T5.X, 48, #3 ; CM-NEXT: ALU clause starting at 12: -; CM-NEXT: MOV * T0.X, 0.0, +; CM-NEXT: MOV * T5.X, 0.0, ; CM-NEXT: ALU clause starting at 13: ; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, ; CM-NEXT: 4(5.605194e-45), 0(0.000000e+00) ; CM-NEXT: AND_INT * T1.W, PV.W, literal.x, ; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00) -; CM-NEXT: AND_INT T0.Z, T1.X, literal.x, +; CM-NEXT: AND_INT T0.Z, T5.X, literal.x, ; CM-NEXT: LSHL * T1.W, PV.W, literal.y, ; CM-NEXT: 65535(9.183409e-41), 3(4.203895e-45) -; CM-NEXT: LSHL T1.X, PV.Z, PV.W, -; CM-NEXT: LSHL * T1.W, literal.x, PV.W, +; CM-NEXT: LSHL T5.X, PV.Z, PV.W, +; CM-NEXT: LSHL * T5.W, literal.x, PV.W, ; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; CM-NEXT: MOV T1.Y, 0.0, -; CM-NEXT: MOV * T1.Z, 0.0, -; CM-NEXT: LSHR * T2.X, T0.W, literal.x, +; CM-NEXT: MOV T5.Y, 0.0, +; CM-NEXT: MOV * T5.Z, 0.0, +; CM-NEXT: LSHL T0.Z, T7.X, literal.x, +; CM-NEXT: AND_INT * T1.W, T6.X, literal.y, BS:VEC_120/SCL_212 +; CM-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T6.X, PV.Z, PV.W, +; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; CM-NEXT: ALU clause starting at 27: -; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: LSHR * T8.X, T0.W, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) entry: store <3 x i16> %in, ptr addrspace(1) %out, align 4 @@ -2669,47 +2676,205 @@ define amdgpu_kernel void @v8i16_arg(ptr addrspace(1) %out, <8 x i16> %in) { ; ; EG-LABEL: v8i16_arg: ; EG: ; %bb.0: ; %entry -; EG-NEXT: ALU 0, @14, KC0[], KC1[] -; EG-NEXT: TEX 3 @6 -; EG-NEXT: ALU 4, @15, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1 +; EG-NEXT: ALU 1, @36, KC0[], KC1[] +; EG-NEXT: TEX 0 @20 +; EG-NEXT: ALU 5, @38, KC0[], KC1[] +; EG-NEXT: TEX 0 @22 +; EG-NEXT: ALU 5, @44, KC0[], KC1[] +; EG-NEXT: TEX 0 @24 +; EG-NEXT: ALU 5, @50, KC0[], KC1[] +; EG-NEXT: TEX 0 @26 +; EG-NEXT: ALU 5, @56, KC0[], KC1[] +; EG-NEXT: TEX 0 @28 +; EG-NEXT: ALU 5, @62, KC0[], KC1[] +; EG-NEXT: TEX 0 @30 +; EG-NEXT: ALU 5, @68, KC0[], KC1[] +; EG-NEXT: TEX 0 @32 +; EG-NEXT: ALU 5, @74, KC0[], KC1[] +; EG-NEXT: TEX 0 @34 +; EG-NEXT: ALU 8, @80, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T8.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD -; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_16 T1.X, T0.X, 52, #3 -; EG-NEXT: VTX_READ_16 T2.X, T0.X, 54, #3 -; EG-NEXT: VTX_READ_16 T3.X, T0.X, 62, #3 -; EG-NEXT: VTX_READ_16 T0.X, T0.X, 60, #3 -; EG-NEXT: ALU clause starting at 14: -; EG-NEXT: MOV * T0.X, 0.0, -; EG-NEXT: ALU clause starting at 15: -; EG-NEXT: MOV T1.Y, T2.X, -; EG-NEXT: MOV * T1.Z, T0.X, BS:VEC_120/SCL_212 -; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x, -; EG-NEXT: MOV * T1.W, T3.X, -; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: Fetch clause starting at 20: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 66, #3 +; EG-NEXT: Fetch clause starting at 22: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 58, #3 +; EG-NEXT: Fetch clause starting at 24: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 64, #3 +; EG-NEXT: Fetch clause starting at 26: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 56, #3 +; EG-NEXT: Fetch clause starting at 28: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 62, #3 +; EG-NEXT: Fetch clause starting at 30: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 54, #3 +; EG-NEXT: Fetch clause starting at 32: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 60, #3 +; EG-NEXT: Fetch clause starting at 34: +; EG-NEXT: VTX_READ_16 T7.X, T7.X, 52, #3 +; EG-NEXT: ALU clause starting at 36: +; EG-NEXT: MOV * T0.Y, T3.X, +; EG-NEXT: MOV * T7.X, 0.0, +; EG-NEXT: ALU clause starting at 38: +; EG-NEXT: LSHL T0.W, T8.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV T3.X, PV.W, +; EG-NEXT: MOV * T0.Y, T5.X, +; EG-NEXT: ALU clause starting at 44: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T1.W, T8.X, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T0.Y, T3.X, +; EG-NEXT: ALU clause starting at 50: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, T8.X, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T3.X, PV.W, +; EG-NEXT: MOV * T0.Y, T5.X, +; EG-NEXT: ALU clause starting at 56: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, T8.X, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T0.Y, T2.X, +; EG-NEXT: ALU clause starting at 62: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T1.W, T8.X, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T2.X, PV.W, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: ALU clause starting at 68: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T1.W, T8.X, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV * T0.Y, T2.X, +; EG-NEXT: ALU clause starting at 74: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, T8.X, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T7.Z, PV.W, PS, +; EG-NEXT: MOV T2.X, PV.Z, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: ALU clause starting at 80: +; EG-NEXT: LSHR T8.X, KC0[2].Y, literal.x, +; EG-NEXT: AND_INT T0.W, T0.Y, literal.y, +; EG-NEXT: AND_INT * T1.W, T7.X, literal.z, +; EG-NEXT: 2(2.802597e-45), -65536(nan) +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T7.X, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.X, +; EG-NEXT: MOV * T7.W, T3.X, +; EG-NEXT: MOV * T7.Y, T5.X, ; ; CM-LABEL: v8i16_arg: ; CM: ; %bb.0: ; %entry -; CM-NEXT: ALU 0, @14, KC0[], KC1[] -; CM-NEXT: TEX 3 @6 -; CM-NEXT: ALU 4, @15, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X +; CM-NEXT: ALU 1, @36, KC0[], KC1[] +; CM-NEXT: TEX 0 @20 +; CM-NEXT: ALU 5, @38, KC0[], KC1[] +; CM-NEXT: TEX 0 @22 +; CM-NEXT: ALU 5, @44, KC0[], KC1[] +; CM-NEXT: TEX 0 @24 +; CM-NEXT: ALU 5, @50, KC0[], KC1[] +; CM-NEXT: TEX 0 @26 +; CM-NEXT: ALU 5, @56, KC0[], KC1[] +; CM-NEXT: TEX 0 @28 +; CM-NEXT: ALU 5, @62, KC0[], KC1[] +; CM-NEXT: TEX 0 @30 +; CM-NEXT: ALU 5, @68, KC0[], KC1[] +; CM-NEXT: TEX 0 @32 +; CM-NEXT: ALU 5, @74, KC0[], KC1[] +; CM-NEXT: TEX 0 @34 +; CM-NEXT: ALU 8, @80, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T7, T8.X ; CM-NEXT: CF_END ; CM-NEXT: PAD -; CM-NEXT: Fetch clause starting at 6: -; CM-NEXT: VTX_READ_16 T1.X, T0.X, 52, #3 -; CM-NEXT: VTX_READ_16 T2.X, T0.X, 54, #3 -; CM-NEXT: VTX_READ_16 T3.X, T0.X, 62, #3 -; CM-NEXT: VTX_READ_16 T0.X, T0.X, 60, #3 -; CM-NEXT: ALU clause starting at 14: -; CM-NEXT: MOV * T0.X, 0.0, -; CM-NEXT: ALU clause starting at 15: -; CM-NEXT: MOV T1.Y, T2.X, -; CM-NEXT: MOV * T1.Z, T0.X, BS:VEC_120/SCL_212 -; CM-NEXT: LSHR T0.X, KC0[2].Y, literal.x, -; CM-NEXT: MOV * T1.W, T3.X, -; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: Fetch clause starting at 20: +; CM-NEXT: VTX_READ_16 T8.X, T7.X, 66, #3 +; CM-NEXT: Fetch clause starting at 22: +; CM-NEXT: VTX_READ_16 T8.X, T7.X, 58, #3 +; CM-NEXT: Fetch clause starting at 24: +; CM-NEXT: VTX_READ_16 T8.X, T7.X, 64, #3 +; CM-NEXT: Fetch clause starting at 26: +; CM-NEXT: VTX_READ_16 T8.X, T7.X, 56, #3 +; CM-NEXT: Fetch clause starting at 28: +; CM-NEXT: VTX_READ_16 T8.X, T7.X, 62, #3 +; CM-NEXT: Fetch clause starting at 30: +; CM-NEXT: VTX_READ_16 T8.X, T7.X, 54, #3 +; CM-NEXT: Fetch clause starting at 32: +; CM-NEXT: VTX_READ_16 T8.X, T7.X, 60, #3 +; CM-NEXT: Fetch clause starting at 34: +; CM-NEXT: VTX_READ_16 T7.X, T7.X, 52, #3 +; CM-NEXT: ALU clause starting at 36: +; CM-NEXT: MOV * T0.Y, T3.X, +; CM-NEXT: MOV * T7.X, 0.0, +; CM-NEXT: ALU clause starting at 38: +; CM-NEXT: LSHL T0.Z, T8.X, literal.x, +; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y, +; CM-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z, +; CM-NEXT: MOV T3.X, PV.W, +; CM-NEXT: MOV * T0.Y, T5.X, +; CM-NEXT: ALU clause starting at 44: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T8.X, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T5.X, PV.W, +; CM-NEXT: MOV * T0.Y, T3.X, +; CM-NEXT: ALU clause starting at 50: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, T8.X, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T3.X, PV.W, +; CM-NEXT: MOV * T0.Y, T5.X, +; CM-NEXT: ALU clause starting at 56: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, T8.X, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T5.X, PV.W, +; CM-NEXT: MOV * T0.Y, T2.X, +; CM-NEXT: ALU clause starting at 62: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T8.X, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T2.X, PV.W, +; CM-NEXT: MOV * T0.Y, T4.X, +; CM-NEXT: ALU clause starting at 68: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T8.X, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.W, +; CM-NEXT: MOV * T0.Y, T2.X, +; CM-NEXT: ALU clause starting at 74: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, T8.X, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T7.Z, PV.Z, PV.W, +; CM-NEXT: MOV T2.X, PV.Z, +; CM-NEXT: MOV * T0.Y, T4.X, +; CM-NEXT: ALU clause starting at 80: +; CM-NEXT: LSHR T8.X, KC0[2].Y, literal.x, +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.y, +; CM-NEXT: AND_INT * T0.W, T7.X, literal.z, +; CM-NEXT: 2(2.802597e-45), -65536(nan) +; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; CM-NEXT: OR_INT * T7.X, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.X, +; CM-NEXT: MOV * T7.W, T3.X, +; CM-NEXT: MOV * T7.Y, T5.X, entry: store <8 x i16> %in, ptr addrspace(1) %out ret void @@ -3453,68 +3618,392 @@ define amdgpu_kernel void @v16i16_arg(ptr addrspace(1) %out, <16 x i16> %in) { ; ; EG-LABEL: v16i16_arg: ; EG: ; %bb.0: ; %entry -; EG-NEXT: ALU 0, @22, KC0[], KC1[] -; EG-NEXT: TEX 7 @6 -; EG-NEXT: ALU 10, @23, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T0.X, 1 +; EG-NEXT: ALU 1, @68, KC0[], KC1[] +; EG-NEXT: TEX 0 @36 +; EG-NEXT: ALU 5, @70, KC0[], KC1[] +; EG-NEXT: TEX 0 @38 +; EG-NEXT: ALU 5, @76, KC0[], KC1[] +; EG-NEXT: TEX 0 @40 +; EG-NEXT: ALU 5, @82, KC0[], KC1[] +; EG-NEXT: TEX 0 @42 +; EG-NEXT: ALU 5, @88, KC0[], KC1[] +; EG-NEXT: TEX 0 @44 +; EG-NEXT: ALU 5, @94, KC0[], KC1[] +; EG-NEXT: TEX 0 @46 +; EG-NEXT: ALU 5, @100, KC0[], KC1[] +; EG-NEXT: TEX 0 @48 +; EG-NEXT: ALU 5, @106, KC0[], KC1[] +; EG-NEXT: TEX 0 @50 +; EG-NEXT: ALU 5, @112, KC0[], KC1[] +; EG-NEXT: TEX 0 @52 +; EG-NEXT: ALU 5, @118, KC0[], KC1[] +; EG-NEXT: TEX 0 @54 +; EG-NEXT: ALU 5, @124, KC0[], KC1[] +; EG-NEXT: TEX 0 @56 +; EG-NEXT: ALU 5, @130, KC0[], KC1[] +; EG-NEXT: TEX 0 @58 +; EG-NEXT: ALU 5, @136, KC0[], KC1[] +; EG-NEXT: TEX 0 @60 +; EG-NEXT: ALU 5, @142, KC0[], KC1[] +; EG-NEXT: TEX 0 @62 +; EG-NEXT: ALU 5, @148, KC0[], KC1[] +; EG-NEXT: TEX 0 @64 +; EG-NEXT: ALU 5, @154, KC0[], KC1[] +; EG-NEXT: TEX 0 @66 +; EG-NEXT: ALU 13, @160, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T14.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T13.X, 1 ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_16 T1.X, T0.X, 84, #3 -; EG-NEXT: VTX_READ_16 T2.X, T0.X, 86, #3 -; EG-NEXT: VTX_READ_16 T3.X, T0.X, 94, #3 -; EG-NEXT: VTX_READ_16 T4.X, T0.X, 78, #3 -; EG-NEXT: VTX_READ_16 T5.X, T0.X, 76, #3 -; EG-NEXT: VTX_READ_16 T6.X, T0.X, 92, #3 -; EG-NEXT: VTX_READ_16 T7.X, T0.X, 68, #3 -; EG-NEXT: VTX_READ_16 T0.X, T0.X, 70, #3 -; EG-NEXT: ALU clause starting at 22: -; EG-NEXT: MOV * T0.X, 0.0, -; EG-NEXT: ALU clause starting at 23: -; EG-NEXT: MOV T1.Y, T2.X, -; EG-NEXT: MOV * T7.Y, T0.X, -; EG-NEXT: MOV * T1.Z, T6.X, -; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x, -; EG-NEXT: MOV T7.Z, T5.X, +; EG-NEXT: Fetch clause starting at 36: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 98, #3 +; EG-NEXT: Fetch clause starting at 38: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 90, #3 +; EG-NEXT: Fetch clause starting at 40: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 82, #3 +; EG-NEXT: Fetch clause starting at 42: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 74, #3 +; EG-NEXT: Fetch clause starting at 44: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 96, #3 +; EG-NEXT: Fetch clause starting at 46: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 88, #3 +; EG-NEXT: Fetch clause starting at 48: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 80, #3 +; EG-NEXT: Fetch clause starting at 50: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 72, #3 +; EG-NEXT: Fetch clause starting at 52: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 94, #3 +; EG-NEXT: Fetch clause starting at 54: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 86, #3 +; EG-NEXT: Fetch clause starting at 56: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 78, #3 +; EG-NEXT: Fetch clause starting at 58: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 70, #3 +; EG-NEXT: Fetch clause starting at 60: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 92, #3 +; EG-NEXT: Fetch clause starting at 62: +; EG-NEXT: VTX_READ_16 T12.X, T11.X, 84, #3 +; EG-NEXT: Fetch clause starting at 64: +; EG-NEXT: VTX_READ_16 T13.X, T11.X, 76, #3 +; EG-NEXT: Fetch clause starting at 66: +; EG-NEXT: VTX_READ_16 T11.X, T11.X, 68, #3 +; EG-NEXT: ALU clause starting at 68: +; EG-NEXT: MOV * T0.Y, T3.X, +; EG-NEXT: MOV * T11.X, 0.0, +; EG-NEXT: ALU clause starting at 70: +; EG-NEXT: LSHL T0.W, T12.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV T3.X, PV.W, +; EG-NEXT: MOV * T0.Y, T5.X, +; EG-NEXT: ALU clause starting at 76: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T1.W, T12.X, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T0.Y, T7.X, +; EG-NEXT: ALU clause starting at 82: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T1.W, T12.X, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T7.X, PV.W, +; EG-NEXT: MOV * T0.Y, T9.X, +; EG-NEXT: ALU clause starting at 88: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T1.W, T12.X, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T9.X, PV.W, +; EG-NEXT: MOV * T0.Y, T3.X, +; EG-NEXT: ALU clause starting at 94: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, T12.X, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T3.X, PV.W, +; EG-NEXT: MOV * T0.Y, T5.X, +; EG-NEXT: ALU clause starting at 100: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, T12.X, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T0.Y, T7.X, +; EG-NEXT: ALU clause starting at 106: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, T12.X, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T7.X, PV.W, +; EG-NEXT: MOV * T0.Y, T9.X, +; EG-NEXT: ALU clause starting at 112: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, T12.X, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T9.X, PV.W, +; EG-NEXT: MOV * T0.Y, T2.X, +; EG-NEXT: ALU clause starting at 118: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T1.W, T12.X, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T2.X, PV.W, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: ALU clause starting at 124: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T1.W, T12.X, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV * T0.Y, T6.X, +; EG-NEXT: ALU clause starting at 130: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T1.W, T12.X, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T6.X, PV.W, +; EG-NEXT: MOV * T0.Y, T8.X, +; EG-NEXT: ALU clause starting at 136: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T1.W, T12.X, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV * T0.Y, T2.X, +; EG-NEXT: ALU clause starting at 142: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, T12.X, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T12.Z, PV.W, PS, +; EG-NEXT: MOV T2.X, PV.Z, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: ALU clause starting at 148: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, T12.X, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T12.X, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.X, +; EG-NEXT: MOV * T0.Y, T6.X, +; EG-NEXT: ALU clause starting at 154: +; EG-NEXT: AND_INT T0.W, T0.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, T13.X, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T11.Z, PV.W, PS, +; EG-NEXT: MOV T6.X, PV.Z, +; EG-NEXT: MOV * T0.Y, T8.X, +; EG-NEXT: ALU clause starting at 160: +; EG-NEXT: LSHR T13.X, KC0[2].Y, literal.x, ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, ; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) -; EG-NEXT: LSHR T2.X, PV.W, literal.x, -; EG-NEXT: MOV T7.W, T4.X, -; EG-NEXT: MOV * T1.W, T3.X, -; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: LSHR T14.X, PV.W, literal.x, +; EG-NEXT: AND_INT T0.W, T0.Y, literal.y, +; EG-NEXT: AND_INT * T1.W, T11.X, literal.z, +; EG-NEXT: 2(2.802597e-45), -65536(nan) +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T11.X, PV.W, PS, +; EG-NEXT: MOV T8.X, PV.X, +; EG-NEXT: MOV * T12.W, T3.X, +; EG-NEXT: MOV T12.Y, T5.X, +; EG-NEXT: MOV T11.W, T7.X, BS:VEC_120/SCL_212 +; EG-NEXT: MOV * T11.Y, T9.X, ; ; CM-LABEL: v16i16_arg: ; CM: ; %bb.0: ; %entry -; CM-NEXT: ALU 0, @22, KC0[], KC1[] -; CM-NEXT: TEX 7 @6 -; CM-NEXT: ALU 11, @23, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T7, T2.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X +; CM-NEXT: ALU 1, @68, KC0[], KC1[] +; CM-NEXT: TEX 0 @36 +; CM-NEXT: ALU 5, @70, KC0[], KC1[] +; CM-NEXT: TEX 0 @38 +; CM-NEXT: ALU 5, @76, KC0[], KC1[] +; CM-NEXT: TEX 0 @40 +; CM-NEXT: ALU 5, @82, KC0[], KC1[] +; CM-NEXT: TEX 0 @42 +; CM-NEXT: ALU 5, @88, KC0[], KC1[] +; CM-NEXT: TEX 0 @44 +; CM-NEXT: ALU 5, @94, KC0[], KC1[] +; CM-NEXT: TEX 0 @46 +; CM-NEXT: ALU 5, @100, KC0[], KC1[] +; CM-NEXT: TEX 0 @48 +; CM-NEXT: ALU 5, @106, KC0[], KC1[] +; CM-NEXT: TEX 0 @50 +; CM-NEXT: ALU 5, @112, KC0[], KC1[] +; CM-NEXT: TEX 0 @52 +; CM-NEXT: ALU 5, @118, KC0[], KC1[] +; CM-NEXT: TEX 0 @54 +; CM-NEXT: ALU 5, @124, KC0[], KC1[] +; CM-NEXT: TEX 0 @56 +; CM-NEXT: ALU 5, @130, KC0[], KC1[] +; CM-NEXT: TEX 0 @58 +; CM-NEXT: ALU 5, @136, KC0[], KC1[] +; CM-NEXT: TEX 0 @60 +; CM-NEXT: ALU 5, @142, KC0[], KC1[] +; CM-NEXT: TEX 0 @62 +; CM-NEXT: ALU 5, @148, KC0[], KC1[] +; CM-NEXT: TEX 0 @64 +; CM-NEXT: ALU 5, @154, KC0[], KC1[] +; CM-NEXT: TEX 0 @66 +; CM-NEXT: ALU 14, @160, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T11, T14.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T12, T13.X ; CM-NEXT: CF_END -; CM-NEXT: Fetch clause starting at 6: -; CM-NEXT: VTX_READ_16 T1.X, T0.X, 84, #3 -; CM-NEXT: VTX_READ_16 T2.X, T0.X, 86, #3 -; CM-NEXT: VTX_READ_16 T3.X, T0.X, 78, #3 -; CM-NEXT: VTX_READ_16 T4.X, T0.X, 94, #3 -; CM-NEXT: VTX_READ_16 T5.X, T0.X, 76, #3 -; CM-NEXT: VTX_READ_16 T6.X, T0.X, 92, #3 -; CM-NEXT: VTX_READ_16 T7.X, T0.X, 68, #3 -; CM-NEXT: VTX_READ_16 T0.X, T0.X, 70, #3 -; CM-NEXT: ALU clause starting at 22: -; CM-NEXT: MOV * T0.X, 0.0, -; CM-NEXT: ALU clause starting at 23: -; CM-NEXT: MOV * T1.Y, T2.X, -; CM-NEXT: MOV T7.Y, T0.X, -; CM-NEXT: MOV T1.Z, T6.X, BS:VEC_120/SCL_212 +; CM-NEXT: Fetch clause starting at 36: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 98, #3 +; CM-NEXT: Fetch clause starting at 38: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 90, #3 +; CM-NEXT: Fetch clause starting at 40: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 82, #3 +; CM-NEXT: Fetch clause starting at 42: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 74, #3 +; CM-NEXT: Fetch clause starting at 44: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 96, #3 +; CM-NEXT: Fetch clause starting at 46: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 88, #3 +; CM-NEXT: Fetch clause starting at 48: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 80, #3 +; CM-NEXT: Fetch clause starting at 50: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 72, #3 +; CM-NEXT: Fetch clause starting at 52: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 94, #3 +; CM-NEXT: Fetch clause starting at 54: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 86, #3 +; CM-NEXT: Fetch clause starting at 56: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 78, #3 +; CM-NEXT: Fetch clause starting at 58: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 70, #3 +; CM-NEXT: Fetch clause starting at 60: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 92, #3 +; CM-NEXT: Fetch clause starting at 62: +; CM-NEXT: VTX_READ_16 T12.X, T11.X, 84, #3 +; CM-NEXT: Fetch clause starting at 64: +; CM-NEXT: VTX_READ_16 T13.X, T11.X, 76, #3 +; CM-NEXT: Fetch clause starting at 66: +; CM-NEXT: VTX_READ_16 T11.X, T11.X, 68, #3 +; CM-NEXT: ALU clause starting at 68: +; CM-NEXT: MOV * T0.Y, T3.X, +; CM-NEXT: MOV * T11.X, 0.0, +; CM-NEXT: ALU clause starting at 70: +; CM-NEXT: LSHL T0.Z, T12.X, literal.x, +; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y, +; CM-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z, +; CM-NEXT: MOV T3.X, PV.W, +; CM-NEXT: MOV * T0.Y, T5.X, +; CM-NEXT: ALU clause starting at 76: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T12.X, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T5.X, PV.W, +; CM-NEXT: MOV * T0.Y, T7.X, +; CM-NEXT: ALU clause starting at 82: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T12.X, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T7.X, PV.W, +; CM-NEXT: MOV * T0.Y, T9.X, +; CM-NEXT: ALU clause starting at 88: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T12.X, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T9.X, PV.W, +; CM-NEXT: MOV * T0.Y, T3.X, +; CM-NEXT: ALU clause starting at 94: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, T12.X, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T3.X, PV.W, +; CM-NEXT: MOV * T0.Y, T5.X, +; CM-NEXT: ALU clause starting at 100: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, T12.X, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T5.X, PV.W, +; CM-NEXT: MOV * T0.Y, T7.X, +; CM-NEXT: ALU clause starting at 106: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, T12.X, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T7.X, PV.W, +; CM-NEXT: MOV * T0.Y, T9.X, +; CM-NEXT: ALU clause starting at 112: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, T12.X, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T9.X, PV.W, +; CM-NEXT: MOV * T0.Y, T2.X, +; CM-NEXT: ALU clause starting at 118: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T12.X, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T2.X, PV.W, +; CM-NEXT: MOV * T0.Y, T4.X, +; CM-NEXT: ALU clause starting at 124: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T12.X, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.W, +; CM-NEXT: MOV * T0.Y, T6.X, +; CM-NEXT: ALU clause starting at 130: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T12.X, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T6.X, PV.W, +; CM-NEXT: MOV * T0.Y, T8.X, +; CM-NEXT: ALU clause starting at 136: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T12.X, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T8.X, PV.W, +; CM-NEXT: MOV * T0.Y, T2.X, +; CM-NEXT: ALU clause starting at 142: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, T12.X, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T12.Z, PV.Z, PV.W, +; CM-NEXT: MOV T2.X, PV.Z, +; CM-NEXT: MOV * T0.Y, T4.X, +; CM-NEXT: ALU clause starting at 148: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, T12.X, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T12.X, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.X, +; CM-NEXT: MOV * T0.Y, T6.X, +; CM-NEXT: ALU clause starting at 154: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, T13.X, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T11.Z, PV.Z, PV.W, +; CM-NEXT: MOV T6.X, PV.Z, +; CM-NEXT: MOV * T0.Y, T8.X, +; CM-NEXT: ALU clause starting at 160: ; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, ; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; CM-NEXT: LSHR T0.X, PV.W, literal.x, -; CM-NEXT: MOV T7.Z, T5.X, -; CM-NEXT: MOV * T1.W, T4.X, BS:VEC_120/SCL_212 -; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; CM-NEXT: LSHR T2.X, KC0[2].Y, literal.x, -; CM-NEXT: MOV * T7.W, T3.X, +; CM-NEXT: LSHR * T13.X, PV.W, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: LSHR T14.X, KC0[2].Y, literal.x, +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.y, +; CM-NEXT: AND_INT * T0.W, T11.X, literal.z, +; CM-NEXT: 2(2.802597e-45), -65536(nan) +; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; CM-NEXT: OR_INT * T11.X, PV.Z, PV.W, +; CM-NEXT: MOV T8.X, PV.X, +; CM-NEXT: MOV * T12.W, T3.X, +; CM-NEXT: MOV T12.Y, T5.X, +; CM-NEXT: MOV * T11.W, T7.X, BS:VEC_120/SCL_212 +; CM-NEXT: MOV * T11.Y, T9.X, entry: store <16 x i16> %in, ptr addrspace(1) %out ret void diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll index 4309cfbe..c29c52c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll @@ -11,6 +11,12 @@ declare <8 x bfloat> @llvm.amdgcn.cvt.scale.pk8.bf16.fp4(i32 %src, i32 %scale, i declare <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.fp8(<2 x i32> %src, i32 %scale, i32 %scale_sel) declare <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.bf8(<2 x i32> %src, i32 %scale, i32 %scale_sel) declare <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.fp4(i32 %src, i32 %scale, i32 %scale_sel) +declare <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.fp6(<3 x i32> %src, i32 %scale, i32 %scale_sel) +declare <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.fp6(<3 x i32> %src, i32 %scale, i32 %scale_sel) +declare <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.bf6(<3 x i32> %src, i32 %scale, i32 %scale_sel) +declare <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.bf6(<3 x i32> %src, i32 %scale, i32 %scale_sel) +declare <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.fp6(<3 x i32> %src, i32 %scale, i32 %scale_sel) +declare <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.bf6(<3 x i32> %src, i32 %scale, i32 %scale_sel) define amdgpu_ps void @test_cvt_scale_pk8_f16_fp8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) { ; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_fp8_vv: @@ -162,3 +168,207 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_fp4_vv(i32 %src, i32 %scale, ptr a store <8 x float> %cvt, ptr addrspace(1) %out, align 32 ret void } + +define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_fp6_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_fp6 v[6:13], v[0:2], v3 +; GFX1250-SDAG-NEXT: s_clause 0x1 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_fp6_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[6:13], v[0:2], v3 +; GFX1250-GISEL-NEXT: s_clause 0x1 +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16 +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.fp6(<3 x i32> %src, i32 %scale, i32 0) + store <16 x half> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_fp6_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1 +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v12, s2 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], 0x64 scale_sel:1 +; GFX1250-SDAG-NEXT: s_clause 0x1 +; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16 +; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_fp6_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1 +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], 0x64 scale_sel:1 +; GFX1250-GISEL-NEXT: s_clause 0x1 +; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16 +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.fp6(<3 x i32> %src, i32 100, i32 1) + store <16 x half> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_cvt_scale_pk16_bf16_fp6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_cvt_scale_pk16_bf16_fp6_vv: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_cvt_scale_pk16_bf16_fp6 v[6:13], v[0:2], v3 scale_sel:2 +; GFX1250-NEXT: s_clause 0x1 +; GFX1250-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16 +; GFX1250-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.fp6(<3 x i32> %src, i32 %scale, i32 2) + store <16 x bfloat> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_cvt_scale_pk16_bf16_fp6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_cvt_scale_pk16_bf16_fp6_sl: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1 +; GFX1250-NEXT: v_mov_b32_e32 v12, s2 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_cvt_scale_pk16_bf16_fp6 v[2:9], v[10:12], 0x64 scale_sel:3 +; GFX1250-NEXT: s_clause 0x1 +; GFX1250-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16 +; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.fp6(<3 x i32> %src, i32 100, i32 3) + store <16 x bfloat> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_bf6_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_bf6 v[6:13], v[0:2], v3 scale_sel:4 +; GFX1250-SDAG-NEXT: s_clause 0x1 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_bf6_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[6:13], v[0:2], v3 scale_sel:4 +; GFX1250-GISEL-NEXT: s_clause 0x1 +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16 +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.bf6(<3 x i32> %src, i32 %scale, i32 4) + store <16 x half> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_bf6_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1 +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v12, s2 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], 0x64 scale_sel:5 +; GFX1250-SDAG-NEXT: s_clause 0x1 +; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16 +; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_bf6_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1 +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], 0x64 scale_sel:5 +; GFX1250-GISEL-NEXT: s_clause 0x1 +; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16 +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.bf6(<3 x i32> %src, i32 100, i32 5) + store <16 x half> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_cvt_scale_pk16_bf16_bf6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_cvt_scale_pk16_bf16_bf6_vv: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_cvt_scale_pk16_bf16_bf6 v[6:13], v[0:2], v3 scale_sel:6 +; GFX1250-NEXT: s_clause 0x1 +; GFX1250-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16 +; GFX1250-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.bf6(<3 x i32> %src, i32 %scale, i32 6) + store <16 x bfloat> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_cvt_scale_pk16_bf16_bf6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_cvt_scale_pk16_bf16_bf6_sl: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1 +; GFX1250-NEXT: v_mov_b32_e32 v12, s2 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_cvt_scale_pk16_bf16_bf6 v[2:9], v[10:12], 0x64 scale_sel:7 +; GFX1250-NEXT: s_clause 0x1 +; GFX1250-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16 +; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <16 x bfloat> @llvm.amdgcn.cvt.scale.pk16.bf16.bf6(<3 x i32> %src, i32 100, i32 7) + store <16 x bfloat> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_cvt_scale_pk16_f32_fp6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f32_fp6_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f32_fp6 v[6:21], v[0:2], v3 scale_sel:5 +; GFX1250-SDAG-NEXT: s_clause 0x3 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[18:21], off offset:48 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[14:17], off offset:32 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f32_fp6_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_fp6 v[6:21], v[0:2], v3 scale_sel:5 +; GFX1250-GISEL-NEXT: s_clause 0x3 +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16 +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[14:17], off offset:32 +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[18:21], off offset:48 +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.fp6(<3 x i32> %src, i32 %scale, i32 5) + store <16 x float> %cvt, ptr addrspace(1) %out, align 16 + ret void +} + +define amdgpu_ps void @test_cvt_scale_pk16_f32_bf6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f32_bf6_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f32_bf6 v[6:21], v[0:2], v3 scale_sel:6 +; GFX1250-SDAG-NEXT: s_clause 0x3 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[18:21], off offset:48 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[14:17], off offset:32 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16 +; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f32_bf6_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_bf6 v[6:21], v[0:2], v3 scale_sel:6 +; GFX1250-GISEL-NEXT: s_clause 0x3 +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16 +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[14:17], off offset:32 +; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[18:21], off offset:48 +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.bf6(<3 x i32> %src, i32 %scale, i32 6) + store <16 x float> %cvt, ptr addrspace(1) %out, align 16 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll new file mode 100644 index 0000000..dfb9089 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll @@ -0,0 +1,303 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s + +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float %scale) +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float %scale) +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> %src, float %scale) +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %src, float %scale) +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %src, float %scale) +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float %scale) + +define amdgpu_ps void @test_scalef32_pk16_bf6_f32_vv(<16 x float> %src, float %scale, ptr addrspace(1) %out) { +; GFX1210-SDAG-LABEL: test_scalef32_pk16_bf6_f32_vv: +; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v23, v18 :: v_dual_mov_b32 v22, v17 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[0:15], v16 +; GFX1250-SDAG-NEXT: global_store_b96 v[22:23], v[18:20], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f32_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v22, v17 :: v_dual_mov_b32 v23, v18 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[0:15], v16 +; GFX1250-GISEL-NEXT: global_store_b96 v[22:23], v[18:20], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_bf6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[2:17], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f32_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[2:17], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_fp6_f32_vv(<16 x float> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f32_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v23, v18 :: v_dual_mov_b32 v22, v17 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[0:15], v16 +; GFX1250-SDAG-NEXT: global_store_b96 v[22:23], v[18:20], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f32_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v22, v17 :: v_dual_mov_b32 v23, v18 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[0:15], v16 +; GFX1250-GISEL-NEXT: global_store_b96 v[22:23], v[18:20], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_fp6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f32_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[2:17], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f32_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[2:17], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_vv(<16 x bfloat> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_bf16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[0:7], v8 +; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_bf16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[0:7], v8 +; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> %src, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_sl(<16 x bfloat> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_bf16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[2:9], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_bf16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[2:9], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> %src, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_bf6_f16_vv(<16 x half> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[0:7], v8 +; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v14, v9 :: v_dual_mov_b32 v15, v10 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[0:7], v8 +; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %src, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_bf6_f16_sl(<16 x half> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[2:9], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[2:9], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %src, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_vv(<16 x bfloat> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_bf16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[0:7], v8 +; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_bf16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[0:7], v8 +; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %src, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_sl(<16 x bfloat> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_bf16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[2:9], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_bf16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[2:9], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %src, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_fp6_f16_vv(<16 x half> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[0:7], v8 +; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v14, v9 :: v_dual_mov_b32 v15, v10 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[0:7], v8 +; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk16_fp6_f16_sl(<16 x half> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[2:9], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[2:9], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll new file mode 100644 index 0000000..cd0b081 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll @@ -0,0 +1,403 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s + +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> %src, float %scale) +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> %src, float %scale) +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> %src, float %scale) +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> %src, float %scale) +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> %src, float %scale) +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> %src, float %scale) +declare i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> %src, float %scale) +declare i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> %src, float %scale) +declare i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> %src, float %scale) + +define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_bf16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_bf16 v[8:9], v[0:3], v4 +; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_bf16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_bf16 v[8:9], v[0:3], v4 +; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> %src, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_bf16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_bf16 v[6:7], v[2:5], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_bf16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_bf16 v[6:7], v[2:5], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> %src, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_bf16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_bf16 v[8:9], v[0:3], v4 +; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_bf16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_bf16 v[8:9], v[0:3], v4 +; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> %src, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_bf16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_bf16 v[6:7], v[2:5], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_bf16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_bf16 v[6:7], v[2:5], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> %src, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp8_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[8:9], v[0:3], v4 +; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[0:3], v4 +; GFX1250-GISEL-NEXT: global_store_b64 v[8:9], v[6:7], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> %src, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp8_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[2:5], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[2:5], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> %src, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_bf8_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[8:9], v[0:3], v4 +; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[0:3], v4 +; GFX1250-GISEL-NEXT: global_store_b64 v[8:9], v[6:7], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> %src, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_bf8_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[2:5], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[2:5], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> %src, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_bf8_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f32_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[12:13], v[0:7], v8 +; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f32_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[0:7], v8 +; GFX1250-GISEL-NEXT: global_store_b64 v[12:13], v[10:11], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> %src, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_bf8_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f32_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[2:9], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f32_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[2:9], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> %src, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp8_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f32_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[12:13], v[0:7], v8 +; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f32_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[0:7], v8 +; GFX1250-GISEL-NEXT: global_store_b64 v[12:13], v[10:11], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> %src, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp8_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f32_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[2:9], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f32_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[2:9], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> %src, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp4_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f32_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f32 v9, v[0:7], v8 +; GFX1250-SDAG-NEXT: global_store_b32 v[10:11], v9, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f32_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f32 v9, v[0:7], v8 +; GFX1250-GISEL-NEXT: global_store_b32 v[12:13], v9, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> %src, float %scale) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp4_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f32_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f32 v10, v[2:9], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v10, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f32_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f32 v10, v[2:9], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v10, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> %src, float 100.0) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp4_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f16 v5, v[0:3], v4 +; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v5, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f16 v5, v[0:3], v4 +; GFX1250-GISEL-NEXT: global_store_b32 v[8:9], v5, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> %src, float %scale) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp4_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f16 v6, v[2:5], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v6, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f16 v6, v[2:5], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v6, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> %src, float 100.0) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_bf16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5 +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_bf16 v5, v[0:3], v4 +; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v5, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_bf16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5 +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_bf16 v5, v[0:3], v4 +; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v5, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> %src, float %scale) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_bf16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_bf16 v6, v[2:5], 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v6, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_bf16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_bf16 v6, v[2:5], 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v6, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> %src, float 100.0) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll new file mode 100644 index 0000000..d33acf6 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll @@ -0,0 +1,385 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s + +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.bf16(<8 x bfloat> %src, i32 %sr, float %scale) +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.bf16(<8 x bfloat> %src, i32 %sr, float %scale) +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f16(<8 x half> %src, i32 %sr, float %scale) +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f16(<8 x half> %src, i32 %sr, float %scale) +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f32(<8 x float> %src, i32 %sr, float %scale) +declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f32(<8 x float> %src, i32 %sr, float %scale) +declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f32(<8 x float> %src, i32 %sr, float %scale) +declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f16(<8 x half> %src, i32 %sr, float %scale) +declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.bf16(<8 x bfloat> %src, i32 %sr, float %scale) + +define amdgpu_ps void @test_scalef32_sr_pk8_fp8_bf16_vv(<8 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_bf16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_bf16 v[8:9], v[0:3], v4, v5 +; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_bf16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_bf16 v[8:9], v[0:3], v4, v5 +; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.bf16(<8 x bfloat> %src, i32 %sr, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_bf16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_bf16 v[6:7], v[2:5], s4, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_bf16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_bf16 v[6:7], v[2:5], s4, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.bf16(<8 x bfloat> %src, i32 %sr, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_bf8_bf16_vv(<8 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_bf16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_bf16 v[8:9], v[0:3], v4, v5 +; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_bf16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_bf16 v[8:9], v[0:3], v4, v5 +; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.bf16(<8 x bfloat> %src, i32 %sr, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_bf16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_bf16 v[6:7], v[2:5], s4, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_bf16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_bf16 v[6:7], v[2:5], s4, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.bf16(<8 x bfloat> %src, i32 %sr, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_vv(<8 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[8:9], v[0:3], v4, v5 +; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[8:9], v[0:3], v4, v5 +; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f16(<8 x half> %src, i32 %sr, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[6:7], v[2:5], s4, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[6:7], v[2:5], s4, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f16(<8 x half> %src, i32 %sr, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_vv(<8 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[8:9], v[0:3], v4, v5 +; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[8:9], v[0:3], v4, v5 +; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f16(<8 x half> %src, i32 %sr, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[6:7], v[2:5], s4, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[6:7], v[2:5], s4, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f16(<8 x half> %src, i32 %sr, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_vv(<8 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f32_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[12:13], v[0:7], v8, v9 +; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f32_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[12:13], v[0:7], v8, v9 +; GFX1250-GISEL-NEXT: global_store_b64 v[10:11], v[12:13], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f32(<8 x float> %src, i32 %sr, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f32_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[2:9], s8, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f32_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[2:9], s8, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f32(<8 x float> %src, i32 %sr, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_vv(<8 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f32_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[12:13], v[0:7], v8, v9 +; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f32_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[12:13], v[0:7], v8, v9 +; GFX1250-GISEL-NEXT: global_store_b64 v[10:11], v[12:13], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f32(<8 x float> %src, i32 %sr, float %scale) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f32_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[2:9], s8, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f32_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[2:9], s8, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f32(<8 x float> %src, i32 %sr, float 100.0) + store <2 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_vv(<8 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f32_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v12, v[0:7], v8, v9 +; GFX1250-SDAG-NEXT: global_store_b32 v[10:11], v12, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f32_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v12, v[0:7], v8, v9 +; GFX1250-GISEL-NEXT: global_store_b32 v[10:11], v12, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f32(<8 x float> %src, i32 %sr, float %scale) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f32_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[2:9], s8, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v10, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f32_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[2:9], s8, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v10, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f32(<8 x float> %src, i32 %sr, float 100.0) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_vv(<8 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v8, v[0:3], v4, v5 +; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v8, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v8, v[0:3], v4, v5 +; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v8, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f16(<8 x half> %src, i32 %sr, float %scale) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v6, v[2:5], s4, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v6, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v6, v[2:5], s4, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v6, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f16(<8 x half> %src, i32 %sr, float 100.0) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp4_bf16_vv(<8 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_bf16_vv: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_bf16 v8, v[0:3], v4, v5 +; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v8, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_bf16_vv: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_bf16 v8, v[0:3], v4, v5 +; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v8, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.bf16(<8 x bfloat> %src, i32 %sr, float %scale) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk8_fp4_bf16_sl(<8 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_bf16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_bf16 v6, v[2:5], s4, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v6, off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_bf16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_bf16 v6, v[2:5], s4, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v6, off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.bf16(<8 x bfloat> %src, i32 %sr, float 100.0) + store i32 %cvt, ptr addrspace(1) %out, align 4 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll new file mode 100644 index 0000000..c439518 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll @@ -0,0 +1,232 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s + +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %src, i32 %sr, float %scale) +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float %scale) +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %src, i32 %sr, float %scale) +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> %src, i32 %sr, float %scale) +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %src, i32 %sr, float %scale) +declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i32 %sr, float %scale) + +define amdgpu_ps void @test_scalef32_sr_pk16_bf6_bf16_vv(<16 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_bf16_vv: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_bf16 v[12:14], v[0:7], v8, v9 +; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %src, i32 %sr, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_bf6_bf16_sl(<16 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_bf16_sl: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[2:9], s8, 0x42c80000 +; GFX1250-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %src, i32 %sr, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_vv(<16 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_f16_vv: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_f16 v[12:14], v[0:7], v8, v9 +; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_sl(<16 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[2:9], s8, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_bf6_f16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[2:9], s8, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_fp6_bf16_vv(<16 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_bf16_vv: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_bf16 v[12:14], v[0:7], v8, v9 +; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> %src, i32 %sr, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_fp6_bf16_sl(<16 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_bf16_sl: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[2:9], s8, 0x42c80000 +; GFX1250-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> %src, i32 %sr, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_vv(<16 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_f16_vv: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_f16 v[12:14], v[0:7], v8, v9 +; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %src, i32 %sr, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_sl(<16 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f16_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[2:9], s8, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_fp6_f16_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[2:9], s8, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %src, i32 %sr, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_vv(<16 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_f32_vv: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_f32 v[20:22], v[0:15], v16, v17 +; GFX1250-NEXT: global_store_b96 v[18:19], v[20:22], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %src, i32 %sr, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_sl(<16 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f32_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_bf6_f32 v[18:20], v[2:17], s16, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_bf6_f32_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_bf6_f32 v[18:20], v[2:17], s16, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %src, i32 %sr, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_vv(<16 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) { +; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_f32_vv: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_f32 v[20:22], v[0:15], v16, v17 +; GFX1250-NEXT: global_store_b96 v[18:19], v[20:22], off +; GFX1250-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i32 %sr, float %scale) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} + +define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_sl(<16 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) { +; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f32_sl: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_fp6_f32 v[18:20], v[2:17], s16, 0x42c80000 +; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_fp6_f32_sl: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_fp6_f32 v[18:20], v[2:17], s16, 0x42c80000 +; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off +; GFX1250-GISEL-NEXT: s_endpgm + %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i32 %sr, float 100.0) + store <3 x i32> %cvt, ptr addrspace(1) %out, align 8 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll new file mode 100644 index 0000000..d2f96c4 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll @@ -0,0 +1,66 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s + +declare <2 x i32> @llvm.amdgcn.perm.pk16.b4.u4(i32, i32, <2 x i32>) +declare <3 x i32> @llvm.amdgcn.perm.pk16.b6.u4(i32, i64, <2 x i32>) +declare <4 x i32> @llvm.amdgcn.perm.pk16.b8.u4(i64, i64, <2 x i32>) + +define void @test_perm_pk16_b4_u4(i32 %a, i32 %b, <2 x i32> %c, ptr %out) { +; GFX1250-LABEL: test_perm_pk16_b4_u4: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_perm_pk16_b4_u4 v[0:1], v0, v1, v[2:3] +; GFX1250-NEXT: flat_store_b64 v[4:5], v[0:1] scope:SCOPE_SE +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %ret = tail call <2 x i32> @llvm.amdgcn.perm.pk16.b4.u4(i32 %a, i32 %b, <2 x i32> %c) + store <2 x i32> %ret, ptr %out, align 8 + ret void +} + +define void @test_perm_pk16_b6_u4(i32 %a, i64 %b, <2 x i32> %c, ptr %out) { +; GFX1250-SDAG-LABEL: test_perm_pk16_b6_u4: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v9, v4 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v3, v2 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v6, v5 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_perm_pk16_b6_u4 v[0:2], v0, v[2:3], v[8:9] +; GFX1250-SDAG-NEXT: flat_store_b96 v[6:7], v[0:2] scope:SCOPE_SE +; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0 +; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-GISEL-LABEL: test_perm_pk16_b6_u4: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v9, v2 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6 +; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250-GISEL-NEXT: v_perm_pk16_b6_u4 v[0:2], v0, v[8:9], v[2:3] +; GFX1250-GISEL-NEXT: flat_store_b96 v[4:5], v[0:2] scope:SCOPE_SE +; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0 +; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31] + %ret = tail call <3 x i32> @llvm.amdgcn.perm.pk16.b6.u4(i32 %a, i64 %b, <2 x i32> %c) + store <3 x i32> %ret, ptr %out, align 16 + ret void +} + +define void @test_perm_pk16_b8_u4(i64 %a, i64 %b, <2 x i32> %c, ptr %out) { +; GFX1250-LABEL: test_perm_pk16_b8_u4: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_perm_pk16_b8_u4 v[0:3], v[0:1], v[2:3], v[4:5] +; GFX1250-NEXT: flat_store_b128 v[6:7], v[0:3] scope:SCOPE_SE +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %ret = tail call <4 x i32> @llvm.amdgcn.perm.pk16.b8.u4(i64 %a, i64 %b, <2 x i32> %c) + store <4 x i32> %ret, ptr %out, align 16 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll index 4491c4b..8c8dd83 100644 --- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll @@ -232,32 +232,38 @@ define amdgpu_kernel void @constant_load_v3i16(ptr addrspace(1) %out, ptr addrsp ; ; EG-LABEL: constant_load_v3i16: ; EG: ; %bb.0: ; %entry -; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 1 @6 -; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T3.X, 0 -; EG-NEXT: MEM_RAT MSKOR T2.XW, T0.X +; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 2 @6 +; EG-NEXT: ALU 19, @13, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T7.X, 0 +; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X ; EG-NEXT: CF_END ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_16 T1.X, T0.X, 0, #1 -; EG-NEXT: VTX_READ_16 T0.X, T0.X, 4, #1 -; EG-NEXT: ALU clause starting at 10: -; EG-NEXT: MOV * T0.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 11: +; EG-NEXT: VTX_READ_16 T6.X, T5.X, 0, #1 +; EG-NEXT: VTX_READ_16 T7.X, T5.X, 2, #1 +; EG-NEXT: VTX_READ_16 T5.X, T5.X, 4, #1 +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T5.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 13: ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, ; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00) ; EG-NEXT: AND_INT T1.W, PV.W, literal.x, -; EG-NEXT: AND_INT * T2.W, T0.X, literal.y, +; EG-NEXT: AND_INT * T2.W, T5.X, literal.y, ; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41) ; EG-NEXT: LSHL * T1.W, PV.W, literal.x, ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) -; EG-NEXT: LSHL T2.X, T2.W, PV.W, -; EG-NEXT: LSHL * T2.W, literal.x, PV.W, +; EG-NEXT: LSHL T5.X, T2.W, PV.W, +; EG-NEXT: LSHL * T5.W, literal.x, PV.W, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: MOV T5.Y, 0.0, +; EG-NEXT: MOV * T5.Z, 0.0, +; EG-NEXT: LSHR T8.X, T0.W, literal.x, +; EG-NEXT: LSHL T0.W, T7.X, literal.y, +; EG-NEXT: AND_INT * T1.W, T6.X, literal.z, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: MOV T2.Y, 0.0, -; EG-NEXT: MOV * T2.Z, 0.0, -; EG-NEXT: LSHR T0.X, T0.W, literal.x, -; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT T6.X, PV.W, PS, +; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; ; GFX12-LABEL: constant_load_v3i16: diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll index b39b38a..5c4bc95 100644 --- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll +++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll @@ -9832,24 +9832,50 @@ define amdgpu_kernel void @constant_zextload_v4i8_to_v4i16(ptr addrspace(1) %out ; ; EG-LABEL: constant_zextload_v4i8_to_v4i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 6, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XY, T5.X, 1 +; EG-NEXT: ALU 31, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XY, T7.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1 +; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T4.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: MOV * T7.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: AND_INT T0.W, T7.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 255(3.573311e-43), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T0.W, T7.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, ; EG-NEXT: MOV * T0.W, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT * T4.Y, T4.X, literal.x, PV.W, +; EG-NEXT: BFE_UINT T0.W, T7.X, literal.x, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T7.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: AND_INT T4.X, T4.X, literal.x, -; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.y, -; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: LSHR T7.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T8.Y, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.Y, +; EG-NEXT: MOV * T8.X, T4.X, ; ; GFX12-LABEL: constant_zextload_v4i8_to_v4i16: ; GFX12: ; %bb.0: @@ -9951,23 +9977,56 @@ define amdgpu_kernel void @constant_sextload_v4i8_to_v4i16(ptr addrspace(1) %out ; ; EG-LABEL: constant_sextload_v4i8_to_v4i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 5, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XY, T4.X, 1 +; EG-NEXT: ALU 37, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XY, T7.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1 +; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T4.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: -; EG-NEXT: BFE_INT T5.X, T4.X, 0.0, literal.x, -; EG-NEXT: LSHR T0.W, T4.X, literal.x, -; EG-NEXT: LSHR * T4.X, KC0[2].Y, literal.y, -; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45) -; EG-NEXT: BFE_INT * T5.Y, PV.W, 0.0, literal.x, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: MOV * T7.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: BFE_INT * T0.W, T7.X, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T7.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: LSHR * T0.W, T7.X, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T7.X, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: LSHR T7.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T8.Y, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.Y, +; EG-NEXT: MOV * T8.X, T4.X, ; ; GFX12-LABEL: constant_sextload_v4i8_to_v4i16: ; GFX12: ; %bb.0: @@ -10088,27 +10147,80 @@ define amdgpu_kernel void @constant_zextload_v8i8_to_v8i16(ptr addrspace(1) %out ; ; EG-LABEL: constant_zextload_v8i8_to_v8i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T5.X, 1 +; EG-NEXT: ALU 61, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T11.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_64 T5.XY, T5.X, 0, #1 +; EG-NEXT: VTX_READ_64 T11.XY, T11.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T5.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: MOV * T0.Y, T8.X, +; EG-NEXT: MOV * T11.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: AND_INT T0.W, T11.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 255(3.573311e-43), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T0.W, T11.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, ; EG-NEXT: MOV * T0.W, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT * T6.W, T5.Y, literal.x, PV.W, +; EG-NEXT: BFE_UINT T1.W, T11.X, literal.x, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), -65536(nan) +; EG-NEXT: OR_INT * T1.W, PS, PV.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T11.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T12.Y, PV.W, PS, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T11.Y, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T11.Y, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT T6.Y, T5.X, literal.x, T0.W, -; EG-NEXT: AND_INT * T6.Z, T5.Y, literal.y, -; EG-NEXT: 8(1.121039e-44), 255(3.573311e-43) -; EG-NEXT: AND_INT T6.X, T5.X, literal.x, -; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.y, -; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: BFE_UINT * T0.W, T11.Y, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PV.W, T0.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T11.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: LSHR T11.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T12.W, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T12.X, T8.X, +; EG-NEXT: MOV * T12.Z, T4.X, ; ; GFX12-LABEL: constant_zextload_v8i8_to_v8i16: ; GFX12: ; %bb.0: @@ -10255,28 +10367,93 @@ define amdgpu_kernel void @constant_sextload_v8i8_to_v8i16(ptr addrspace(1) %out ; ; EG-LABEL: constant_sextload_v8i8_to_v8i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T5.X, 1 +; EG-NEXT: ALU 74, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T11.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_64 T5.XY, T5.X, 0, #1 +; EG-NEXT: VTX_READ_64 T11.XY, T11.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T5.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: -; EG-NEXT: BFE_INT * T6.Z, T5.Y, 0.0, literal.x, +; EG-NEXT: MOV * T0.Y, T8.X, +; EG-NEXT: MOV * T11.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: BFE_INT * T0.W, T11.X, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T6.X, T5.X, 0.0, literal.x, -; EG-NEXT: LSHR * T0.W, T5.Y, literal.x, +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T11.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T6.W, PV.W, 0.0, literal.x, -; EG-NEXT: LSHR * T0.W, T5.X, literal.x, +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, +; EG-NEXT: LSHR * T0.W, T11.X, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T11.X, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T12.Y, PV.W, PS, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV T0.Y, T4.X, +; EG-NEXT: BFE_INT * T0.W, T11.Y, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T5.X, KC0[2].Y, literal.x, -; EG-NEXT: BFE_INT * T6.Y, PS, 0.0, literal.y, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T11.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: LSHR * T0.W, T11.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T11.Y, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: LSHR T11.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T12.W, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T12.X, T8.X, +; EG-NEXT: MOV * T12.Z, T4.X, ; ; GFX12-LABEL: constant_sextload_v8i8_to_v8i16: ; GFX12: ; %bb.0: @@ -10472,37 +10649,146 @@ define amdgpu_kernel void @constant_zextload_v16i8_to_v16i16(ptr addrspace(1) %o ; ; EG-LABEL: constant_zextload_v16i8_to_v16i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 19, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T10.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T7.X, 1 +; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @8 +; EG-NEXT: ALU 103, @12, KC0[], KC1[] +; EG-NEXT: ALU 20, @116, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T22.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T21.X, 1 ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1 -; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T7.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T19.XYZW, T19.X, 0, #1 +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: MOV * T0.Y, T16.X, +; EG-NEXT: MOV * T19.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: AND_INT T0.W, T19.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 255(3.573311e-43), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T16.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T0.W, T19.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T16.X, PV.W, +; EG-NEXT: MOV T0.Y, T17.X, ; EG-NEXT: MOV * T0.W, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT * T8.W, T7.Y, literal.x, PV.W, +; EG-NEXT: BFE_UINT T1.W, T19.X, literal.x, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), -65536(nan) +; EG-NEXT: OR_INT * T1.W, PS, PV.W, +; EG-NEXT: MOV * T17.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T19.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT T8.Y, T7.X, literal.x, T0.W, -; EG-NEXT: AND_INT T8.Z, T7.Y, literal.y, -; EG-NEXT: BFE_UINT * T9.W, T7.W, literal.x, T0.W, -; EG-NEXT: 8(1.121039e-44), 255(3.573311e-43) -; EG-NEXT: AND_INT T8.X, T7.X, literal.x, -; EG-NEXT: BFE_UINT T9.Y, T7.Z, literal.y, T0.W, -; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.z, -; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44) -; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; EG-NEXT: AND_INT * T9.Z, T7.W, literal.x, -; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) -; EG-NEXT: AND_INT T9.X, T7.Z, literal.x, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, -; EG-NEXT: 255(3.573311e-43), 16(2.242078e-44) -; EG-NEXT: LSHR * T10.X, PV.W, literal.x, +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T20.Y, PV.W, PS, +; EG-NEXT: MOV T17.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T12.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T19.Y, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T12.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T19.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T12.X, PV.W, +; EG-NEXT: MOV T0.Y, T13.X, +; EG-NEXT: BFE_UINT * T1.W, T19.Y, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T13.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T19.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T20.W, PV.W, PS, +; EG-NEXT: MOV T13.X, PV.W, +; EG-NEXT: MOV * T0.Y, T8.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T19.Z, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T19.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, +; EG-NEXT: BFE_UINT * T1.W, T19.Z, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T19.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T19.Y, PV.W, PS, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T19.W, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T19.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: BFE_UINT * T0.W, T19.W, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: ALU clause starting at 116: +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PV.W, T0.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR T0.W, T19.W, literal.x, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44) +; EG-NEXT: LSHR T21.X, PS, literal.x, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.y, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.z, +; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; EG-NEXT: 16711680(2.341805e-38), 0(0.000000e+00) +; EG-NEXT: LSHR T22.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T19.W, PV.W, PS, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T20.X, T16.X, +; EG-NEXT: MOV * T20.Z, T12.X, +; EG-NEXT: MOV T19.X, T8.X, +; EG-NEXT: MOV * T19.Z, T4.X, BS:VEC_120/SCL_212 ; ; GFX12-LABEL: constant_zextload_v16i8_to_v16i16: ; GFX12: ; %bb.0: @@ -10753,38 +11039,173 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i16(ptr addrspace(1) %o ; ; EG-LABEL: constant_sextload_v16i8_to_v16i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 20, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T10.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T7.X, 1 +; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @8 +; EG-NEXT: ALU 104, @12, KC0[], KC1[] +; EG-NEXT: ALU 46, @117, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T22.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T21.X, 1 ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1 -; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T7.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: -; EG-NEXT: BFE_INT * T8.Z, T7.Y, 0.0, literal.x, +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T19.XYZW, T19.X, 0, #1 +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: MOV * T0.Y, T16.X, +; EG-NEXT: MOV * T19.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: BFE_INT * T0.W, T19.X, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T16.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T19.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T8.X, T7.X, 0.0, literal.x, -; EG-NEXT: BFE_INT T9.Z, T7.W, 0.0, literal.x, -; EG-NEXT: LSHR * T0.W, T7.Y, literal.x, +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T16.X, PV.W, +; EG-NEXT: MOV T0.Y, T17.X, +; EG-NEXT: LSHR * T0.W, T19.X, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T17.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T19.X, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T20.Y, PV.W, PS, +; EG-NEXT: MOV T17.X, PV.Y, +; EG-NEXT: MOV T0.Y, T12.X, +; EG-NEXT: BFE_INT * T0.W, T19.Y, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T9.X, T7.Z, 0.0, literal.x, -; EG-NEXT: LSHR T0.Z, T7.W, literal.x, -; EG-NEXT: BFE_INT T8.W, PV.W, 0.0, literal.x, -; EG-NEXT: LSHR * T0.W, T7.X, literal.x, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T12.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T19.Y, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T7.X, KC0[2].Y, literal.x, -; EG-NEXT: BFE_INT T8.Y, PS, 0.0, literal.y, -; EG-NEXT: LSHR T1.Z, T7.Z, literal.y, -; EG-NEXT: BFE_INT T9.W, PV.Z, 0.0, literal.y, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T10.X, PS, literal.x, -; EG-NEXT: BFE_INT * T9.Y, PV.Z, 0.0, literal.y, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T12.X, PV.W, +; EG-NEXT: MOV T0.Y, T13.X, +; EG-NEXT: LSHR * T0.W, T19.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T13.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T19.Y, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T20.W, PV.W, PS, +; EG-NEXT: MOV T13.X, PV.W, +; EG-NEXT: MOV T0.Y, T8.X, +; EG-NEXT: BFE_INT * T0.W, T19.Z, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T19.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, +; EG-NEXT: LSHR * T0.W, T19.Z, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T19.Z, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: ALU clause starting at 117: +; EG-NEXT: OR_INT * T19.Y, T1.W, T0.W, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV T0.Y, T4.X, +; EG-NEXT: BFE_INT * T0.W, T19.W, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T19.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: LSHR * T0.W, T19.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR T0.W, T19.W, literal.x, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y, +; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44) +; EG-NEXT: LSHR T21.X, PS, literal.x, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.y, +; EG-NEXT: LSHL * T0.W, PV.W, literal.z, +; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T22.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T19.W, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T20.X, T16.X, +; EG-NEXT: MOV * T20.Z, T12.X, +; EG-NEXT: MOV T19.X, T8.X, +; EG-NEXT: MOV * T19.Z, T4.X, BS:VEC_120/SCL_212 ; ; GFX12-LABEL: constant_sextload_v16i8_to_v16i16: ; GFX12: ; %bb.0: @@ -11132,58 +11553,276 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i16(ptr addrspace(1) %o ; ; EG-LABEL: constant_zextload_v32i8_to_v32i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 1 @8 -; EG-NEXT: ALU 37, @13, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T18.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T12.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T16.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T11.X, 1 +; EG-NEXT: ALU 1, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @10 +; EG-NEXT: ALU 103, @16, KC0[], KC1[] +; EG-NEXT: ALU 104, @120, KC0[], KC1[] +; EG-NEXT: ALU 41, @225, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T42.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T41.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T40.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T35.XYZW, T39.X, 1 ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 8: -; EG-NEXT: VTX_READ_128 T12.XYZW, T11.X, 16, #1 -; EG-NEXT: VTX_READ_128 T11.XYZW, T11.X, 0, #1 -; EG-NEXT: ALU clause starting at 12: -; EG-NEXT: MOV * T11.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 13: +; EG-NEXT: Fetch clause starting at 10: +; EG-NEXT: VTX_READ_128 T37.XYZW, T35.X, 16, #1 +; EG-NEXT: VTX_READ_128 T35.XYZW, T35.X, 0, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: MOV * T0.Y, T16.X, +; EG-NEXT: MOV * T35.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 16: +; EG-NEXT: AND_INT T0.W, T37.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 255(3.573311e-43), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T16.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T0.W, T37.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T16.X, PV.W, +; EG-NEXT: MOV T0.Y, T17.X, ; EG-NEXT: MOV * T0.W, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT * T13.W, T11.Y, literal.x, PV.W, +; EG-NEXT: BFE_UINT T1.W, T37.X, literal.x, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), -65536(nan) +; EG-NEXT: OR_INT * T1.W, PS, PV.W, +; EG-NEXT: MOV * T17.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T37.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT T13.Y, T11.X, literal.x, T0.W, -; EG-NEXT: AND_INT T13.Z, T11.Y, literal.y, -; EG-NEXT: BFE_UINT * T14.W, T11.W, literal.x, T0.W, -; EG-NEXT: 8(1.121039e-44), 255(3.573311e-43) -; EG-NEXT: AND_INT T13.X, T11.X, literal.x, -; EG-NEXT: BFE_UINT T14.Y, T11.Z, literal.y, T0.W, -; EG-NEXT: LSHR * T11.X, KC0[2].Y, literal.z, -; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44) -; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; EG-NEXT: AND_INT T14.Z, T11.W, literal.x, -; EG-NEXT: BFE_UINT * T15.W, T12.Y, literal.y, T0.W, -; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44) -; EG-NEXT: AND_INT T14.X, T11.Z, literal.x, -; EG-NEXT: BFE_UINT T15.Y, T12.X, literal.y, T0.W, -; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z, -; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T36.Y, PV.W, PS, +; EG-NEXT: MOV T17.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T12.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T37.Y, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T12.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T37.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T12.X, PV.W, +; EG-NEXT: MOV T0.Y, T13.X, +; EG-NEXT: BFE_UINT * T1.W, T37.Y, literal.x, T0.W, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T16.X, PV.W, literal.x, -; EG-NEXT: AND_INT T15.Z, T12.Y, literal.y, -; EG-NEXT: BFE_UINT T17.W, T12.W, literal.z, T0.W, -; EG-NEXT: AND_INT * T15.X, T12.X, literal.y, -; EG-NEXT: 2(2.802597e-45), 255(3.573311e-43) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T13.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T37.Y, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT T17.Y, T12.Z, literal.x, T0.W, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, -; EG-NEXT: 8(1.121039e-44), 32(4.484155e-44) -; EG-NEXT: LSHR T12.X, PV.W, literal.x, -; EG-NEXT: AND_INT T17.Z, T12.W, literal.y, -; EG-NEXT: AND_INT * T17.X, T12.Z, literal.y, -; EG-NEXT: 2(2.802597e-45), 255(3.573311e-43) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T36.W, PV.W, PS, +; EG-NEXT: MOV T13.X, PV.W, +; EG-NEXT: MOV * T0.Y, T8.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T37.Z, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T37.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, +; EG-NEXT: BFE_UINT * T1.W, T37.Z, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T37.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T37.Y, PV.W, PS, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T37.W, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T37.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: BFE_UINT * T1.W, T37.W, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: ALU clause starting at 120: +; EG-NEXT: AND_INT * T2.W, T0.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T37.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T37.W, PV.W, PS, +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T0.Y, T32.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T35.X, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T32.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T35.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T32.X, PV.W, +; EG-NEXT: MOV T0.Y, T33.X, +; EG-NEXT: BFE_UINT * T1.W, T35.X, literal.x, T0.W, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T33.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T35.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T38.Y, PV.W, PS, +; EG-NEXT: MOV T33.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T28.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T35.Y, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T28.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T35.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T28.X, PV.W, +; EG-NEXT: MOV T0.Y, T29.X, +; EG-NEXT: BFE_UINT * T1.W, T35.Y, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T29.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T35.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T38.W, PV.W, PS, +; EG-NEXT: MOV T29.X, PV.W, +; EG-NEXT: MOV * T0.Y, T24.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T35.Z, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T24.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T35.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T24.X, PV.W, +; EG-NEXT: MOV T0.Y, T25.X, +; EG-NEXT: BFE_UINT * T1.W, T35.Z, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T25.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T35.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T35.Y, PV.W, PS, +; EG-NEXT: MOV T25.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T20.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T35.W, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T20.X, PV.W, +; EG-NEXT: ALU clause starting at 225: +; EG-NEXT: MOV T0.Y, T20.X, +; EG-NEXT: LSHL * T1.W, T35.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T20.X, PV.W, +; EG-NEXT: MOV T0.Y, T21.X, +; EG-NEXT: BFE_UINT * T0.W, T35.W, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PV.W, T0.W, +; EG-NEXT: MOV * T21.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, -; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) -; EG-NEXT: LSHR * T18.X, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T39.X, PV.W, literal.x, +; EG-NEXT: LSHR * T40.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: LSHR T0.W, T35.W, literal.x, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 48(6.726233e-44) +; EG-NEXT: LSHR T41.X, PS, literal.x, +; EG-NEXT: AND_INT T0.Z, T0.Y, literal.y, +; EG-NEXT: AND_INT T0.W, PV.W, literal.z, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w, +; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; EG-NEXT: 16711680(2.341805e-38), 32(4.484155e-44) +; EG-NEXT: LSHR T42.X, PS, literal.x, +; EG-NEXT: OR_INT * T35.W, PV.Z, PV.W, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T21.X, PV.W, +; EG-NEXT: MOV * T36.X, T16.X, +; EG-NEXT: MOV * T36.Z, T12.X, +; EG-NEXT: MOV T37.X, T8.X, +; EG-NEXT: MOV T37.Z, T4.X, BS:VEC_120/SCL_212 +; EG-NEXT: MOV * T38.X, T32.X, +; EG-NEXT: MOV * T38.Z, T28.X, +; EG-NEXT: MOV T35.X, T24.X, +; EG-NEXT: MOV * T35.Z, T20.X, BS:VEC_120/SCL_212 ; ; GFX12-LABEL: constant_zextload_v32i8_to_v32i16: ; GFX12: ; %bb.0: @@ -11642,60 +12281,331 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i16(ptr addrspace(1) %o ; ; EG-LABEL: constant_sextload_v32i8_to_v32i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 1 @8 -; EG-NEXT: ALU 39, @13, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T12.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T11.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T14.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T13.X, 1 +; EG-NEXT: ALU 1, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @10 +; EG-NEXT: ALU 104, @16, KC0[], KC1[] +; EG-NEXT: ALU 104, @121, KC0[], KC1[] +; EG-NEXT: ALU 95, @226, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T42.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T41.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T40.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T35.XYZW, T39.X, 1 ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 8: -; EG-NEXT: VTX_READ_128 T12.XYZW, T11.X, 16, #1 -; EG-NEXT: VTX_READ_128 T11.XYZW, T11.X, 0, #1 -; EG-NEXT: ALU clause starting at 12: -; EG-NEXT: MOV * T11.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 13: -; EG-NEXT: LSHR T13.X, KC0[2].Y, literal.x, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, -; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) -; EG-NEXT: LSHR T14.X, PV.W, literal.x, -; EG-NEXT: BFE_INT * T15.Z, T11.Y, 0.0, literal.y, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) -; EG-NEXT: BFE_INT T15.X, T11.X, 0.0, literal.x, -; EG-NEXT: LSHR T0.Y, T12.W, literal.x, -; EG-NEXT: BFE_INT T16.Z, T11.W, 0.0, literal.x, BS:VEC_120/SCL_212 -; EG-NEXT: LSHR T0.W, T12.Y, literal.x, -; EG-NEXT: LSHR * T1.W, T11.Y, literal.x, +; EG-NEXT: Fetch clause starting at 10: +; EG-NEXT: VTX_READ_128 T37.XYZW, T35.X, 16, #1 +; EG-NEXT: VTX_READ_128 T35.XYZW, T35.X, 0, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: MOV * T0.Y, T16.X, +; EG-NEXT: MOV * T35.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 16: +; EG-NEXT: BFE_INT * T0.W, T37.X, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T16.X, T11.Z, 0.0, literal.x, -; EG-NEXT: LSHR T1.Y, T11.W, literal.x, -; EG-NEXT: BFE_INT T17.Z, T12.Y, 0.0, literal.x, -; EG-NEXT: BFE_INT T15.W, PS, 0.0, literal.x, -; EG-NEXT: LSHR * T1.W, T11.X, literal.x, +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T16.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T37.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T17.X, T12.X, 0.0, literal.x, -; EG-NEXT: BFE_INT T15.Y, PS, 0.0, literal.x, -; EG-NEXT: BFE_INT T18.Z, T12.W, 0.0, literal.x, -; EG-NEXT: BFE_INT T16.W, PV.Y, 0.0, literal.x, -; EG-NEXT: LSHR * T1.W, T11.Z, literal.x, +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T16.X, PV.W, +; EG-NEXT: MOV T0.Y, T17.X, +; EG-NEXT: LSHR * T0.W, T37.X, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T17.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T37.X, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T36.Y, PV.W, PS, +; EG-NEXT: MOV T17.X, PV.Y, +; EG-NEXT: MOV T0.Y, T12.X, +; EG-NEXT: BFE_INT * T0.W, T37.Y, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T18.X, T12.Z, 0.0, literal.x, -; EG-NEXT: BFE_INT T16.Y, PS, 0.0, literal.x, -; EG-NEXT: LSHR T0.Z, T12.X, literal.x, -; EG-NEXT: BFE_INT T17.W, T0.W, 0.0, literal.x, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, -; EG-NEXT: 8(1.121039e-44), 32(4.484155e-44) -; EG-NEXT: LSHR T11.X, PS, literal.x, -; EG-NEXT: BFE_INT T17.Y, PV.Z, 0.0, literal.y, -; EG-NEXT: LSHR T0.Z, T12.Z, literal.y, -; EG-NEXT: BFE_INT T18.W, T0.Y, 0.0, literal.y, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) -; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T12.X, PS, literal.x, -; EG-NEXT: BFE_INT * T18.Y, PV.Z, 0.0, literal.y, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T12.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T37.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T12.X, PV.W, +; EG-NEXT: MOV T0.Y, T13.X, +; EG-NEXT: LSHR * T0.W, T37.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T13.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T37.Y, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T36.W, PV.W, PS, +; EG-NEXT: MOV T13.X, PV.W, +; EG-NEXT: MOV T0.Y, T8.X, +; EG-NEXT: BFE_INT * T0.W, T37.Z, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T37.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, +; EG-NEXT: LSHR * T0.W, T37.Z, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T37.Z, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: ALU clause starting at 121: +; EG-NEXT: OR_INT * T37.Y, T1.W, T0.W, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV T0.Y, T4.X, +; EG-NEXT: BFE_INT * T0.W, T37.W, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T37.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: LSHR * T0.W, T37.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T37.W, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T37.W, PV.W, PS, +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV T0.Y, T32.X, +; EG-NEXT: BFE_INT * T0.W, T35.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T32.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T35.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T32.X, PV.W, +; EG-NEXT: MOV T0.Y, T33.X, +; EG-NEXT: LSHR * T0.W, T35.X, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T33.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T35.X, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T38.Y, PV.W, PS, +; EG-NEXT: MOV T33.X, PV.Y, +; EG-NEXT: MOV T0.Y, T28.X, +; EG-NEXT: BFE_INT * T0.W, T35.Y, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T28.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T35.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T28.X, PV.W, +; EG-NEXT: MOV T0.Y, T29.X, +; EG-NEXT: LSHR * T0.W, T35.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T29.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T35.Y, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: ALU clause starting at 226: +; EG-NEXT: AND_INT T1.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T0.W, T0.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T38.W, PV.W, PS, +; EG-NEXT: MOV T29.X, PV.W, +; EG-NEXT: MOV T0.Y, T24.X, +; EG-NEXT: BFE_INT * T0.W, T35.Z, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T24.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T35.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T24.X, PV.W, +; EG-NEXT: MOV T0.Y, T25.X, +; EG-NEXT: LSHR * T0.W, T35.Z, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T25.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T35.Z, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T35.Y, PV.W, PS, +; EG-NEXT: MOV T25.X, PV.Y, +; EG-NEXT: MOV T0.Y, T20.X, +; EG-NEXT: BFE_INT * T0.W, T35.W, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T20.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T35.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T20.X, PV.W, +; EG-NEXT: MOV T0.Y, T21.X, +; EG-NEXT: LSHR * T0.W, T35.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T21.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T39.X, PV.W, literal.x, +; EG-NEXT: LSHR * T40.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ASHR T0.W, T35.W, literal.x, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y, +; EG-NEXT: 24(3.363116e-44), 48(6.726233e-44) +; EG-NEXT: LSHR T41.X, PS, literal.x, +; EG-NEXT: AND_INT T0.Z, T0.Y, literal.y, +; EG-NEXT: LSHL T0.W, PV.W, literal.z, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w, +; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; EG-NEXT: 16(2.242078e-44), 32(4.484155e-44) +; EG-NEXT: LSHR T42.X, PS, literal.x, +; EG-NEXT: OR_INT * T35.W, PV.Z, PV.W, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T21.X, PV.W, +; EG-NEXT: MOV * T36.X, T16.X, +; EG-NEXT: MOV * T36.Z, T12.X, +; EG-NEXT: MOV T37.X, T8.X, +; EG-NEXT: MOV T37.Z, T4.X, BS:VEC_120/SCL_212 +; EG-NEXT: MOV * T38.X, T32.X, +; EG-NEXT: MOV * T38.Z, T28.X, +; EG-NEXT: MOV T35.X, T24.X, +; EG-NEXT: MOV * T35.Z, T20.X, BS:VEC_120/SCL_212 ; ; GFX12-LABEL: constant_sextload_v32i8_to_v32i16: ; GFX12: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll index 3753737..ff5b9aa 100644 --- a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll @@ -263,63 +263,74 @@ define amdgpu_kernel void @global_load_v3i16(ptr addrspace(1) %out, ptr addrspac ; ; EG-LABEL: global_load_v3i16: ; EG: ; %bb.0: ; %entry -; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 1 @6 -; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T3.X, 0 -; EG-NEXT: MEM_RAT MSKOR T2.XW, T0.X +; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 2 @6 +; EG-NEXT: ALU 19, @13, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T7.X, 0 +; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X ; EG-NEXT: CF_END ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_16 T1.X, T0.X, 0, #1 -; EG-NEXT: VTX_READ_16 T0.X, T0.X, 4, #1 -; EG-NEXT: ALU clause starting at 10: -; EG-NEXT: MOV * T0.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 11: +; EG-NEXT: VTX_READ_16 T6.X, T5.X, 0, #1 +; EG-NEXT: VTX_READ_16 T7.X, T5.X, 2, #1 +; EG-NEXT: VTX_READ_16 T5.X, T5.X, 4, #1 +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T5.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 13: ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, ; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00) ; EG-NEXT: AND_INT T1.W, PV.W, literal.x, -; EG-NEXT: AND_INT * T2.W, T0.X, literal.y, +; EG-NEXT: AND_INT * T2.W, T5.X, literal.y, ; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41) ; EG-NEXT: LSHL * T1.W, PV.W, literal.x, ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) -; EG-NEXT: LSHL T2.X, T2.W, PV.W, -; EG-NEXT: LSHL * T2.W, literal.x, PV.W, +; EG-NEXT: LSHL T5.X, T2.W, PV.W, +; EG-NEXT: LSHL * T5.W, literal.x, PV.W, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: MOV T5.Y, 0.0, +; EG-NEXT: MOV * T5.Z, 0.0, +; EG-NEXT: LSHR T8.X, T0.W, literal.x, +; EG-NEXT: LSHL T0.W, T7.X, literal.y, +; EG-NEXT: AND_INT * T1.W, T6.X, literal.z, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: MOV T2.Y, 0.0, -; EG-NEXT: MOV * T2.Z, 0.0, -; EG-NEXT: LSHR T0.X, T0.W, literal.x, -; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT T6.X, PV.W, PS, +; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; ; CM-LABEL: global_load_v3i16: ; CM: ; %bb.0: ; %entry -; CM-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] -; CM-NEXT: TEX 1 @6 -; CM-NEXT: ALU 15, @11, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT MSKOR T2.XW, T3.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 2 @6 +; CM-NEXT: ALU 19, @13, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT MSKOR T5.XW, T8.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T6.X, T7.X ; CM-NEXT: CF_END ; CM-NEXT: Fetch clause starting at 6: -; CM-NEXT: VTX_READ_16 T1.X, T0.X, 0, #1 -; CM-NEXT: VTX_READ_16 T0.X, T0.X, 4, #1 -; CM-NEXT: ALU clause starting at 10: -; CM-NEXT: MOV * T0.X, KC0[2].Z, -; CM-NEXT: ALU clause starting at 11: +; CM-NEXT: VTX_READ_16 T6.X, T5.X, 0, #1 +; CM-NEXT: VTX_READ_16 T7.X, T5.X, 2, #1 +; CM-NEXT: VTX_READ_16 T5.X, T5.X, 4, #1 +; CM-NEXT: ALU clause starting at 12: +; CM-NEXT: MOV * T5.X, KC0[2].Z, +; CM-NEXT: ALU clause starting at 13: ; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, ; CM-NEXT: 4(5.605194e-45), 0(0.000000e+00) ; CM-NEXT: AND_INT * T1.W, PV.W, literal.x, ; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00) -; CM-NEXT: AND_INT T0.Z, T0.X, literal.x, +; CM-NEXT: AND_INT T0.Z, T5.X, literal.x, ; CM-NEXT: LSHL * T1.W, PV.W, literal.y, ; CM-NEXT: 65535(9.183409e-41), 3(4.203895e-45) -; CM-NEXT: LSHL T2.X, PV.Z, PV.W, -; CM-NEXT: LSHL * T2.W, literal.x, PV.W, +; CM-NEXT: LSHL T5.X, PV.Z, PV.W, +; CM-NEXT: LSHL * T5.W, literal.x, PV.W, ; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; CM-NEXT: MOV T2.Y, 0.0, -; CM-NEXT: MOV * T2.Z, 0.0, -; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, +; CM-NEXT: MOV T5.Y, 0.0, +; CM-NEXT: MOV * T5.Z, 0.0, +; CM-NEXT: LSHL T0.Z, T7.X, literal.x, +; CM-NEXT: AND_INT * T1.W, T6.X, literal.y, BS:VEC_120/SCL_212 +; CM-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T6.X, PV.Z, PV.W, +; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; CM-NEXT: LSHR * T3.X, T0.W, literal.x, +; CM-NEXT: LSHR * T8.X, T0.W, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) entry: %ld = load <3 x i16>, ptr addrspace(1) %in diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll index 5bc02c4..6a39df9 100644 --- a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll +++ b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll @@ -9887,46 +9887,97 @@ define amdgpu_kernel void @global_zextload_v4i8_to_v4i16(ptr addrspace(1) %out, ; ; EG-LABEL: global_zextload_v4i8_to_v4i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 6, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XY, T5.X, 1 +; EG-NEXT: ALU 31, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XY, T7.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1 +; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T4.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: MOV * T7.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: AND_INT T0.W, T7.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 255(3.573311e-43), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T0.W, T7.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, ; EG-NEXT: MOV * T0.W, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT * T4.Y, T4.X, literal.x, PV.W, +; EG-NEXT: BFE_UINT T0.W, T7.X, literal.x, PV.W, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T7.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: AND_INT T4.X, T4.X, literal.x, -; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.y, -; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: LSHR T7.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T8.Y, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.Y, +; EG-NEXT: MOV * T8.X, T4.X, ; ; CM-LABEL: global_zextload_v4i8_to_v4i16: ; CM: ; %bb.0: -; CM-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; CM-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; CM-NEXT: TEX 0 @6 -; CM-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4, T5.X +; CM-NEXT: ALU 31, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T8, T7.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: Fetch clause starting at 6: -; CM-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1 +; CM-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1 ; CM-NEXT: ALU clause starting at 8: -; CM-NEXT: MOV * T4.X, KC0[2].Z, -; CM-NEXT: ALU clause starting at 9: +; CM-NEXT: MOV * T0.Y, T4.X, +; CM-NEXT: MOV * T7.X, KC0[2].Z, +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: AND_INT T0.Z, T7.X, literal.x, +; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y, +; CM-NEXT: 255(3.573311e-43), -65536(nan) +; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z, +; CM-NEXT: MOV * T4.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T0.W, T7.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.W, +; CM-NEXT: MOV T0.Y, T5.X, ; CM-NEXT: MOV * T0.W, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_UINT * T4.Y, T4.X, literal.x, PV.W, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T0.W, T7.X, literal.y, PV.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T7.X, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: AND_INT * T4.X, T4.X, literal.x, -; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00) -; CM-NEXT: LSHR * T5.X, KC0[2].Y, literal.x, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: LSHR T7.X, KC0[2].Y, literal.x, +; CM-NEXT: OR_INT * T8.Y, PV.Z, PV.W, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T5.X, PV.Y, +; CM-NEXT: MOV * T8.X, T4.X, %load = load <4 x i8>, ptr addrspace(1) %in %ext = zext <4 x i8> %load to <4 x i16> store <4 x i16> %ext, ptr addrspace(1) %out @@ -10017,43 +10068,109 @@ define amdgpu_kernel void @global_sextload_v4i8_to_v4i16(ptr addrspace(1) %out, ; ; EG-LABEL: global_sextload_v4i8_to_v4i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 5, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XY, T4.X, 1 +; EG-NEXT: ALU 37, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XY, T7.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1 +; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T4.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: -; EG-NEXT: BFE_INT T5.X, T4.X, 0.0, literal.x, -; EG-NEXT: LSHR T0.W, T4.X, literal.x, -; EG-NEXT: LSHR * T4.X, KC0[2].Y, literal.y, -; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45) -; EG-NEXT: BFE_INT * T5.Y, PV.W, 0.0, literal.x, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: MOV * T7.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: BFE_INT * T0.W, T7.X, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T7.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: LSHR * T0.W, T7.X, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T7.X, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: LSHR T7.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T8.Y, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.Y, +; EG-NEXT: MOV * T8.X, T4.X, ; ; CM-LABEL: global_sextload_v4i8_to_v4i16: ; CM: ; %bb.0: -; CM-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; CM-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; CM-NEXT: TEX 0 @6 -; CM-NEXT: ALU 5, @9, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T5, T4.X +; CM-NEXT: ALU 37, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T8, T7.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: Fetch clause starting at 6: -; CM-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1 +; CM-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1 ; CM-NEXT: ALU clause starting at 8: -; CM-NEXT: MOV * T4.X, KC0[2].Z, -; CM-NEXT: ALU clause starting at 9: -; CM-NEXT: BFE_INT T5.X, T4.X, 0.0, literal.x, -; CM-NEXT: LSHR * T0.W, T4.X, literal.x, +; CM-NEXT: MOV * T0.Y, T4.X, +; CM-NEXT: MOV * T7.X, KC0[2].Z, +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: BFE_INT * T0.W, T7.X, 0.0, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: LSHR T4.X, KC0[2].Y, literal.x, -; CM-NEXT: BFE_INT * T5.Y, PV.W, 0.0, literal.y, -; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; CM-NEXT: AND_INT T0.Z, PV.W, literal.x, +; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y, +; CM-NEXT: 65535(9.183409e-41), -65536(nan) +; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z, +; CM-NEXT: MOV * T4.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T7.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.W, +; CM-NEXT: MOV T0.Y, T5.X, +; CM-NEXT: LSHR * T0.W, T7.X, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T7.X, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: LSHR T7.X, KC0[2].Y, literal.x, +; CM-NEXT: OR_INT * T8.Y, PV.Z, PV.W, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T5.X, PV.Y, +; CM-NEXT: MOV * T8.X, T4.X, %load = load <4 x i8>, ptr addrspace(1) %in %ext = sext <4 x i8> %load to <4 x i16> store <4 x i16> %ext, ptr addrspace(1) %out @@ -10158,52 +10275,156 @@ define amdgpu_kernel void @global_zextload_v8i8_to_v8i16(ptr addrspace(1) %out, ; ; EG-LABEL: global_zextload_v8i8_to_v8i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T5.X, 1 +; EG-NEXT: ALU 61, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T11.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_64 T5.XY, T5.X, 0, #1 +; EG-NEXT: VTX_READ_64 T11.XY, T11.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T5.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: MOV * T0.Y, T8.X, +; EG-NEXT: MOV * T11.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: AND_INT T0.W, T11.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 255(3.573311e-43), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T0.W, T11.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, ; EG-NEXT: MOV * T0.W, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT * T6.W, T5.Y, literal.x, PV.W, +; EG-NEXT: BFE_UINT T1.W, T11.X, literal.x, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), -65536(nan) +; EG-NEXT: OR_INT * T1.W, PS, PV.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T11.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT T6.Y, T5.X, literal.x, T0.W, -; EG-NEXT: AND_INT * T6.Z, T5.Y, literal.y, -; EG-NEXT: 8(1.121039e-44), 255(3.573311e-43) -; EG-NEXT: AND_INT T6.X, T5.X, literal.x, -; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.y, -; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T12.Y, PV.W, PS, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T11.Y, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T11.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: BFE_UINT * T0.W, T11.Y, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PV.W, T0.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T11.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: LSHR T11.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T12.W, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T12.X, T8.X, +; EG-NEXT: MOV * T12.Z, T4.X, ; ; CM-LABEL: global_zextload_v8i8_to_v8i16: ; CM: ; %bb.0: -; CM-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; CM-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; CM-NEXT: TEX 0 @6 -; CM-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T6, T5.X +; CM-NEXT: ALU 60, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T12, T11.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: Fetch clause starting at 6: -; CM-NEXT: VTX_READ_64 T5.XY, T5.X, 0, #1 +; CM-NEXT: VTX_READ_64 T11.XY, T11.X, 0, #1 ; CM-NEXT: ALU clause starting at 8: -; CM-NEXT: MOV * T5.X, KC0[2].Z, -; CM-NEXT: ALU clause starting at 9: +; CM-NEXT: MOV * T0.Y, T8.X, +; CM-NEXT: MOV * T11.X, KC0[2].Z, +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: AND_INT T0.Z, T11.X, literal.x, +; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y, +; CM-NEXT: 255(3.573311e-43), -65536(nan) +; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z, +; CM-NEXT: MOV * T8.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T0.W, T11.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T8.X, PV.W, +; CM-NEXT: MOV T0.Y, T9.X, ; CM-NEXT: MOV * T0.W, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_UINT * T6.W, T5.Y, literal.x, PV.W, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T1.W, T11.X, literal.y, PV.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T9.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T11.X, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_UINT T6.Y, T5.X, literal.x, T0.W, -; CM-NEXT: AND_INT * T6.Z, T5.Y, literal.y, -; CM-NEXT: 8(1.121039e-44), 255(3.573311e-43) -; CM-NEXT: AND_INT * T6.X, T5.X, literal.x, -; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00) -; CM-NEXT: LSHR * T5.X, KC0[2].Y, literal.x, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T12.Y, PV.Z, PV.W, +; CM-NEXT: MOV T9.X, PV.Y, +; CM-NEXT: MOV * T0.Y, T4.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T11.Y, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T4.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T1.W, T11.Y, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.W, +; CM-NEXT: MOV * T0.Y, T5.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T0.W, T11.Y, literal.y, T0.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T11.Y, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: LSHR T11.X, KC0[2].Y, literal.x, +; CM-NEXT: OR_INT * T12.W, PV.Z, PV.W, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T12.X, T8.X, +; CM-NEXT: MOV * T12.Z, T4.X, BS:VEC_120/SCL_212 %load = load <8 x i8>, ptr addrspace(1) %in %ext = zext <8 x i8> %load to <8 x i16> store <8 x i16> %ext, ptr addrspace(1) %out @@ -10344,53 +10565,183 @@ define amdgpu_kernel void @global_sextload_v8i8_to_v8i16(ptr addrspace(1) %out, ; ; EG-LABEL: global_sextload_v8i8_to_v8i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T5.X, 1 +; EG-NEXT: ALU 74, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T11.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_64 T5.XY, T5.X, 0, #1 +; EG-NEXT: VTX_READ_64 T11.XY, T11.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T5.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: -; EG-NEXT: BFE_INT * T6.Z, T5.Y, 0.0, literal.x, +; EG-NEXT: MOV * T0.Y, T8.X, +; EG-NEXT: MOV * T11.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: BFE_INT * T0.W, T11.X, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T6.X, T5.X, 0.0, literal.x, -; EG-NEXT: LSHR * T0.W, T5.Y, literal.x, +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T11.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T6.W, PV.W, 0.0, literal.x, -; EG-NEXT: LSHR * T0.W, T5.X, literal.x, +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, +; EG-NEXT: LSHR * T0.W, T11.X, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T11.X, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T12.Y, PV.W, PS, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV T0.Y, T4.X, +; EG-NEXT: BFE_INT * T0.W, T11.Y, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T5.X, KC0[2].Y, literal.x, -; EG-NEXT: BFE_INT * T6.Y, PS, 0.0, literal.y, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T11.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: LSHR * T0.W, T11.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T11.Y, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: LSHR T11.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T12.W, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T12.X, T8.X, +; EG-NEXT: MOV * T12.Z, T4.X, ; ; CM-LABEL: global_sextload_v8i8_to_v8i16: ; CM: ; %bb.0: -; CM-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; CM-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; CM-NEXT: TEX 0 @6 -; CM-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T6, T5.X +; CM-NEXT: ALU 74, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T12, T11.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: Fetch clause starting at 6: -; CM-NEXT: VTX_READ_64 T5.XY, T5.X, 0, #1 +; CM-NEXT: VTX_READ_64 T11.XY, T11.X, 0, #1 ; CM-NEXT: ALU clause starting at 8: -; CM-NEXT: MOV * T5.X, KC0[2].Z, -; CM-NEXT: ALU clause starting at 9: -; CM-NEXT: BFE_INT * T6.Z, T5.Y, 0.0, literal.x, +; CM-NEXT: MOV * T0.Y, T8.X, +; CM-NEXT: MOV * T11.X, KC0[2].Z, +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: BFE_INT * T0.W, T11.X, 0.0, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_INT T6.X, T5.X, 0.0, literal.x, -; CM-NEXT: LSHR * T0.W, T5.Y, literal.x, +; CM-NEXT: AND_INT T0.Z, PV.W, literal.x, +; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y, +; CM-NEXT: 65535(9.183409e-41), -65536(nan) +; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z, +; CM-NEXT: MOV * T8.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T11.X, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: LSHR T0.Z, T5.X, literal.x, -; CM-NEXT: BFE_INT * T6.W, PV.W, 0.0, literal.x, +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: LSHR T5.X, KC0[2].Y, literal.x, -; CM-NEXT: BFE_INT * T6.Y, PV.Z, 0.0, literal.y, -; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T8.X, PV.W, +; CM-NEXT: MOV T0.Y, T9.X, +; CM-NEXT: LSHR * T0.W, T11.X, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T9.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T11.X, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T12.Y, PV.Z, PV.W, +; CM-NEXT: MOV T9.X, PV.Y, +; CM-NEXT: MOV T0.Y, T4.X, +; CM-NEXT: BFE_INT * T0.W, T11.Y, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T4.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T11.Y, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.W, +; CM-NEXT: MOV T0.Y, T5.X, +; CM-NEXT: LSHR * T0.W, T11.Y, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T11.Y, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: LSHR T11.X, KC0[2].Y, literal.x, +; CM-NEXT: OR_INT * T12.W, PV.Z, PV.W, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T12.X, T8.X, +; CM-NEXT: MOV * T12.Z, T4.X, BS:VEC_120/SCL_212 %load = load <8 x i8>, ptr addrspace(1) %in %ext = sext <8 x i8> %load to <8 x i16> store <8 x i16> %ext, ptr addrspace(1) %out @@ -10547,71 +10898,287 @@ define amdgpu_kernel void @global_zextload_v16i8_to_v16i16(ptr addrspace(1) %out ; ; EG-LABEL: global_zextload_v16i8_to_v16i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 19, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T10.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T7.X, 1 +; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @8 +; EG-NEXT: ALU 103, @12, KC0[], KC1[] +; EG-NEXT: ALU 20, @116, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T22.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T21.X, 1 ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1 -; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T7.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T19.XYZW, T19.X, 0, #1 +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: MOV * T0.Y, T16.X, +; EG-NEXT: MOV * T19.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: AND_INT T0.W, T19.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 255(3.573311e-43), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T16.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T0.W, T19.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T16.X, PV.W, +; EG-NEXT: MOV T0.Y, T17.X, ; EG-NEXT: MOV * T0.W, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT * T8.W, T7.Y, literal.x, PV.W, +; EG-NEXT: BFE_UINT T1.W, T19.X, literal.x, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), -65536(nan) +; EG-NEXT: OR_INT * T1.W, PS, PV.W, +; EG-NEXT: MOV * T17.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T19.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T20.Y, PV.W, PS, +; EG-NEXT: MOV T17.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T12.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T19.Y, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T12.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T19.Y, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT T8.Y, T7.X, literal.x, T0.W, -; EG-NEXT: AND_INT T8.Z, T7.Y, literal.y, -; EG-NEXT: BFE_UINT * T9.W, T7.W, literal.x, T0.W, -; EG-NEXT: 8(1.121039e-44), 255(3.573311e-43) -; EG-NEXT: AND_INT T8.X, T7.X, literal.x, -; EG-NEXT: BFE_UINT T9.Y, T7.Z, literal.y, T0.W, -; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.z, -; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44) -; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; EG-NEXT: AND_INT * T9.Z, T7.W, literal.x, -; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) -; EG-NEXT: AND_INT T9.X, T7.Z, literal.x, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, -; EG-NEXT: 255(3.573311e-43), 16(2.242078e-44) -; EG-NEXT: LSHR * T10.X, PV.W, literal.x, +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T12.X, PV.W, +; EG-NEXT: MOV T0.Y, T13.X, +; EG-NEXT: BFE_UINT * T1.W, T19.Y, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T13.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T19.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T20.W, PV.W, PS, +; EG-NEXT: MOV T13.X, PV.W, +; EG-NEXT: MOV * T0.Y, T8.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T19.Z, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T19.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, +; EG-NEXT: BFE_UINT * T1.W, T19.Z, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T19.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T19.Y, PV.W, PS, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T19.W, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T19.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: BFE_UINT * T0.W, T19.W, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: ALU clause starting at 116: +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PV.W, T0.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR T0.W, T19.W, literal.x, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44) +; EG-NEXT: LSHR T21.X, PS, literal.x, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.y, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.z, +; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; EG-NEXT: 16711680(2.341805e-38), 0(0.000000e+00) +; EG-NEXT: LSHR T22.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T19.W, PV.W, PS, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T20.X, T16.X, +; EG-NEXT: MOV * T20.Z, T12.X, +; EG-NEXT: MOV T19.X, T8.X, +; EG-NEXT: MOV * T19.Z, T4.X, BS:VEC_120/SCL_212 ; ; CM-LABEL: global_zextload_v16i8_to_v16i16: ; CM: ; %bb.0: -; CM-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] -; CM-NEXT: TEX 0 @6 -; CM-NEXT: ALU 19, @9, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T9, T7.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T8, T10.X +; CM-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 0 @8 +; CM-NEXT: ALU 101, @12, KC0[], KC1[] +; CM-NEXT: ALU 20, @114, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T19, T22.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T20, T21.X ; CM-NEXT: CF_END -; CM-NEXT: Fetch clause starting at 6: -; CM-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1 -; CM-NEXT: ALU clause starting at 8: -; CM-NEXT: MOV * T7.X, KC0[2].Z, -; CM-NEXT: ALU clause starting at 9: +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 8: +; CM-NEXT: VTX_READ_128 T19.XYZW, T19.X, 0, #1 +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: MOV * T0.Y, T16.X, +; CM-NEXT: MOV * T19.X, KC0[2].Z, +; CM-NEXT: ALU clause starting at 12: +; CM-NEXT: AND_INT T0.Z, T19.X, literal.x, +; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y, +; CM-NEXT: 255(3.573311e-43), -65536(nan) +; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z, +; CM-NEXT: MOV * T16.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T0.W, T19.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T16.X, PV.W, +; CM-NEXT: MOV T0.Y, T17.X, ; CM-NEXT: MOV * T0.W, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_UINT * T8.W, T7.W, literal.x, PV.W, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T1.W, T19.X, literal.y, PV.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T17.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T19.X, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_UINT T8.Y, T7.Z, literal.x, T0.W, -; CM-NEXT: AND_INT T8.Z, T7.W, literal.y, -; CM-NEXT: BFE_UINT * T9.W, T7.Y, literal.x, T0.W, -; CM-NEXT: 8(1.121039e-44), 255(3.573311e-43) -; CM-NEXT: AND_INT T8.X, T7.Z, literal.x, -; CM-NEXT: BFE_UINT T9.Y, T7.X, literal.y, T0.W, -; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z, -; CM-NEXT: 255(3.573311e-43), 8(1.121039e-44) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T20.Y, PV.Z, PV.W, +; CM-NEXT: MOV T17.X, PV.Y, +; CM-NEXT: MOV * T0.Y, T12.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T19.Y, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T12.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T1.W, T19.Y, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T12.X, PV.W, +; CM-NEXT: MOV * T0.Y, T13.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T1.W, T19.Y, literal.y, T0.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T13.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T19.Y, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T20.W, PV.Z, PV.W, +; CM-NEXT: MOV T13.X, PV.W, +; CM-NEXT: MOV * T0.Y, T8.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T19.Z, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T8.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T1.W, T19.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T8.X, PV.W, +; CM-NEXT: MOV * T0.Y, T9.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T1.W, T19.Z, literal.y, T0.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T9.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T19.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T19.Y, PV.Z, PV.W, +; CM-NEXT: MOV T9.X, PV.Y, +; CM-NEXT: MOV * T0.Y, T4.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T19.W, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T4.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T1.W, T19.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.W, +; CM-NEXT: MOV * T0.Y, T5.X, +; CM-NEXT: AND_INT * T0.Z, PV.Y, literal.x, +; CM-NEXT: -65536(nan), 0(0.000000e+00) +; CM-NEXT: ALU clause starting at 114: +; CM-NEXT: BFE_UINT * T0.W, T19.W, literal.x, T0.W, ; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; CM-NEXT: LSHR T10.X, PV.W, literal.x, -; CM-NEXT: AND_INT * T9.Z, T7.Y, literal.y, -; CM-NEXT: 2(2.802597e-45), 255(3.573311e-43) -; CM-NEXT: AND_INT * T9.X, T7.X, literal.x, -; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00) -; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, +; CM-NEXT: OR_INT * T0.W, T0.Z, PV.W, +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T19.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: LSHR T21.X, KC0[2].Y, literal.x, +; CM-NEXT: AND_INT T0.Y, PV.Y, literal.y, +; CM-NEXT: AND_INT T0.Z, PV.W, literal.z, +; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.w, +; CM-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; CM-NEXT: 16711680(2.341805e-38), 16(2.242078e-44) +; CM-NEXT: LSHR T22.X, PV.W, literal.x, +; CM-NEXT: OR_INT * T19.W, PV.Y, PV.Z, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T20.X, T16.X, +; CM-NEXT: MOV * T20.Z, T12.X, BS:VEC_120/SCL_212 +; CM-NEXT: MOV T19.X, T8.X, +; CM-NEXT: MOV * T19.Z, T4.X, BS:VEC_120/SCL_212 %load = load <16 x i8>, ptr addrspace(1) %in %ext = zext <16 x i8> %load to <16 x i16> store <16 x i16> %ext, ptr addrspace(1) %out @@ -10844,72 +11411,343 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i16(ptr addrspace(1) %out ; ; EG-LABEL: global_sextload_v16i8_to_v16i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 20, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T10.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T7.X, 1 +; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @8 +; EG-NEXT: ALU 104, @12, KC0[], KC1[] +; EG-NEXT: ALU 46, @117, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T22.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T21.X, 1 ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1 -; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T7.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: -; EG-NEXT: BFE_INT * T8.Z, T7.Y, 0.0, literal.x, +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_128 T19.XYZW, T19.X, 0, #1 +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: MOV * T0.Y, T16.X, +; EG-NEXT: MOV * T19.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: BFE_INT * T0.W, T19.X, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T8.X, T7.X, 0.0, literal.x, -; EG-NEXT: BFE_INT T9.Z, T7.W, 0.0, literal.x, -; EG-NEXT: LSHR * T0.W, T7.Y, literal.x, +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T16.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T19.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T9.X, T7.Z, 0.0, literal.x, -; EG-NEXT: LSHR T0.Z, T7.W, literal.x, -; EG-NEXT: BFE_INT T8.W, PV.W, 0.0, literal.x, -; EG-NEXT: LSHR * T0.W, T7.X, literal.x, +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T16.X, PV.W, +; EG-NEXT: MOV T0.Y, T17.X, +; EG-NEXT: LSHR * T0.W, T19.X, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T17.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T19.X, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T20.Y, PV.W, PS, +; EG-NEXT: MOV T17.X, PV.Y, +; EG-NEXT: MOV T0.Y, T12.X, +; EG-NEXT: BFE_INT * T0.W, T19.Y, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T7.X, KC0[2].Y, literal.x, -; EG-NEXT: BFE_INT T8.Y, PS, 0.0, literal.y, -; EG-NEXT: LSHR T1.Z, T7.Z, literal.y, -; EG-NEXT: BFE_INT T9.W, PV.Z, 0.0, literal.y, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T12.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T19.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T10.X, PS, literal.x, -; EG-NEXT: BFE_INT * T9.Y, PV.Z, 0.0, literal.y, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T12.X, PV.W, +; EG-NEXT: MOV T0.Y, T13.X, +; EG-NEXT: LSHR * T0.W, T19.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T13.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T19.Y, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T20.W, PV.W, PS, +; EG-NEXT: MOV T13.X, PV.W, +; EG-NEXT: MOV T0.Y, T8.X, +; EG-NEXT: BFE_INT * T0.W, T19.Z, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T19.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, +; EG-NEXT: LSHR * T0.W, T19.Z, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T19.Z, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: ALU clause starting at 117: +; EG-NEXT: OR_INT * T19.Y, T1.W, T0.W, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV T0.Y, T4.X, +; EG-NEXT: BFE_INT * T0.W, T19.W, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T19.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: LSHR * T0.W, T19.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR T0.W, T19.W, literal.x, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y, +; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44) +; EG-NEXT: LSHR T21.X, PS, literal.x, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.y, +; EG-NEXT: LSHL * T0.W, PV.W, literal.z, +; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T22.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T19.W, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T20.X, T16.X, +; EG-NEXT: MOV * T20.Z, T12.X, +; EG-NEXT: MOV T19.X, T8.X, +; EG-NEXT: MOV * T19.Z, T4.X, BS:VEC_120/SCL_212 ; ; CM-LABEL: global_sextload_v16i8_to_v16i16: ; CM: ; %bb.0: -; CM-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] -; CM-NEXT: TEX 0 @6 -; CM-NEXT: ALU 19, @9, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T9, T7.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T8, T10.X +; CM-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 0 @8 +; CM-NEXT: ALU 104, @12, KC0[], KC1[] +; CM-NEXT: ALU 46, @117, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T19, T22.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T20, T21.X ; CM-NEXT: CF_END -; CM-NEXT: Fetch clause starting at 6: -; CM-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1 -; CM-NEXT: ALU clause starting at 8: -; CM-NEXT: MOV * T7.X, KC0[2].Z, -; CM-NEXT: ALU clause starting at 9: -; CM-NEXT: BFE_INT * T8.Z, T7.W, 0.0, literal.x, +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 8: +; CM-NEXT: VTX_READ_128 T19.XYZW, T19.X, 0, #1 +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: MOV * T0.Y, T16.X, +; CM-NEXT: MOV * T19.X, KC0[2].Z, +; CM-NEXT: ALU clause starting at 12: +; CM-NEXT: BFE_INT * T0.W, T19.X, 0.0, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_INT T8.X, T7.Z, 0.0, literal.x, -; CM-NEXT: LSHR T0.Y, T7.Y, literal.x, -; CM-NEXT: BFE_INT T9.Z, T7.Y, 0.0, literal.x, -; CM-NEXT: LSHR * T0.W, T7.W, literal.x, +; CM-NEXT: AND_INT T0.Z, PV.W, literal.x, +; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y, +; CM-NEXT: 65535(9.183409e-41), -65536(nan) +; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z, +; CM-NEXT: MOV * T16.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T19.X, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_INT T9.X, T7.X, 0.0, literal.x, -; CM-NEXT: LSHR T1.Y, T7.Z, literal.x, -; CM-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.y, -; CM-NEXT: BFE_INT * T8.W, PV.W, 0.0, literal.x, -; CM-NEXT: 8(1.121039e-44), 16(2.242078e-44) -; CM-NEXT: LSHR T10.X, PV.Z, literal.x, -; CM-NEXT: BFE_INT T8.Y, PV.Y, 0.0, literal.y, -; CM-NEXT: LSHR T0.Z, T7.X, literal.y, -; CM-NEXT: BFE_INT * T9.W, T0.Y, 0.0, literal.y, -; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44) -; CM-NEXT: LSHR T7.X, KC0[2].Y, literal.x, -; CM-NEXT: BFE_INT * T9.Y, PV.Z, 0.0, literal.y, -; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T16.X, PV.W, +; CM-NEXT: MOV T0.Y, T17.X, +; CM-NEXT: LSHR * T0.W, T19.X, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T17.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T19.X, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T20.Y, PV.Z, PV.W, +; CM-NEXT: MOV T17.X, PV.Y, +; CM-NEXT: MOV T0.Y, T12.X, +; CM-NEXT: BFE_INT * T0.W, T19.Y, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T12.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T19.Y, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T12.X, PV.W, +; CM-NEXT: MOV T0.Y, T13.X, +; CM-NEXT: LSHR * T0.W, T19.Y, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T13.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T19.Y, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T20.W, PV.Z, PV.W, +; CM-NEXT: MOV T13.X, PV.W, +; CM-NEXT: MOV T0.Y, T8.X, +; CM-NEXT: BFE_INT * T0.W, T19.Z, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T8.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T19.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T8.X, PV.W, +; CM-NEXT: MOV T0.Y, T9.X, +; CM-NEXT: LSHR * T0.W, T19.Z, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T9.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T19.Z, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: ALU clause starting at 117: +; CM-NEXT: OR_INT * T19.Y, T0.Z, T0.W, +; CM-NEXT: MOV T9.X, PV.Y, +; CM-NEXT: MOV T0.Y, T4.X, +; CM-NEXT: BFE_INT * T0.W, T19.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T4.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T19.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.W, +; CM-NEXT: MOV T0.Y, T5.X, +; CM-NEXT: LSHR * T0.W, T19.W, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T19.W, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: LSHR T21.X, KC0[2].Y, literal.x, +; CM-NEXT: AND_INT T0.Y, PV.Y, literal.y, +; CM-NEXT: LSHL T0.Z, PV.W, literal.z, +; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z, +; CM-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR T22.X, PV.W, literal.x, +; CM-NEXT: OR_INT * T19.W, PV.Y, PV.Z, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T20.X, T16.X, +; CM-NEXT: MOV * T20.Z, T12.X, BS:VEC_120/SCL_212 +; CM-NEXT: MOV T19.X, T8.X, +; CM-NEXT: MOV * T19.Z, T4.X, BS:VEC_120/SCL_212 %load = load <16 x i8>, ptr addrspace(1) %in %ext = sext <16 x i8> %load to <16 x i16> store <16 x i16> %ext, ptr addrspace(1) %out @@ -11181,115 +12019,543 @@ define amdgpu_kernel void @global_zextload_v32i8_to_v32i16(ptr addrspace(1) %out ; ; EG-LABEL: global_zextload_v32i8_to_v32i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 1 @8 -; EG-NEXT: ALU 37, @13, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T18.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T12.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T16.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T11.X, 1 +; EG-NEXT: ALU 1, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @10 +; EG-NEXT: ALU 103, @16, KC0[], KC1[] +; EG-NEXT: ALU 104, @120, KC0[], KC1[] +; EG-NEXT: ALU 41, @225, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T42.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T41.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T40.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T35.XYZW, T39.X, 1 ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 8: -; EG-NEXT: VTX_READ_128 T12.XYZW, T11.X, 16, #1 -; EG-NEXT: VTX_READ_128 T11.XYZW, T11.X, 0, #1 -; EG-NEXT: ALU clause starting at 12: -; EG-NEXT: MOV * T11.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 13: +; EG-NEXT: Fetch clause starting at 10: +; EG-NEXT: VTX_READ_128 T37.XYZW, T35.X, 16, #1 +; EG-NEXT: VTX_READ_128 T35.XYZW, T35.X, 0, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: MOV * T0.Y, T16.X, +; EG-NEXT: MOV * T35.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 16: +; EG-NEXT: AND_INT T0.W, T37.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 255(3.573311e-43), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T16.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T0.W, T37.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T16.X, PV.W, +; EG-NEXT: MOV T0.Y, T17.X, ; EG-NEXT: MOV * T0.W, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT * T13.W, T11.Y, literal.x, PV.W, +; EG-NEXT: BFE_UINT T1.W, T37.X, literal.x, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), -65536(nan) +; EG-NEXT: OR_INT * T1.W, PS, PV.W, +; EG-NEXT: MOV * T17.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T37.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT T13.Y, T11.X, literal.x, T0.W, -; EG-NEXT: AND_INT T13.Z, T11.Y, literal.y, -; EG-NEXT: BFE_UINT * T14.W, T11.W, literal.x, T0.W, -; EG-NEXT: 8(1.121039e-44), 255(3.573311e-43) -; EG-NEXT: AND_INT T13.X, T11.X, literal.x, -; EG-NEXT: BFE_UINT T14.Y, T11.Z, literal.y, T0.W, -; EG-NEXT: LSHR * T11.X, KC0[2].Y, literal.z, -; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44) -; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; EG-NEXT: AND_INT T14.Z, T11.W, literal.x, -; EG-NEXT: BFE_UINT * T15.W, T12.Y, literal.y, T0.W, -; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44) -; EG-NEXT: AND_INT T14.X, T11.Z, literal.x, -; EG-NEXT: BFE_UINT T15.Y, T12.X, literal.y, T0.W, -; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z, -; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T36.Y, PV.W, PS, +; EG-NEXT: MOV T17.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T12.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T37.Y, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T12.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T37.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T12.X, PV.W, +; EG-NEXT: MOV T0.Y, T13.X, +; EG-NEXT: BFE_UINT * T1.W, T37.Y, literal.x, T0.W, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T16.X, PV.W, literal.x, -; EG-NEXT: AND_INT T15.Z, T12.Y, literal.y, -; EG-NEXT: BFE_UINT T17.W, T12.W, literal.z, T0.W, -; EG-NEXT: AND_INT * T15.X, T12.X, literal.y, -; EG-NEXT: 2(2.802597e-45), 255(3.573311e-43) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T13.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T37.Y, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_UINT T17.Y, T12.Z, literal.x, T0.W, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, -; EG-NEXT: 8(1.121039e-44), 32(4.484155e-44) -; EG-NEXT: LSHR T12.X, PV.W, literal.x, -; EG-NEXT: AND_INT T17.Z, T12.W, literal.y, -; EG-NEXT: AND_INT * T17.X, T12.Z, literal.y, -; EG-NEXT: 2(2.802597e-45), 255(3.573311e-43) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T36.W, PV.W, PS, +; EG-NEXT: MOV T13.X, PV.W, +; EG-NEXT: MOV * T0.Y, T8.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T37.Z, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T37.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, +; EG-NEXT: BFE_UINT * T1.W, T37.Z, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T37.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T37.Y, PV.W, PS, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T37.W, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T37.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: BFE_UINT * T1.W, T37.W, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: ALU clause starting at 120: +; EG-NEXT: AND_INT * T2.W, T0.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T37.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T37.W, PV.W, PS, +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T0.Y, T32.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T35.X, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T32.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T35.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T32.X, PV.W, +; EG-NEXT: MOV T0.Y, T33.X, +; EG-NEXT: BFE_UINT * T1.W, T35.X, literal.x, T0.W, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T33.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T35.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T38.Y, PV.W, PS, +; EG-NEXT: MOV T33.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T28.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T35.Y, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T28.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T35.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T28.X, PV.W, +; EG-NEXT: MOV T0.Y, T29.X, +; EG-NEXT: BFE_UINT * T1.W, T35.Y, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T29.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T35.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T38.W, PV.W, PS, +; EG-NEXT: MOV T29.X, PV.W, +; EG-NEXT: MOV * T0.Y, T24.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T35.Z, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T24.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHL * T1.W, T35.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T24.X, PV.W, +; EG-NEXT: MOV T0.Y, T25.X, +; EG-NEXT: BFE_UINT * T1.W, T35.Z, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, PV.W, T1.W, +; EG-NEXT: MOV * T25.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T1.W, T35.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T35.Y, PV.W, PS, +; EG-NEXT: MOV T25.X, PV.Y, +; EG-NEXT: MOV * T0.Y, T20.X, +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T2.W, T35.W, literal.y, +; EG-NEXT: -65536(nan), 255(3.573311e-43) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV * T20.X, PV.W, +; EG-NEXT: ALU clause starting at 225: +; EG-NEXT: MOV T0.Y, T20.X, +; EG-NEXT: LSHL * T1.W, T35.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; EG-NEXT: OR_INT * T1.W, PV.W, PS, +; EG-NEXT: MOV T20.X, PV.W, +; EG-NEXT: MOV T0.Y, T21.X, +; EG-NEXT: BFE_UINT * T0.W, T35.W, literal.x, T0.W, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PV.W, T0.W, +; EG-NEXT: MOV * T21.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, -; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) -; EG-NEXT: LSHR * T18.X, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T39.X, PV.W, literal.x, +; EG-NEXT: LSHR * T40.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: LSHR T0.W, T35.W, literal.x, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 48(6.726233e-44) +; EG-NEXT: LSHR T41.X, PS, literal.x, +; EG-NEXT: AND_INT T0.Z, T0.Y, literal.y, +; EG-NEXT: AND_INT T0.W, PV.W, literal.z, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w, +; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; EG-NEXT: 16711680(2.341805e-38), 32(4.484155e-44) +; EG-NEXT: LSHR T42.X, PS, literal.x, +; EG-NEXT: OR_INT * T35.W, PV.Z, PV.W, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T21.X, PV.W, +; EG-NEXT: MOV * T36.X, T16.X, +; EG-NEXT: MOV * T36.Z, T12.X, +; EG-NEXT: MOV T37.X, T8.X, +; EG-NEXT: MOV T37.Z, T4.X, BS:VEC_120/SCL_212 +; EG-NEXT: MOV * T38.X, T32.X, +; EG-NEXT: MOV * T38.Z, T28.X, +; EG-NEXT: MOV T35.X, T24.X, +; EG-NEXT: MOV * T35.Z, T20.X, BS:VEC_120/SCL_212 ; ; CM-LABEL: global_zextload_v32i8_to_v32i16: ; CM: ; %bb.0: -; CM-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] -; CM-NEXT: TEX 1 @8 -; CM-NEXT: ALU 39, @13, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T17, T12.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T11, T18.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T14, T16.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T13, T15.X +; CM-NEXT: ALU 1, @14, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 1 @10 +; CM-NEXT: ALU 101, @16, KC0[], KC1[] +; CM-NEXT: ALU 101, @118, KC0[], KC1[] +; CM-NEXT: ALU 40, @220, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T36, T42.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T38, T41.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T37, T40.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T35, T39.X ; CM-NEXT: CF_END -; CM-NEXT: Fetch clause starting at 8: -; CM-NEXT: VTX_READ_128 T12.XYZW, T11.X, 0, #1 -; CM-NEXT: VTX_READ_128 T11.XYZW, T11.X, 16, #1 -; CM-NEXT: ALU clause starting at 12: -; CM-NEXT: MOV * T11.X, KC0[2].Z, -; CM-NEXT: ALU clause starting at 13: +; CM-NEXT: Fetch clause starting at 10: +; CM-NEXT: VTX_READ_128 T37.XYZW, T35.X, 16, #1 +; CM-NEXT: VTX_READ_128 T36.XYZW, T35.X, 0, #1 +; CM-NEXT: ALU clause starting at 14: +; CM-NEXT: MOV * T0.Y, T16.X, +; CM-NEXT: MOV * T35.X, KC0[2].Z, +; CM-NEXT: ALU clause starting at 16: +; CM-NEXT: AND_INT T0.Z, T37.X, literal.x, +; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y, +; CM-NEXT: 255(3.573311e-43), -65536(nan) +; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z, +; CM-NEXT: MOV * T16.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T0.W, T37.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T16.X, PV.W, +; CM-NEXT: MOV T0.Y, T17.X, ; CM-NEXT: MOV * T0.W, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_UINT * T13.W, T11.W, literal.x, PV.W, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T1.W, T37.X, literal.y, PV.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T17.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T37.X, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_UINT T13.Y, T11.Z, literal.x, T0.W, -; CM-NEXT: AND_INT T13.Z, T11.W, literal.y, -; CM-NEXT: BFE_UINT * T14.W, T11.Y, literal.x, T0.W, -; CM-NEXT: 8(1.121039e-44), 255(3.573311e-43) -; CM-NEXT: AND_INT T13.X, T11.Z, literal.x, -; CM-NEXT: BFE_UINT T14.Y, T11.X, literal.y, T0.W, -; CM-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z, -; CM-NEXT: 255(3.573311e-43), 8(1.121039e-44) -; CM-NEXT: 48(6.726233e-44), 0(0.000000e+00) -; CM-NEXT: LSHR T15.X, PV.W, literal.x, -; CM-NEXT: AND_INT T14.Z, T11.Y, literal.y, -; CM-NEXT: BFE_UINT * T11.W, T12.W, literal.z, T0.W, -; CM-NEXT: 2(2.802597e-45), 255(3.573311e-43) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T35.Y, PV.Z, PV.W, +; CM-NEXT: MOV T17.X, PV.Y, +; CM-NEXT: MOV * T0.Y, T12.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T37.Y, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T12.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T1.W, T37.Y, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: AND_INT T14.X, T11.X, literal.x, -; CM-NEXT: BFE_UINT T11.Y, T12.Z, literal.y, T0.W, -; CM-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z, -; CM-NEXT: 255(3.573311e-43), 8(1.121039e-44) -; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00) -; CM-NEXT: LSHR T16.X, PV.W, literal.x, -; CM-NEXT: AND_INT T11.Z, T12.W, literal.y, -; CM-NEXT: BFE_UINT * T17.W, T12.Y, literal.z, T0.W, -; CM-NEXT: 2(2.802597e-45), 255(3.573311e-43) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T12.X, PV.W, +; CM-NEXT: MOV * T0.Y, T13.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T1.W, T37.Y, literal.y, T0.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T13.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T37.Y, literal.x, ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: AND_INT T11.X, T12.Z, literal.x, -; CM-NEXT: BFE_UINT T17.Y, T12.X, literal.y, T0.W, -; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z, -; CM-NEXT: 255(3.573311e-43), 8(1.121039e-44) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T35.W, PV.Z, PV.W, +; CM-NEXT: MOV T13.X, PV.W, +; CM-NEXT: MOV * T0.Y, T8.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T37.Z, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T8.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T1.W, T37.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T8.X, PV.W, +; CM-NEXT: MOV * T0.Y, T9.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T1.W, T37.Z, literal.y, T0.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T9.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T37.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T37.Y, PV.Z, PV.W, +; CM-NEXT: MOV T9.X, PV.Y, +; CM-NEXT: MOV * T0.Y, T4.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T37.W, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T4.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T1.W, T37.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.W, +; CM-NEXT: MOV * T0.Y, T5.X, +; CM-NEXT: AND_INT * T0.Z, PV.Y, literal.x, +; CM-NEXT: -65536(nan), 0(0.000000e+00) +; CM-NEXT: ALU clause starting at 118: +; CM-NEXT: BFE_UINT * T1.W, T37.W, literal.x, T0.W, ; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; CM-NEXT: LSHR T18.X, PV.W, literal.x, -; CM-NEXT: AND_INT * T17.Z, T12.Y, literal.y, -; CM-NEXT: 2(2.802597e-45), 255(3.573311e-43) -; CM-NEXT: AND_INT * T17.X, T12.X, literal.x, -; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00) -; CM-NEXT: LSHR * T12.X, KC0[2].Y, literal.x, +; CM-NEXT: OR_INT * T1.W, T0.Z, PV.W, +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T37.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T37.W, PV.Z, PV.W, +; CM-NEXT: MOV T5.X, PV.W, +; CM-NEXT: MOV * T0.Y, T32.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T36.X, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T32.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T1.W, T36.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T32.X, PV.W, +; CM-NEXT: MOV * T0.Y, T33.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T1.W, T36.X, literal.y, T0.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T33.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T36.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T38.Y, PV.Z, PV.W, +; CM-NEXT: MOV T33.X, PV.Y, +; CM-NEXT: MOV * T0.Y, T28.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T36.Y, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T28.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T1.W, T36.Y, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T28.X, PV.W, +; CM-NEXT: MOV * T0.Y, T29.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T1.W, T36.Y, literal.y, T0.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T29.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T36.Y, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T38.W, PV.Z, PV.W, +; CM-NEXT: MOV T29.X, PV.W, +; CM-NEXT: MOV * T0.Y, T24.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T36.Z, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T24.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHL * T1.W, T36.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T24.X, PV.W, +; CM-NEXT: MOV * T0.Y, T25.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T1.W, T36.Z, literal.y, T0.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T25.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T1.W, T36.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T36.Y, PV.Z, PV.W, +; CM-NEXT: MOV T25.X, PV.Y, +; CM-NEXT: MOV * T0.Y, T20.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, T36.W, literal.y, +; CM-NEXT: -65536(nan), 255(3.573311e-43) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV * T20.X, PV.W, +; CM-NEXT: ALU clause starting at 220: +; CM-NEXT: MOV T0.Y, T20.X, +; CM-NEXT: LSHL * T1.W, T36.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T1.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38) +; CM-NEXT: OR_INT * T1.W, PV.Z, PV.W, +; CM-NEXT: MOV T20.X, PV.W, +; CM-NEXT: MOV * T0.Y, T21.X, +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: BFE_UINT * T0.W, T36.W, literal.y, T0.W, +; CM-NEXT: -65536(nan), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T21.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00) +; CM-NEXT: LSHR T39.X, PV.W, literal.x, +; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; CM-NEXT: 2(2.802597e-45), 48(6.726233e-44) +; CM-NEXT: LSHR T40.X, PV.W, literal.x, +; CM-NEXT: LSHR * T0.W, T36.W, literal.y, +; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; CM-NEXT: LSHR T41.X, KC0[2].Y, literal.x, +; CM-NEXT: AND_INT T0.Y, T0.Y, literal.y, +; CM-NEXT: AND_INT T0.Z, PV.W, literal.z, +; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.w, +; CM-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; CM-NEXT: 16711680(2.341805e-38), 16(2.242078e-44) +; CM-NEXT: LSHR T42.X, PV.W, literal.x, +; CM-NEXT: OR_INT * T36.W, PV.Y, PV.Z, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T21.X, PV.W, +; CM-NEXT: MOV T35.X, T16.X, +; CM-NEXT: MOV * T35.Z, T12.X, BS:VEC_120/SCL_212 +; CM-NEXT: MOV T37.X, T8.X, +; CM-NEXT: MOV * T37.Z, T4.X, BS:VEC_120/SCL_212 +; CM-NEXT: MOV T38.X, T32.X, +; CM-NEXT: MOV * T38.Z, T28.X, BS:VEC_120/SCL_212 +; CM-NEXT: MOV T36.X, T24.X, +; CM-NEXT: MOV * T36.Z, T20.X, BS:VEC_120/SCL_212 %load = load <32 x i8>, ptr addrspace(1) %in %ext = zext <32 x i8> %load to <32 x i16> store <32 x i16> %ext, ptr addrspace(1) %out @@ -11717,118 +12983,659 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i16(ptr addrspace(1) %out ; ; EG-LABEL: global_sextload_v32i8_to_v32i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 1 @8 -; EG-NEXT: ALU 39, @13, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T12.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T11.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T14.X, 0 -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T13.X, 1 +; EG-NEXT: ALU 1, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @10 +; EG-NEXT: ALU 104, @16, KC0[], KC1[] +; EG-NEXT: ALU 104, @121, KC0[], KC1[] +; EG-NEXT: ALU 95, @226, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T42.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T41.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T40.X, 0 +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T35.XYZW, T39.X, 1 ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 8: -; EG-NEXT: VTX_READ_128 T12.XYZW, T11.X, 16, #1 -; EG-NEXT: VTX_READ_128 T11.XYZW, T11.X, 0, #1 -; EG-NEXT: ALU clause starting at 12: -; EG-NEXT: MOV * T11.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 13: -; EG-NEXT: LSHR T13.X, KC0[2].Y, literal.x, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, -; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) -; EG-NEXT: LSHR T14.X, PV.W, literal.x, -; EG-NEXT: BFE_INT * T15.Z, T11.Y, 0.0, literal.y, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) -; EG-NEXT: BFE_INT T15.X, T11.X, 0.0, literal.x, -; EG-NEXT: LSHR T0.Y, T12.W, literal.x, -; EG-NEXT: BFE_INT T16.Z, T11.W, 0.0, literal.x, BS:VEC_120/SCL_212 -; EG-NEXT: LSHR T0.W, T12.Y, literal.x, -; EG-NEXT: LSHR * T1.W, T11.Y, literal.x, +; EG-NEXT: Fetch clause starting at 10: +; EG-NEXT: VTX_READ_128 T37.XYZW, T35.X, 16, #1 +; EG-NEXT: VTX_READ_128 T35.XYZW, T35.X, 0, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: MOV * T0.Y, T16.X, +; EG-NEXT: MOV * T35.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 16: +; EG-NEXT: BFE_INT * T0.W, T37.X, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T16.X, T11.Z, 0.0, literal.x, -; EG-NEXT: LSHR T1.Y, T11.W, literal.x, -; EG-NEXT: BFE_INT T17.Z, T12.Y, 0.0, literal.x, -; EG-NEXT: BFE_INT T15.W, PS, 0.0, literal.x, -; EG-NEXT: LSHR * T1.W, T11.X, literal.x, +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T16.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T37.X, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T17.X, T12.X, 0.0, literal.x, -; EG-NEXT: BFE_INT T15.Y, PS, 0.0, literal.x, -; EG-NEXT: BFE_INT T18.Z, T12.W, 0.0, literal.x, -; EG-NEXT: BFE_INT T16.W, PV.Y, 0.0, literal.x, -; EG-NEXT: LSHR * T1.W, T11.Z, literal.x, +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T16.X, PV.W, +; EG-NEXT: MOV T0.Y, T17.X, +; EG-NEXT: LSHR * T0.W, T37.X, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T17.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T37.X, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T36.Y, PV.W, PS, +; EG-NEXT: MOV T17.X, PV.Y, +; EG-NEXT: MOV T0.Y, T12.X, +; EG-NEXT: BFE_INT * T0.W, T37.Y, 0.0, literal.x, ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; EG-NEXT: BFE_INT T18.X, T12.Z, 0.0, literal.x, -; EG-NEXT: BFE_INT T16.Y, PS, 0.0, literal.x, -; EG-NEXT: LSHR T0.Z, T12.X, literal.x, -; EG-NEXT: BFE_INT T17.W, T0.W, 0.0, literal.x, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, -; EG-NEXT: 8(1.121039e-44), 32(4.484155e-44) -; EG-NEXT: LSHR T11.X, PS, literal.x, -; EG-NEXT: BFE_INT T17.Y, PV.Z, 0.0, literal.y, -; EG-NEXT: LSHR T0.Z, T12.Z, literal.y, -; EG-NEXT: BFE_INT T18.W, T0.Y, 0.0, literal.y, -; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) -; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T12.X, PS, literal.x, -; EG-NEXT: BFE_INT * T18.Y, PV.Z, 0.0, literal.y, -; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T12.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T37.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T12.X, PV.W, +; EG-NEXT: MOV T0.Y, T13.X, +; EG-NEXT: LSHR * T0.W, T37.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T13.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T37.Y, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T36.W, PV.W, PS, +; EG-NEXT: MOV T13.X, PV.W, +; EG-NEXT: MOV T0.Y, T8.X, +; EG-NEXT: BFE_INT * T0.W, T37.Z, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T8.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T37.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T8.X, PV.W, +; EG-NEXT: MOV T0.Y, T9.X, +; EG-NEXT: LSHR * T0.W, T37.Z, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T9.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T37.Z, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: ALU clause starting at 121: +; EG-NEXT: OR_INT * T37.Y, T1.W, T0.W, +; EG-NEXT: MOV T9.X, PV.Y, +; EG-NEXT: MOV T0.Y, T4.X, +; EG-NEXT: BFE_INT * T0.W, T37.W, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T37.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T4.X, PV.W, +; EG-NEXT: MOV T0.Y, T5.X, +; EG-NEXT: LSHR * T0.W, T37.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T37.W, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T37.W, PV.W, PS, +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV T0.Y, T32.X, +; EG-NEXT: BFE_INT * T0.W, T35.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T32.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T35.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T32.X, PV.W, +; EG-NEXT: MOV T0.Y, T33.X, +; EG-NEXT: LSHR * T0.W, T35.X, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T33.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T35.X, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T38.Y, PV.W, PS, +; EG-NEXT: MOV T33.X, PV.Y, +; EG-NEXT: MOV T0.Y, T28.X, +; EG-NEXT: BFE_INT * T0.W, T35.Y, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T28.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T35.Y, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T28.X, PV.W, +; EG-NEXT: MOV T0.Y, T29.X, +; EG-NEXT: LSHR * T0.W, T35.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T29.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T35.Y, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: ALU clause starting at 226: +; EG-NEXT: AND_INT T1.W, T0.Y, literal.x, +; EG-NEXT: LSHL * T0.W, T0.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T38.W, PV.W, PS, +; EG-NEXT: MOV T29.X, PV.W, +; EG-NEXT: MOV T0.Y, T24.X, +; EG-NEXT: BFE_INT * T0.W, T35.Z, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T24.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T35.Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T24.X, PV.W, +; EG-NEXT: MOV T0.Y, T25.X, +; EG-NEXT: LSHR * T0.W, T35.Z, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T25.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ASHR * T0.W, T35.Z, literal.x, +; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: LSHL * T0.W, PV.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: OR_INT * T35.Y, PV.W, PS, +; EG-NEXT: MOV T25.X, PV.Y, +; EG-NEXT: MOV T0.Y, T20.X, +; EG-NEXT: BFE_INT * T0.W, T35.W, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, +; EG-NEXT: -65536(nan), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV * T20.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T35.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T20.X, PV.W, +; EG-NEXT: MOV T0.Y, T21.X, +; EG-NEXT: LSHR * T0.W, T35.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y, +; EG-NEXT: 8(1.121039e-44), -65536(nan) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T21.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T39.X, PV.W, literal.x, +; EG-NEXT: LSHR * T40.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: ASHR T0.W, T35.W, literal.x, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y, +; EG-NEXT: 24(3.363116e-44), 48(6.726233e-44) +; EG-NEXT: LSHR T41.X, PS, literal.x, +; EG-NEXT: AND_INT T0.Z, T0.Y, literal.y, +; EG-NEXT: LSHL T0.W, PV.W, literal.z, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w, +; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; EG-NEXT: 16(2.242078e-44), 32(4.484155e-44) +; EG-NEXT: LSHR T42.X, PS, literal.x, +; EG-NEXT: OR_INT * T35.W, PV.Z, PV.W, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T21.X, PV.W, +; EG-NEXT: MOV * T36.X, T16.X, +; EG-NEXT: MOV * T36.Z, T12.X, +; EG-NEXT: MOV T37.X, T8.X, +; EG-NEXT: MOV T37.Z, T4.X, BS:VEC_120/SCL_212 +; EG-NEXT: MOV * T38.X, T32.X, +; EG-NEXT: MOV * T38.Z, T28.X, +; EG-NEXT: MOV T35.X, T24.X, +; EG-NEXT: MOV * T35.Z, T20.X, BS:VEC_120/SCL_212 ; ; CM-LABEL: global_sextload_v32i8_to_v32i16: ; CM: ; %bb.0: -; CM-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] -; CM-NEXT: TEX 1 @8 -; CM-NEXT: ALU 40, @13, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T17, T11.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T12, T18.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T16, T14.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T15, T13.X +; CM-NEXT: ALU 1, @14, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 1 @10 +; CM-NEXT: ALU 104, @16, KC0[], KC1[] +; CM-NEXT: ALU 104, @121, KC0[], KC1[] +; CM-NEXT: ALU 95, @226, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T35, T42.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T38, T41.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T37, T40.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T36, T39.X ; CM-NEXT: CF_END -; CM-NEXT: Fetch clause starting at 8: -; CM-NEXT: VTX_READ_128 T12.XYZW, T11.X, 16, #1 -; CM-NEXT: VTX_READ_128 T11.XYZW, T11.X, 0, #1 -; CM-NEXT: ALU clause starting at 12: -; CM-NEXT: MOV * T11.X, KC0[2].Z, -; CM-NEXT: ALU clause starting at 13: +; CM-NEXT: Fetch clause starting at 10: +; CM-NEXT: VTX_READ_128 T37.XYZW, T35.X, 16, #1 +; CM-NEXT: VTX_READ_128 T35.XYZW, T35.X, 0, #1 +; CM-NEXT: ALU clause starting at 14: +; CM-NEXT: MOV * T0.Y, T16.X, +; CM-NEXT: MOV * T35.X, KC0[2].Z, +; CM-NEXT: ALU clause starting at 16: +; CM-NEXT: BFE_INT * T0.W, T37.X, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.W, literal.x, +; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y, +; CM-NEXT: 65535(9.183409e-41), -65536(nan) +; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z, +; CM-NEXT: MOV * T16.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T37.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T16.X, PV.W, +; CM-NEXT: MOV T0.Y, T17.X, +; CM-NEXT: LSHR * T0.W, T37.X, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T17.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T37.X, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T36.Y, PV.Z, PV.W, +; CM-NEXT: MOV T17.X, PV.Y, +; CM-NEXT: MOV T0.Y, T12.X, +; CM-NEXT: BFE_INT * T0.W, T37.Y, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T12.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T37.Y, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T12.X, PV.W, +; CM-NEXT: MOV T0.Y, T13.X, +; CM-NEXT: LSHR * T0.W, T37.Y, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T13.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T37.Y, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T36.W, PV.Z, PV.W, +; CM-NEXT: MOV T13.X, PV.W, +; CM-NEXT: MOV T0.Y, T8.X, +; CM-NEXT: BFE_INT * T0.W, T37.Z, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T8.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T37.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T8.X, PV.W, +; CM-NEXT: MOV T0.Y, T9.X, +; CM-NEXT: LSHR * T0.W, T37.Z, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T9.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T37.Z, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: ALU clause starting at 121: +; CM-NEXT: OR_INT * T37.Y, T0.Z, T0.W, +; CM-NEXT: MOV T9.X, PV.Y, +; CM-NEXT: MOV T0.Y, T4.X, +; CM-NEXT: BFE_INT * T0.W, T37.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T4.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T37.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T4.X, PV.W, +; CM-NEXT: MOV T0.Y, T5.X, +; CM-NEXT: LSHR * T0.W, T37.W, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T5.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T37.W, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T37.W, PV.Z, PV.W, +; CM-NEXT: MOV T5.X, PV.W, +; CM-NEXT: MOV T0.Y, T32.X, +; CM-NEXT: BFE_INT * T0.W, T35.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T32.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T35.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T32.X, PV.W, +; CM-NEXT: MOV T0.Y, T33.X, +; CM-NEXT: LSHR * T0.W, T35.X, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T33.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T35.X, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T38.Y, PV.Z, PV.W, +; CM-NEXT: MOV T33.X, PV.Y, +; CM-NEXT: MOV T0.Y, T28.X, +; CM-NEXT: BFE_INT * T0.W, T35.Y, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T28.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T35.Y, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T28.X, PV.W, +; CM-NEXT: MOV T0.Y, T29.X, +; CM-NEXT: LSHR * T0.W, T35.Y, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T29.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T35.Y, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: ALU clause starting at 226: +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, T0.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T38.W, PV.Z, PV.W, +; CM-NEXT: MOV T29.X, PV.W, +; CM-NEXT: MOV T0.Y, T24.X, +; CM-NEXT: BFE_INT * T0.W, T35.Z, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T24.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T35.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T24.X, PV.W, +; CM-NEXT: MOV T0.Y, T25.X, +; CM-NEXT: LSHR * T0.W, T35.Z, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T25.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: ASHR * T0.W, T35.Z, literal.x, +; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T35.Y, PV.Z, PV.W, +; CM-NEXT: MOV T25.X, PV.Y, +; CM-NEXT: MOV T0.Y, T20.X, +; CM-NEXT: BFE_INT * T0.W, T35.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, PV.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T20.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, +; CM-NEXT: LSHR * T0.W, T35.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: LSHL * T0.W, PV.W, literal.y, +; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV T20.X, PV.W, +; CM-NEXT: MOV T0.Y, T21.X, +; CM-NEXT: LSHR * T0.W, T35.W, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x, +; CM-NEXT: AND_INT * T0.W, PV.W, literal.y, +; CM-NEXT: -65536(nan), 65535(9.183409e-41) +; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W, +; CM-NEXT: MOV * T21.X, PV.W, +; CM-NEXT: MOV T0.Y, PV.X, ; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, -; CM-NEXT: 48(6.726233e-44), 0(0.000000e+00) -; CM-NEXT: LSHR T13.X, PV.W, literal.x, -; CM-NEXT: LSHR T0.Y, T11.Y, literal.y, -; CM-NEXT: LSHR T0.Z, T11.Z, literal.y, -; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z, -; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44) ; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00) -; CM-NEXT: LSHR T14.X, PV.W, literal.x, -; CM-NEXT: LSHR T1.Y, T11.W, literal.y, -; CM-NEXT: BFE_INT T15.Z, T12.W, 0.0, literal.y, BS:VEC_120/SCL_212 -; CM-NEXT: LSHR * T0.W, T12.X, literal.y, -; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44) -; CM-NEXT: BFE_INT T15.X, T12.Z, 0.0, literal.x, -; CM-NEXT: LSHR T2.Y, T12.Y, literal.x, -; CM-NEXT: BFE_INT T16.Z, T12.Y, 0.0, literal.x, -; CM-NEXT: LSHR * T1.W, T12.W, literal.x, -; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_INT T16.X, T12.X, 0.0, literal.x, -; CM-NEXT: LSHR T3.Y, T12.Z, literal.x, -; CM-NEXT: BFE_INT T12.Z, T11.W, 0.0, literal.x, -; CM-NEXT: BFE_INT * T15.W, PV.W, 0.0, literal.x, -; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_INT T12.X, T11.Z, 0.0, literal.x, -; CM-NEXT: BFE_INT T15.Y, PV.Y, 0.0, literal.x, -; CM-NEXT: BFE_INT T17.Z, T11.Y, 0.0, literal.x, -; CM-NEXT: BFE_INT * T16.W, T2.Y, 0.0, literal.x, BS:VEC_120/SCL_212 -; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: BFE_INT T17.X, T11.X, 0.0, literal.x, -; CM-NEXT: BFE_INT T16.Y, T0.W, 0.0, literal.x, -; CM-NEXT: ADD_INT T1.Z, KC0[2].Y, literal.y, -; CM-NEXT: BFE_INT * T12.W, T1.Y, 0.0, literal.x, -; CM-NEXT: 8(1.121039e-44), 16(2.242078e-44) -; CM-NEXT: LSHR T18.X, PV.Z, literal.x, -; CM-NEXT: BFE_INT T12.Y, T0.Z, 0.0, literal.y, -; CM-NEXT: LSHR T0.Z, T11.X, literal.y, -; CM-NEXT: BFE_INT * T17.W, T0.Y, 0.0, literal.y, -; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44) -; CM-NEXT: LSHR T11.X, KC0[2].Y, literal.x, -; CM-NEXT: BFE_INT * T17.Y, PV.Z, 0.0, literal.y, -; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44) +; CM-NEXT: LSHR T39.X, PV.W, literal.x, +; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; CM-NEXT: 2(2.802597e-45), 48(6.726233e-44) +; CM-NEXT: LSHR T40.X, PV.W, literal.x, +; CM-NEXT: ASHR * T0.W, T35.W, literal.y, +; CM-NEXT: 2(2.802597e-45), 24(3.363116e-44) +; CM-NEXT: LSHR T41.X, KC0[2].Y, literal.x, +; CM-NEXT: AND_INT T0.Y, T0.Y, literal.y, +; CM-NEXT: LSHL T0.Z, PV.W, literal.z, +; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z, +; CM-NEXT: 2(2.802597e-45), 65535(9.183409e-41) +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR T42.X, PV.W, literal.x, +; CM-NEXT: OR_INT * T35.W, PV.Y, PV.Z, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T21.X, PV.W, +; CM-NEXT: MOV T36.X, T16.X, +; CM-NEXT: MOV * T36.Z, T12.X, BS:VEC_120/SCL_212 +; CM-NEXT: MOV T37.X, T8.X, +; CM-NEXT: MOV * T37.Z, T4.X, BS:VEC_120/SCL_212 +; CM-NEXT: MOV T38.X, T32.X, +; CM-NEXT: MOV * T38.Z, T28.X, BS:VEC_120/SCL_212 +; CM-NEXT: MOV T35.X, T24.X, +; CM-NEXT: MOV * T35.Z, T20.X, BS:VEC_120/SCL_212 %load = load <32 x i8>, ptr addrspace(1) %in %ext = sext <32 x i8> %load to <32 x i16> store <32 x i16> %ext, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i16.ll b/llvm/test/CodeGen/AMDGPU/load-local-i16.ll index 8dcecfe..a209de7 100644 --- a/llvm/test/CodeGen/AMDGPU/load-local-i16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-local-i16.ll @@ -151,19 +151,27 @@ define amdgpu_kernel void @local_load_v3i16(ptr addrspace(3) %out, ptr addrspace ; ; EG-LABEL: local_load_v3i16: ; EG: ; %bb.0: ; %entry -; EG-NEXT: ALU 11, @2, KC0[CB0:0-32], KC1[] -; EG-NEXT: ADD_INT * T0.W, KC0[2].Z, literal.x, -; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00) -; EG-NEXT: LDS_USHORT_READ_RET * OQAP, T0.W -; EG-NEXT: MOV T0.X, OQAP, +; EG-NEXT: ALU 19, @2, KC0[CB0:0-32], KC1[] ; EG-NEXT: MOV * T0.W, KC0[2].Z, ; EG-NEXT: LDS_USHORT_READ_RET * OQAP, T0.W ; EG-NEXT: MOV T0.Y, OQAP, -; EG-NEXT: MOV * T0.W, KC0[2].Y, -; EG-NEXT: LDS_WRITE * T0.W, T0.Y, +; EG-NEXT: ADD_INT * T0.W, KC0[2].Z, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: LDS_USHORT_READ_RET * OQAP, T0.W +; EG-NEXT: MOV * T0.Z, OQAP, +; EG-NEXT: LSHL T0.Z, PV.Z, literal.x, +; EG-NEXT: AND_INT T0.W, T0.Y, literal.y, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Z, literal.z, +; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00) +; EG-NEXT: LDS_USHORT_READ_RET * OQAP, T1.W +; EG-NEXT: MOV T0.Y, OQAP, +; EG-NEXT: OR_INT T0.W, T0.Z, T0.W, +; EG-NEXT: MOV * T1.W, KC0[2].Y, +; EG-NEXT: LDS_WRITE * T1.W, T0.W, ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, ; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00) -; EG-NEXT: LDS_SHORT_WRITE * T0.W, T0.X, +; EG-NEXT: LDS_SHORT_WRITE * T0.W, T0.Y, ; EG-NEXT: RETURN entry: %ld = load <3 x i16>, ptr addrspace(3) %in diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll index 721f974..311527d 100644 --- a/llvm/test/CodeGen/AMDGPU/min.ll +++ b/llvm/test/CodeGen/AMDGPU/min.ll @@ -991,30 +991,81 @@ define amdgpu_kernel void @s_test_imin_sle_v2i16(ptr addrspace(1) %out, <2 x i16 define amdgpu_kernel void @s_test_imin_sle_v4i16(ptr addrspace(1) %out, <4 x i16> %a, <4 x i16> %b) #0 { ; EG-LABEL: s_test_imin_sle_v4i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @14, KC0[], KC1[] -; EG-NEXT: TEX 3 @6 -; EG-NEXT: ALU 9, @15, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: ALU 1, @28, KC0[], KC1[] +; EG-NEXT: TEX 1 @12 +; EG-NEXT: ALU 9, @30, KC0[], KC1[] +; EG-NEXT: TEX 1 @16 +; EG-NEXT: ALU 10, @40, KC0[], KC1[] +; EG-NEXT: TEX 1 @20 +; EG-NEXT: ALU 10, @51, KC0[], KC1[] +; EG-NEXT: TEX 1 @24 +; EG-NEXT: ALU 11, @62, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XY, T5.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD -; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_16 T1.X, T0.X, 46, #3 -; EG-NEXT: VTX_READ_16 T2.X, T0.X, 52, #3 -; EG-NEXT: VTX_READ_16 T3.X, T0.X, 44, #3 -; EG-NEXT: VTX_READ_16 T0.X, T0.X, 54, #3 -; EG-NEXT: ALU clause starting at 14: -; EG-NEXT: MOV * T0.X, 0.0, -; EG-NEXT: ALU clause starting at 15: -; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x, -; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: Fetch clause starting at 12: +; EG-NEXT: VTX_READ_16 T6.X, T5.X, 50, #3 +; EG-NEXT: VTX_READ_16 T7.X, T5.X, 58, #3 +; EG-NEXT: Fetch clause starting at 16: +; EG-NEXT: VTX_READ_16 T6.X, T5.X, 48, #3 +; EG-NEXT: VTX_READ_16 T7.X, T5.X, 56, #3 +; EG-NEXT: Fetch clause starting at 20: +; EG-NEXT: VTX_READ_16 T6.X, T5.X, 46, #3 +; EG-NEXT: VTX_READ_16 T7.X, T5.X, 54, #3 +; EG-NEXT: Fetch clause starting at 24: +; EG-NEXT: VTX_READ_16 T6.X, T5.X, 44, #3 +; EG-NEXT: VTX_READ_16 T5.X, T5.X, 52, #3 +; EG-NEXT: ALU clause starting at 28: +; EG-NEXT: MOV * T0.Y, T3.X, +; EG-NEXT: MOV * T5.X, 0.0, +; EG-NEXT: ALU clause starting at 30: +; EG-NEXT: BFE_INT T0.Z, T6.X, 0.0, literal.x, +; EG-NEXT: BFE_INT * T0.W, T7.X, 0.0, literal.x, BS:VEC_120/SCL_212 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: MIN_INT T0.Y, PV.Z, PV.W, -; EG-NEXT: BFE_INT T0.Z, T3.X, 0.0, literal.x, -; EG-NEXT: BFE_INT * T0.W, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: MIN_INT * T0.W, PV.Z, PV.W, +; EG-NEXT: LSHL T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T3.X, PV.W, +; EG-NEXT: MOV * T0.Y, PV.X, +; EG-NEXT: ALU clause starting at 40: +; EG-NEXT: BFE_INT T0.Z, T6.X, 0.0, literal.x, +; EG-NEXT: BFE_INT * T0.W, T7.X, 0.0, literal.x, BS:VEC_120/SCL_212 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: MIN_INT T0.X, PV.Z, PV.W, -; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, -; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MIN_INT T0.W, PV.Z, PV.W, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T3.X, PV.W, +; EG-NEXT: MOV * T0.Y, T2.X, +; EG-NEXT: ALU clause starting at 51: +; EG-NEXT: BFE_INT T0.Z, T6.X, 0.0, literal.x, +; EG-NEXT: BFE_INT * T0.W, T7.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: MIN_INT T0.W, PV.Z, PV.W, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T2.X, PV.W, +; EG-NEXT: MOV * T0.Y, PV.X, +; EG-NEXT: ALU clause starting at 62: +; EG-NEXT: BFE_INT T0.Z, T6.X, 0.0, literal.x, +; EG-NEXT: BFE_INT * T0.W, T5.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: MIN_INT * T0.W, PV.Z, PV.W, +; EG-NEXT: LSHR T5.X, KC0[2].Y, literal.x, +; EG-NEXT: AND_INT T1.W, T0.Y, literal.y, +; EG-NEXT: AND_INT * T0.W, PV.W, literal.z, +; EG-NEXT: 2(2.802597e-45), -65536(nan) +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T6.X, PV.W, PS, +; EG-NEXT: MOV T2.X, PV.X, +; EG-NEXT: MOV * T6.Y, T3.X, ; ; CI-LABEL: s_test_imin_sle_v4i16: ; CI: ; %bb.0: @@ -2154,40 +2205,49 @@ define amdgpu_kernel void @v_test_umin_ule_v3i32(ptr addrspace(1) %out, ptr addr define amdgpu_kernel void @v_test_umin_ule_v3i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 { ; EG-LABEL: v_test_umin_ule_v3i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 3, @14, KC0[CB0:0-32], KC1[] -; EG-NEXT: TEX 3 @6 -; EG-NEXT: ALU 17, @18, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 0 -; EG-NEXT: MEM_RAT MSKOR T4.XW, T0.X +; EG-NEXT: ALU 3, @20, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @8 +; EG-NEXT: ALU 11, @24, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 3 @12 +; EG-NEXT: ALU 8, @36, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T8.X, 0 +; EG-NEXT: MEM_RAT MSKOR T7.XW, T0.X ; EG-NEXT: CF_END -; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_16 T2.X, T1.X, 0, #1 -; EG-NEXT: VTX_READ_16 T3.X, T0.X, 0, #1 -; EG-NEXT: VTX_READ_16 T1.X, T1.X, 4, #1 -; EG-NEXT: VTX_READ_16 T0.X, T0.X, 4, #1 -; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_16 T7.X, T6.X, 4, #1 +; EG-NEXT: VTX_READ_16 T8.X, T0.X, 4, #1 +; EG-NEXT: Fetch clause starting at 12: +; EG-NEXT: VTX_READ_16 T8.X, T6.X, 0, #1 +; EG-NEXT: VTX_READ_16 T9.X, T0.X, 0, #1 +; EG-NEXT: VTX_READ_16 T6.X, T6.X, 2, #1 +; EG-NEXT: VTX_READ_16 T0.X, T0.X, 2, #1 +; EG-NEXT: ALU clause starting at 20: ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) ; EG-NEXT: ADD_INT T0.X, KC0[2].Z, PV.W, -; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.W, -; EG-NEXT: ALU clause starting at 18: +; EG-NEXT: ADD_INT * T6.X, KC0[2].W, PV.W, +; EG-NEXT: ALU clause starting at 24: ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W, ; EG-NEXT: ADD_INT * T1.W, PV.W, literal.x, ; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00) ; EG-NEXT: AND_INT * T2.W, PV.W, literal.x, ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) ; EG-NEXT: LSHL T2.W, PV.W, literal.x, -; EG-NEXT: MIN_UINT * T3.W, T0.X, T1.X, +; EG-NEXT: MIN_UINT * T3.W, T8.X, T7.X, ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) -; EG-NEXT: LSHL T4.X, PS, PV.W, -; EG-NEXT: LSHL * T4.W, literal.x, PV.W, +; EG-NEXT: LSHL T7.X, PS, PV.W, +; EG-NEXT: LSHL * T7.W, literal.x, PV.W, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: MOV T4.Y, 0.0, -; EG-NEXT: MOV * T4.Z, 0.0, +; EG-NEXT: MOV * T7.Y, 0.0, +; EG-NEXT: ALU clause starting at 36: +; EG-NEXT: MOV T7.Z, 0.0, +; EG-NEXT: MIN_UINT * T2.W, T0.X, T6.X, ; EG-NEXT: LSHR T0.X, T1.W, literal.x, -; EG-NEXT: MIN_UINT * T1.X, T3.X, T2.X, -; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; EG-NEXT: LSHR * T2.X, T0.W, literal.x, +; EG-NEXT: LSHL T1.W, PV.W, literal.y, +; EG-NEXT: MIN_UINT * T2.W, T9.X, T8.X, +; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44) +; EG-NEXT: OR_INT T6.X, PV.W, PS, +; EG-NEXT: LSHR * T8.X, T0.W, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; ; CI-LABEL: v_test_umin_ule_v3i16: @@ -3483,46 +3543,142 @@ define amdgpu_kernel void @s_test_umin_ult_v8i32(ptr addrspace(1) %out, <8 x i32 define amdgpu_kernel void @s_test_umin_ult_v8i16(ptr addrspace(1) %out, <8 x i16> %a, <8 x i16> %b) #0 { ; EG-LABEL: s_test_umin_ult_v8i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @24, KC0[], KC1[] -; EG-NEXT: TEX 2 @8 -; EG-NEXT: ALU 2, @25, KC0[], KC1[] -; EG-NEXT: TEX 4 @14 -; EG-NEXT: ALU 14, @28, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 +; EG-NEXT: ALU 1, @52, KC0[], KC1[] +; EG-NEXT: TEX 1 @20 +; EG-NEXT: ALU 9, @54, KC0[], KC1[] +; EG-NEXT: TEX 1 @24 +; EG-NEXT: ALU 8, @64, KC0[], KC1[] +; EG-NEXT: TEX 1 @28 +; EG-NEXT: ALU 10, @73, KC0[], KC1[] +; EG-NEXT: TEX 1 @32 +; EG-NEXT: ALU 8, @84, KC0[], KC1[] +; EG-NEXT: TEX 1 @36 +; EG-NEXT: ALU 10, @93, KC0[], KC1[] +; EG-NEXT: TEX 1 @40 +; EG-NEXT: ALU 8, @104, KC0[], KC1[] +; EG-NEXT: TEX 1 @44 +; EG-NEXT: ALU 10, @113, KC0[], KC1[] +; EG-NEXT: TEX 1 @48 +; EG-NEXT: ALU 10, @124, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T8.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD -; EG-NEXT: Fetch clause starting at 8: -; EG-NEXT: VTX_READ_16 T1.X, T0.X, 62, #3 -; EG-NEXT: VTX_READ_16 T2.X, T0.X, 60, #3 -; EG-NEXT: VTX_READ_16 T3.X, T0.X, 78, #3 -; EG-NEXT: Fetch clause starting at 14: -; EG-NEXT: VTX_READ_16 T1.X, T0.X, 68, #3 -; EG-NEXT: VTX_READ_16 T3.X, T0.X, 52, #3 -; EG-NEXT: VTX_READ_16 T4.X, T0.X, 70, #3 -; EG-NEXT: VTX_READ_16 T5.X, T0.X, 54, #3 -; EG-NEXT: VTX_READ_16 T0.X, T0.X, 76, #3 -; EG-NEXT: ALU clause starting at 24: -; EG-NEXT: MOV * T0.X, 0.0, -; EG-NEXT: ALU clause starting at 25: -; EG-NEXT: AND_INT T0.W, T1.X, literal.x, -; EG-NEXT: AND_INT * T1.W, T3.X, literal.x, +; EG-NEXT: Fetch clause starting at 20: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 66, #3 +; EG-NEXT: VTX_READ_16 T9.X, T7.X, 82, #3 +; EG-NEXT: Fetch clause starting at 24: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 64, #3 +; EG-NEXT: VTX_READ_16 T9.X, T7.X, 80, #3 +; EG-NEXT: Fetch clause starting at 28: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 62, #3 +; EG-NEXT: VTX_READ_16 T9.X, T7.X, 78, #3 +; EG-NEXT: Fetch clause starting at 32: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 60, #3 +; EG-NEXT: VTX_READ_16 T9.X, T7.X, 76, #3 +; EG-NEXT: Fetch clause starting at 36: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 58, #3 +; EG-NEXT: VTX_READ_16 T9.X, T7.X, 74, #3 +; EG-NEXT: Fetch clause starting at 40: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 56, #3 +; EG-NEXT: VTX_READ_16 T9.X, T7.X, 72, #3 +; EG-NEXT: Fetch clause starting at 44: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 54, #3 +; EG-NEXT: VTX_READ_16 T9.X, T7.X, 70, #3 +; EG-NEXT: Fetch clause starting at 48: +; EG-NEXT: VTX_READ_16 T8.X, T7.X, 52, #3 +; EG-NEXT: VTX_READ_16 T7.X, T7.X, 68, #3 +; EG-NEXT: ALU clause starting at 52: +; EG-NEXT: MOV * T0.Y, T3.X, +; EG-NEXT: MOV * T7.X, 0.0, +; EG-NEXT: ALU clause starting at 54: +; EG-NEXT: AND_INT T0.W, T8.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T9.X, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: ALU clause starting at 28: -; EG-NEXT: AND_INT T0.Z, T2.X, literal.x, -; EG-NEXT: AND_INT T2.W, T0.X, literal.x, BS:VEC_120/SCL_212 -; EG-NEXT: MIN_UINT * T0.W, T0.W, T1.W, +; EG-NEXT: MIN_UINT * T0.W, PV.W, PS, +; EG-NEXT: LSHL T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T3.X, PV.W, +; EG-NEXT: MOV * T0.Y, PV.X, +; EG-NEXT: ALU clause starting at 64: +; EG-NEXT: AND_INT T0.W, T8.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T9.X, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: MIN_UINT T0.Z, PV.Z, PV.W, -; EG-NEXT: AND_INT T1.W, T5.X, literal.x, -; EG-NEXT: AND_INT * T2.W, T4.X, literal.x, +; EG-NEXT: AND_INT T2.W, T0.Y, literal.x, +; EG-NEXT: MIN_UINT * T0.W, PV.W, PS, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T3.X, PV.W, +; EG-NEXT: MOV * T0.Y, T2.X, +; EG-NEXT: ALU clause starting at 73: +; EG-NEXT: AND_INT T0.W, T8.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T9.X, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: MIN_UINT T0.Y, PV.W, PS, -; EG-NEXT: AND_INT T1.W, T3.X, literal.x, -; EG-NEXT: AND_INT * T2.W, T1.X, literal.x, +; EG-NEXT: MIN_UINT T0.W, PV.W, PS, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: MIN_UINT T0.X, PV.W, PS, -; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, -; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T2.X, PV.W, +; EG-NEXT: MOV * T0.Y, PV.X, +; EG-NEXT: ALU clause starting at 84: +; EG-NEXT: AND_INT T0.W, T8.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T9.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, T0.Y, literal.x, +; EG-NEXT: MIN_UINT * T0.W, PV.W, PS, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T7.Z, PV.W, PS, +; EG-NEXT: MOV T2.X, PV.Z, +; EG-NEXT: MOV * T0.Y, T5.X, +; EG-NEXT: ALU clause starting at 93: +; EG-NEXT: AND_INT T0.W, T8.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T9.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: MIN_UINT T0.W, PV.W, PS, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T5.X, PV.W, +; EG-NEXT: MOV * T0.Y, PV.X, +; EG-NEXT: ALU clause starting at 104: +; EG-NEXT: AND_INT T0.W, T8.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T9.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, T0.Y, literal.x, +; EG-NEXT: MIN_UINT * T0.W, PV.W, PS, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, PV.W, PS, +; EG-NEXT: MOV T5.X, PV.W, +; EG-NEXT: MOV * T0.Y, T4.X, +; EG-NEXT: ALU clause starting at 113: +; EG-NEXT: AND_INT T0.W, T8.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T9.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: MIN_UINT T0.W, PV.W, PS, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T4.X, PV.W, +; EG-NEXT: MOV * T0.Y, PV.X, +; EG-NEXT: ALU clause starting at 124: +; EG-NEXT: AND_INT T0.W, T8.X, literal.x, +; EG-NEXT: AND_INT * T1.W, T7.X, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHR T8.X, KC0[2].Y, literal.x, +; EG-NEXT: AND_INT T2.W, T0.Y, literal.y, +; EG-NEXT: MIN_UINT * T0.W, PV.W, PS, +; EG-NEXT: 2(2.802597e-45), -65536(nan) +; EG-NEXT: OR_INT * T7.X, PV.W, PS, +; EG-NEXT: MOV T4.X, PV.X, +; EG-NEXT: MOV * T7.W, T3.X, +; EG-NEXT: MOV * T7.Y, T5.X, ; ; CI-LABEL: s_test_umin_ult_v8i16: ; CI: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/shl.ll b/llvm/test/CodeGen/AMDGPU/shl.ll index 7aa7342..28330bf 100644 --- a/llvm/test/CodeGen/AMDGPU/shl.ll +++ b/llvm/test/CodeGen/AMDGPU/shl.ll @@ -681,30 +681,63 @@ define amdgpu_kernel void @shl_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in ; ; EG-LABEL: shl_v4i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 3, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T8.X, 1 +; EG-NEXT: ALU 42, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T0.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_128 T8.XYZW, T0.X, 0, #1 +; EG-NEXT: VTX_READ_128 T10.XYZW, T0.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: LSHL * T0.W, T0.X, literal.x, +; EG-NEXT: MOV T0.Y, T6.X, +; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, -; EG-NEXT: ALU clause starting at 11: -; EG-NEXT: LSHR T1.W, T8.Z, literal.x, -; EG-NEXT: LSHR * T2.W, T8.X, literal.x, +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: AND_INT * T1.W, T10.Z, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T1.W, T10.X, PV.W, +; EG-NEXT: AND_INT T1.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T2.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T1.W, PS, PV.W, +; EG-NEXT: MOV * T6.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: LSHR T1.W, T10.Z, literal.x, +; EG-NEXT: LSHR * T2.W, T10.X, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: LSHL T0.Y, PS, PV.W, -; EG-NEXT: AND_INT T1.W, T8.Z, literal.x, -; EG-NEXT: AND_INT * T2.W, T8.X, literal.x, +; EG-NEXT: LSHL T1.W, PS, PV.W, +; EG-NEXT: AND_INT * T2.W, PV.X, literal.x, ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) -; EG-NEXT: LSHL T0.X, PS, PV.W, +; EG-NEXT: LSHL * T1.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, +; EG-NEXT: MOV T6.X, PV.W, +; EG-NEXT: MOV * T0.X, T7.X, +; EG-NEXT: AND_INT * T1.W, T10.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL T1.W, T10.Y, PV.W, +; EG-NEXT: AND_INT * T2.W, T0.X, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: AND_INT * T1.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, +; EG-NEXT: MOV * T7.X, PV.W, +; EG-NEXT: MOV T0.X, PV.X, +; EG-NEXT: LSHR T1.W, T10.W, literal.x, +; EG-NEXT: LSHR * T2.W, T10.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: LSHL * T1.W, PS, PV.W, +; EG-NEXT: AND_INT T0.Z, T0.X, literal.x, +; EG-NEXT: LSHL T1.W, PV.W, literal.y, ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W, -; EG-NEXT: LSHR * T8.X, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) +; EG-NEXT: LSHR T0.X, PS, literal.x, +; EG-NEXT: OR_INT * T10.Y, PV.Z, PV.W, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T7.X, PV.Y, +; EG-NEXT: MOV * T10.X, T6.X, %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep = getelementptr inbounds <4 x i16>, ptr addrspace(1) %in, i32 %tid %gep.out = getelementptr inbounds <4 x i16>, ptr addrspace(1) %out, i32 %tid diff --git a/llvm/test/CodeGen/AMDGPU/sra.ll b/llvm/test/CodeGen/AMDGPU/sra.ll index 5d169c1..80c0d0f 100644 --- a/llvm/test/CodeGen/AMDGPU/sra.ll +++ b/llvm/test/CodeGen/AMDGPU/sra.ll @@ -320,28 +320,67 @@ define amdgpu_kernel void @ashr_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %i ; ; EG-LABEL: ashr_v4i16: ; EG: ; %bb.0: -; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: TEX 0 @6 -; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[] -; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XY, T8.X, 1 +; EG-NEXT: ALU 48, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T9.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD ; EG-NEXT: Fetch clause starting at 6: -; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1 +; EG-NEXT: VTX_READ_128 T9.XYZW, T9.X, 0, #1 ; EG-NEXT: ALU clause starting at 8: -; EG-NEXT: MOV * T7.X, KC0[2].Z, -; EG-NEXT: ALU clause starting at 9: -; EG-NEXT: LSHR T0.Z, T7.X, literal.x, -; EG-NEXT: BFE_INT T0.W, T7.X, 0.0, literal.x, -; EG-NEXT: AND_INT * T1.W, T7.Z, literal.y, +; EG-NEXT: MOV * T0.Y, T6.X, +; EG-NEXT: MOV * T9.X, KC0[2].Z, +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: BFE_INT T0.W, T9.X, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, T9.Z, literal.y, ; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) -; EG-NEXT: ASHR T7.X, PV.W, PS, -; EG-NEXT: BFE_INT T0.W, PV.Z, 0.0, literal.x, -; EG-NEXT: LSHR * T1.W, T7.Z, literal.x, +; EG-NEXT: ASHR * T0.W, PV.W, PS, +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y, +; EG-NEXT: 65535(9.183409e-41), -65536(nan) +; EG-NEXT: OR_INT * T0.W, PS, PV.W, +; EG-NEXT: MOV * T6.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T9.X, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: LSHR * T1.W, T9.Z, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T0.W, PV.W, PS, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV T6.X, PV.W, +; EG-NEXT: MOV T0.Y, T7.X, +; EG-NEXT: BFE_INT T0.W, T9.Y, 0.0, literal.x, +; EG-NEXT: AND_INT * T1.W, T9.W, literal.y, +; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) +; EG-NEXT: ASHR T0.W, PV.W, PS, +; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x, +; EG-NEXT: -65536(nan), 0(0.000000e+00) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: OR_INT * T0.W, T1.W, PV.W, +; EG-NEXT: MOV * T7.X, PV.W, +; EG-NEXT: MOV T0.Y, PV.X, +; EG-NEXT: LSHR * T0.W, T9.Y, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: LSHR * T1.W, T9.W, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: ASHR T0.W, PV.W, PS, +; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: LSHL * T0.W, PV.W, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) -; EG-NEXT: LSHR T8.X, KC0[2].Y, literal.x, -; EG-NEXT: ASHR * T7.Y, PV.W, PS, +; EG-NEXT: LSHR T9.X, KC0[2].Y, literal.x, +; EG-NEXT: OR_INT * T10.Y, T1.W, PV.W, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV T7.X, PV.Y, +; EG-NEXT: MOV * T10.X, T6.X, %b_ptr = getelementptr <4 x i16>, ptr addrspace(1) %in, i16 1 %a = load <4 x i16>, ptr addrspace(1) %in %b = load <4 x i16>, ptr addrspace(1) %b_ptr diff --git a/llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll new file mode 100644 index 0000000..ac3cd84 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll @@ -0,0 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=riscv64 -mattr='+v' < %s | FileCheck %s + +define <2 x i8> @fp4(<4 x i4> %0) nounwind { +; CHECK-LABEL: fp4: +; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: vslidedown.vi v9, v8, 1 +; CHECK-NEXT: vmv.x.s a1, v9 +; CHECK-NEXT: vslidedown.vi v9, v8, 2 +; CHECK-NEXT: vslidedown.vi v8, v8, 3 +; CHECK-NEXT: andi a0, a0, 15 +; CHECK-NEXT: vmv.x.s a2, v9 +; CHECK-NEXT: andi a1, a1, 15 +; CHECK-NEXT: slli a1, a1, 4 +; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: vmv.x.s a1, v8 +; CHECK-NEXT: andi a2, a2, 15 +; CHECK-NEXT: slli a1, a1, 12 +; CHECK-NEXT: slli a2, a2, 8 +; CHECK-NEXT: or a1, a2, a1 +; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: sh a0, 14(sp) +; CHECK-NEXT: addi a0, sp, 14 +; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret + %2 = bitcast <4 x i4> %0 to <2 x i8> + ret <2 x i8> %2 +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll b/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll index f29c74a..697c582 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll @@ -21,7 +21,7 @@ define <vscale x 4 x i32> @intrinsic_vsha2cl_vv_nxv4i32_nxv4i32(<vscale x 4 x i3 ; CHECK-LABEL: intrinsic_vsha2cl_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: vsha2ch.vv v8, v10, v12 +; CHECK-NEXT: vsha2cl.vv v8, v10, v12 ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32( @@ -45,7 +45,7 @@ define <vscale x 8 x i32> @intrinsic_vsha2cl_vv_nxv8i32_nxv8i32(<vscale x 8 x i3 ; CHECK-LABEL: intrinsic_vsha2cl_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: vsha2ch.vv v8, v12, v16 +; CHECK-NEXT: vsha2cl.vv v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32( @@ -70,7 +70,7 @@ define <vscale x 16 x i32> @intrinsic_vsha2cl_vv_nxv16i32_nxv16i32(<vscale x 16 ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma -; CHECK-NEXT: vsha2ch.vv v8, v16, v24 +; CHECK-NEXT: vsha2cl.vv v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32( @@ -94,7 +94,7 @@ define <vscale x 4 x i64> @intrinsic_vsha2cl_vv_nxv4i64_nxv4i64(<vscale x 4 x i6 ; CHECK-LABEL: intrinsic_vsha2cl_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: vsha2ch.vv v8, v12, v16 +; CHECK-NEXT: vsha2cl.vv v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64( @@ -119,7 +119,7 @@ define <vscale x 8 x i64> @intrinsic_vsha2cl_vv_nxv8i64_nxv8i64(<vscale x 8 x i6 ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma -; CHECK-NEXT: vsha2ch.vv v8, v16, v24 +; CHECK-NEXT: vsha2cl.vv v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i64> @llvm.riscv.vsha2cl.nxv8i64.nxv8i64( diff --git a/llvm/test/CodeGen/X86/avx512f-large-stack.ll b/llvm/test/CodeGen/X86/avx512f-large-stack.ll new file mode 100644 index 0000000..326f72b --- /dev/null +++ b/llvm/test/CodeGen/X86/avx512f-large-stack.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp --version 4 +; RUN: llc -O0 -mtriple=x86_64 -mattr=+avx512f < %s | FileCheck %s --check-prefix=CHECK +define void @f(i16 %LGV2, i1 %LGV3) { +; CHECK-LABEL: f: +; CHECK: # %bb.0: # %BB +; CHECK-NEXT: subq $2147483528, %rsp # imm = 0x7FFFFF88 +; CHECK-NEXT: .cfi_def_cfa_offset 2147483536 +; CHECK-NEXT: movb %sil, %cl +; CHECK-NEXT: movw %di, %ax +; CHECK-NEXT: movswq %ax, %rax +; CHECK-NEXT: andb $1, %cl +; CHECK-NEXT: movabsq $-2147483768, %rdx # imm = 0xFFFFFFFF7FFFFF88 +; CHECK-NEXT: movb %cl, (%rsp,%rdx) +; CHECK-NEXT: addq $2147483528, %rsp # imm = 0x7FFFFF88 +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: retq +BB: + %A = alloca i1, i33 2147483648, align 1 + %G = getelementptr i1, ptr %A, i16 %LGV2 + %G4 = getelementptr i1, ptr %G, i32 -2147483648 + store i1 %LGV3, ptr %G4, align 1 + ret void +} diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll index f3e1417..ed3f0e0 100644 --- a/llvm/test/CodeGen/X86/cmp.ll +++ b/llvm/test/CodeGen/X86/cmp.ll @@ -956,3 +956,185 @@ define i1 @fold_test_and_with_chain(ptr %x, ptr %y, i32 %z) { store i32 %z, ptr %y ret i1 %c } + +define i1 @sext_mask(i32 %a) { +; CHECK-LABEL: sext_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpl $-523, %edi # encoding: [0x81,0xff,0xf5,0xfd,0xff,0xff] +; CHECK-NEXT: # imm = 0xFDF5 +; CHECK-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; CHECK-NEXT: retq # encoding: [0xc3] + %a64 = sext i32 %a to i64 + %v1 = icmp slt i64 %a64, -523 + ret i1 %v1 +} + +define i1 @sext_i9_mask(i9 %a) { +; NO-NDD-LABEL: sext_i9_mask: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: # kill: def $edi killed $edi def $rdi +; NO-NDD-NEXT: shlq $55, %rdi # encoding: [0x48,0xc1,0xe7,0x37] +; NO-NDD-NEXT: sarq $55, %rdi # encoding: [0x48,0xc1,0xff,0x37] +; NO-NDD-NEXT: cmpl $-522, %edi # encoding: [0x81,0xff,0xf6,0xfd,0xff,0xff] +; NO-NDD-NEXT: # imm = 0xFDF6 +; NO-NDD-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: sext_i9_mask: +; NDD: # %bb.0: +; NDD-NEXT: # kill: def $edi killed $edi def $rdi +; NDD-NEXT: shlq $55, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x37] +; NDD-NEXT: sarq $55, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xff,0x37] +; NDD-NEXT: cmpl $-522, %edi # encoding: [0x81,0xff,0xf6,0xfd,0xff,0xff] +; NDD-NEXT: # imm = 0xFDF6 +; NDD-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i9 %a to i64 + %v1 = icmp slt i64 %a64, -522 + ret i1 %v1 +} + +define i1 @sext_i32_mask(i32 %a) { +; CHECK-LABEL: sext_i32_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpl $-522, %edi # encoding: [0x81,0xff,0xf6,0xfd,0xff,0xff] +; CHECK-NEXT: # imm = 0xFDF6 +; CHECK-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; CHECK-NEXT: retq # encoding: [0xc3] + %a64 = sext i32 %a to i64 + %v1 = icmp slt i64 %a64, -522 + ret i1 %v1 +} + +define i1 @i40(i40 %a) { +; NO-NDD-LABEL: i40: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shlq $24, %rdi # encoding: [0x48,0xc1,0xe7,0x18] +; NO-NDD-NEXT: sarq $24, %rdi # encoding: [0x48,0xc1,0xff,0x18] +; NO-NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NO-NDD-NEXT: # imm = 0xFDF7 +; NO-NDD-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: i40: +; NDD: # %bb.0: +; NDD-NEXT: shlq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x18] +; NDD-NEXT: sarq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xff,0x18] +; NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NDD-NEXT: # imm = 0xFDF7 +; NDD-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i40 %a to i64 + %v1 = icmp slt i64 %a64, -521 + ret i1 %v1 +} + +define i1 @sext_i9_mask_sgt(i9 %a) { +; NO-NDD-LABEL: sext_i9_mask_sgt: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: # kill: def $edi killed $edi def $rdi +; NO-NDD-NEXT: shlq $55, %rdi # encoding: [0x48,0xc1,0xe7,0x37] +; NO-NDD-NEXT: sarq $55, %rdi # encoding: [0x48,0xc1,0xff,0x37] +; NO-NDD-NEXT: cmpl $-520, %edi # encoding: [0x81,0xff,0xf8,0xfd,0xff,0xff] +; NO-NDD-NEXT: # imm = 0xFDF8 +; NO-NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: sext_i9_mask_sgt: +; NDD: # %bb.0: +; NDD-NEXT: # kill: def $edi killed $edi def $rdi +; NDD-NEXT: shlq $55, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x37] +; NDD-NEXT: sarq $55, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xff,0x37] +; NDD-NEXT: cmpl $-520, %edi # encoding: [0x81,0xff,0xf8,0xfd,0xff,0xff] +; NDD-NEXT: # imm = 0xFDF8 +; NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i9 %a to i64 + %v1 = icmp sgt i64 %a64, -521 + ret i1 %v1 +} + +define i1 @sext_i32_mask_sgt(i32 %a) { +; CHECK-LABEL: sext_i32_mask_sgt: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpl $-521, %edi # encoding: [0x81,0xff,0xf7,0xfd,0xff,0xff] +; CHECK-NEXT: # imm = 0xFDF7 +; CHECK-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0] +; CHECK-NEXT: retq # encoding: [0xc3] + %a64 = sext i32 %a to i64 + %v1 = icmp sgt i64 %a64, -522 + ret i1 %v1 +} + +define i1 @i40_sge(i40 %a) { +; NO-NDD-LABEL: i40_sge: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shlq $24, %rdi # encoding: [0x48,0xc1,0xe7,0x18] +; NO-NDD-NEXT: sarq $24, %rdi # encoding: [0x48,0xc1,0xff,0x18] +; NO-NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NO-NDD-NEXT: # imm = 0xFDF7 +; NO-NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: i40_sge: +; NDD: # %bb.0: +; NDD-NEXT: shlq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x18] +; NDD-NEXT: sarq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xff,0x18] +; NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NDD-NEXT: # imm = 0xFDF7 +; NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i40 %a to i64 + %v1 = icmp sge i64 %a64, -521 + ret i1 %v1 +} + +define i1 @i40_eq(i40 %a) { +; NO-NDD-LABEL: i40_eq: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: movabsq $1099511627775, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00] +; NO-NDD-NEXT: # imm = 0xFFFFFFFFFF +; NO-NDD-NEXT: andq %rdi, %rax # encoding: [0x48,0x21,0xf8] +; NO-NDD-NEXT: movabsq $1099511627255, %rcx # encoding: [0x48,0xb9,0xf7,0xfd,0xff,0xff,0xff,0x00,0x00,0x00] +; NO-NDD-NEXT: # imm = 0xFFFFFFFDF7 +; NO-NDD-NEXT: cmpq %rcx, %rax # encoding: [0x48,0x39,0xc8] +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: i40_eq: +; NDD: # %bb.0: +; NDD-NEXT: movabsq $1099511627775, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00] +; NDD-NEXT: # imm = 0xFFFFFFFFFF +; NDD-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8] +; NDD-NEXT: movabsq $1099511627255, %rcx # encoding: [0x48,0xb9,0xf7,0xfd,0xff,0xff,0xff,0x00,0x00,0x00] +; NDD-NEXT: # imm = 0xFFFFFFFDF7 +; NDD-NEXT: cmpq %rcx, %rax # encoding: [0x48,0x39,0xc8] +; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i40 %a to i64 + %v1 = icmp eq i64 %a64, -521 + ret i1 %v1 +} + +define i1 @i40_ult(i40 %a) { +; NO-NDD-LABEL: i40_ult: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shlq $24, %rdi # encoding: [0x48,0xc1,0xe7,0x18] +; NO-NDD-NEXT: sarq $24, %rdi # encoding: [0x48,0xc1,0xff,0x18] +; NO-NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NO-NDD-NEXT: # imm = 0xFDF7 +; NO-NDD-NEXT: setb %al # encoding: [0x0f,0x92,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: i40_ult: +; NDD: # %bb.0: +; NDD-NEXT: shlq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x18] +; NDD-NEXT: sarq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xff,0x18] +; NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NDD-NEXT: # imm = 0xFDF7 +; NDD-NEXT: setb %al # encoding: [0x0f,0x92,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i40 %a to i64 + %v1 = icmp ult i64 %a64, -521 + ret i1 %v1 +} diff --git a/llvm/test/CodeGen/X86/huge-stack.ll b/llvm/test/CodeGen/X86/huge-stack.ll index 920033b..41b8a01 100644 --- a/llvm/test/CodeGen/X86/huge-stack.ll +++ b/llvm/test/CodeGen/X86/huge-stack.ll @@ -5,20 +5,70 @@ define void @foo() unnamed_addr #0 { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: -; CHECK-NEXT: movabsq $8589934462, %rax # imm = 0x1FFFFFF7E +; CHECK-NEXT: movabsq $8589934472, %rax # imm = 0x1FFFFFF88 ; CHECK-NEXT: subq %rax, %rsp -; CHECK-NEXT: .cfi_def_cfa_offset 8589934470 -; CHECK-NEXT: movb $42, -129(%rsp) -; CHECK-NEXT: movb $43, -128(%rsp) -; CHECK-NEXT: movabsq $8589934462, %rax # imm = 0x1FFFFFF7E +; CHECK-NEXT: .cfi_def_cfa_offset 8589934480 +; CHECK-NEXT: movabsq $4294967177, %rax # imm = 0xFFFFFF89 +; CHECK-NEXT: movb $42, (%rsp,%rax) +; CHECK-NEXT: movb $43, -118(%rsp) +; CHECK-NEXT: movabsq $8589934472, %rax # imm = 0x1FFFFFF88 ; CHECK-NEXT: addq %rax, %rsp ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: retq - %1 = alloca %large, align 1 - %2 = alloca %large, align 1 - %3 = getelementptr inbounds %large, ptr %1, i64 0, i64 0 - store i8 42, ptr %3, align 1 - %4 = getelementptr inbounds %large, ptr %2, i64 0, i64 0 - store i8 43, ptr %4, align 1 + %large1 = alloca %large, align 1 + %large2 = alloca %large, align 1 + %ptrLarge1 = getelementptr inbounds %large, ptr %large1, i64 0, i64 0 + store i8 42, ptr %ptrLarge1, align 1 + %ptrLarge2 = getelementptr inbounds %large, ptr %large2, i64 0, i64 0 + store i8 43, ptr %ptrLarge2, align 1 ret void } + +declare ptr @baz(ptr, ptr, ptr, ptr) + +define ptr @scavenge_spill() unnamed_addr #0 { +; CHECK-LABEL: scavenge_spill: +; CHECK: # %bb.0: +; CHECK-NEXT: movabsq $25769803816, %rax # imm = 0x600000028 +; CHECK-NEXT: subq %rax, %rsp +; CHECK-NEXT: .cfi_def_cfa_offset 25769803824 +; CHECK-NEXT: movabsq $21474836521, %rax # imm = 0x500000029 +; CHECK-NEXT: leaq (%rsp,%rax), %rdi +; CHECK-NEXT: movabsq $17179869226, %rax # imm = 0x40000002A +; CHECK-NEXT: leaq (%rsp,%rax), %rsi +; CHECK-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; CHECK-NEXT: movabsq $12884901931, %rax # imm = 0x30000002B +; CHECK-NEXT: leaq (%rsp,%rax), %rdx +; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; CHECK-NEXT: movabsq $8589934636, %rax # imm = 0x20000002C +; CHECK-NEXT: leaq (%rsp,%rax), %rcx +; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; CHECK-NEXT: callq baz@PLT +; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload +; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload +; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload +; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; CHECK-NEXT: leaq 46(%rsp), %rdi +; CHECK-NEXT: callq baz@PLT +; CHECK-NEXT: # kill: def $rcx killed $rax +; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload +; CHECK-NEXT: movabsq $25769803816, %rcx # imm = 0x600000028 +; CHECK-NEXT: addq %rcx, %rsp +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: retq + %large1 = alloca %large, align 1 + %ptrLarge1 = getelementptr inbounds %large, ptr %large1, i64 0, i64 0 + %large2 = alloca %large, align 1 + %ptrLarge2 = getelementptr inbounds %large, ptr %large2, i64 0, i64 0 + %large3 = alloca %large, align 1 + %ptrLarge3 = getelementptr inbounds %large, ptr %large3, i64 0, i64 0 + %large4 = alloca %large, align 1 + %ptrLarge4 = getelementptr inbounds %large, ptr %large4, i64 0, i64 0 + %large5 = alloca %large, align 1 + %ptrLarge5 = getelementptr inbounds %large, ptr %large5, i64 0, i64 0 + %ret1 = call ptr @baz(ptr %ptrLarge1, ptr %ptrLarge2, ptr %ptrLarge3, ptr %ptrLarge4) + %large6 = alloca %large, align 1 + %ptrLarge6 = getelementptr inbounds %large, ptr %large6, i64 0, i64 0 + %ret2 = call ptr @baz(ptr %ptrLarge6, ptr %ptrLarge2, ptr %ptrLarge3, ptr %ptrLarge4) + ret ptr %ret1 +} diff --git a/llvm/test/CodeGen/X86/large-displacements-fastisel.ll b/llvm/test/CodeGen/X86/large-displacements-fastisel.ll new file mode 100644 index 0000000..4177466 --- /dev/null +++ b/llvm/test/CodeGen/X86/large-displacements-fastisel.ll @@ -0,0 +1,18 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=x86_64 -O=0 | FileCheck %s +@G = global i8 0 + +; Regression test for PR113856 - incorrect FastISel assert + +define i32 @main() { +; CHECK-LABEL: main: +; CHECK: # %bb.0: +; CHECK-NEXT: movabsq $-2147483652, %rax # imm = 0xFFFFFFFF7FFFFFFC +; CHECK-NEXT: movl $0, (%rsp,%rax) +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %1 = alloca i32, align 4 + %G = getelementptr i8, ptr %1, i32 -2147483648 + store i32 0, ptr %G, align 4 + ret i32 0 +} diff --git a/llvm/test/CodeGen/X86/large-displacements.ll b/llvm/test/CodeGen/X86/large-displacements.ll new file mode 100644 index 0000000..8935ec0 --- /dev/null +++ b/llvm/test/CodeGen/X86/large-displacements.ll @@ -0,0 +1,82 @@ +; RUN: not llc < %s -mtriple=i686 -filetype=null 2>&1 | FileCheck %s -check-prefix=ERR-i686 +; RUN: llc < %s -mtriple=x86_64 | FileCheck %s -check-prefix=x86_64 + +; Regression test for #121932, #113856, #106352, #69365, #25051 which are caused by +; an incorrectly written assertion for 64-bit offsets when compiling for 32-bit X86. + +define i32 @main() #0 { +; ERR-i686: error: <unknown>:0:0: 64-bit offset calculated but target is 32-bit +; +; x86_64-LABEL: main: +; x86_64: # %bb.0: # %entry +; x86_64-NEXT: movl $4294967192, %eax # imm = 0xFFFFFF98 +; x86_64-NEXT: subq %rax, %rsp +; x86_64-NEXT: .cfi_def_cfa_offset 4294967200 +; x86_64-NEXT: movabsq $3221225318, %rax # imm = 0xBFFFFF66 +; x86_64-NEXT: movb $32, (%rsp,%rax) +; x86_64-NEXT: movb $33, 2147483494(%rsp) +; x86_64-NEXT: movb $34, 1073741670(%rsp) +; x86_64-NEXT: movb $35, -154(%rsp) +; x86_64-NEXT: xorl %eax, %eax +; x86_64-NEXT: movl $4294967192, %ecx # imm = 0xFFFFFF98 +; x86_64-NEXT: addq %rcx, %rsp +; x86_64-NEXT: .cfi_def_cfa_offset 8 +; x86_64-NEXT: retq +entry: + %a = alloca [1073741824 x i8], align 16 + %b = alloca [1073741824 x i8], align 16 + %c = alloca [1073741824 x i8], align 16 + %d = alloca [1073741824 x i8], align 16 + + %arrayida = getelementptr inbounds [1073741824 x i8], ptr %a, i64 0, i64 -42 + %arrayidb = getelementptr inbounds [1073741824 x i8], ptr %b, i64 0, i64 -42 + %arrayidc = getelementptr inbounds [1073741824 x i8], ptr %c, i64 0, i64 -42 + %arrayidd = getelementptr inbounds [1073741824 x i8], ptr %d, i64 0, i64 -42 + + store i8 32, ptr %arrayida, align 2 + store i8 33, ptr %arrayidb, align 2 + store i8 34, ptr %arrayidc, align 2 + store i8 35, ptr %arrayidd, align 2 + + ret i32 0 +} + +; Same test as above but for an anonymous function. +define i32 @0() #0 { +; ERR-i686: error: <unknown>:0:0: 64-bit offset calculated but target is 32-bit +; +; x86_64-LABEL: __unnamed_1: +; x86_64: # %bb.0: # %entry +; x86_64-NEXT: movl $4294967192, %eax # imm = 0xFFFFFF98 +; x86_64-NEXT: subq %rax, %rsp +; x86_64-NEXT: .cfi_def_cfa_offset 4294967200 +; x86_64-NEXT: movabsq $3221225318, %rax # imm = 0xBFFFFF66 +; x86_64-NEXT: movb $32, (%rsp,%rax) +; x86_64-NEXT: movb $33, 2147483494(%rsp) +; x86_64-NEXT: movb $34, 1073741670(%rsp) +; x86_64-NEXT: movb $35, -154(%rsp) +; x86_64-NEXT: xorl %eax, %eax +; x86_64-NEXT: movl $4294967192, %ecx # imm = 0xFFFFFF98 +; x86_64-NEXT: addq %rcx, %rsp +; x86_64-NEXT: .cfi_def_cfa_offset 8 +; x86_64-NEXT: retq +entry: + %a = alloca [1073741824 x i8], align 16 + %b = alloca [1073741824 x i8], align 16 + %c = alloca [1073741824 x i8], align 16 + %d = alloca [1073741824 x i8], align 16 + + %arrayida = getelementptr inbounds [1073741824 x i8], ptr %a, i64 0, i64 -42 + %arrayidb = getelementptr inbounds [1073741824 x i8], ptr %b, i64 0, i64 -42 + %arrayidc = getelementptr inbounds [1073741824 x i8], ptr %c, i64 0, i64 -42 + %arrayidd = getelementptr inbounds [1073741824 x i8], ptr %d, i64 0, i64 -42 + + store i8 32, ptr %arrayida, align 2 + store i8 33, ptr %arrayidb, align 2 + store i8 34, ptr %arrayidc, align 2 + store i8 35, ptr %arrayidd, align 2 + + ret i32 0 +} + +attributes #0 = { optnone noinline } diff --git a/llvm/test/CodeGen/X86/merge-huge-sp-updates.ll b/llvm/test/CodeGen/X86/merge-huge-sp-updates.ll index b26345e..6920e74 100644 --- a/llvm/test/CodeGen/X86/merge-huge-sp-updates.ll +++ b/llvm/test/CodeGen/X86/merge-huge-sp-updates.ll @@ -22,8 +22,8 @@ entry: call void @bar(i64 0, i64 0, i64 0, i64 0, i64 0, ptr null, ptr %rhs, ptr null, ptr %rhs) ; CHECK: call{{.*}}bar ; CHECK: addq{{.*}}$2147483647, %rsp -; CHECK: addq{{.*}}$372037585, %rsp -; CHECK: .cfi_adjust_cfa_offset -2519521232 +; CHECK: addq{{.*}}$372037601, %rsp +; CHECK: .cfi_adjust_cfa_offset -2519521248 ret void } diff --git a/llvm/test/CodeGen/X86/stack-clash-extra-huge.ll b/llvm/test/CodeGen/X86/stack-clash-extra-huge.ll index d9b20f5..4c8bb62 100644 --- a/llvm/test/CodeGen/X86/stack-clash-extra-huge.ll +++ b/llvm/test/CodeGen/X86/stack-clash-extra-huge.ll @@ -16,13 +16,13 @@ define i32 @foo() local_unnamed_addr #0 { ; CHECK-X64-NEXT: cmpq %r11, %rsp ; CHECK-X64-NEXT: jne .LBB0_1 ; CHECK-X64-NEXT: # %bb.2: -; CHECK-X64-NEXT: subq $3976, %rsp # imm = 0xF88 +; CHECK-X64-NEXT: subq $3992, %rsp # imm = 0xF98 ; CHECK-X64-NEXT: .cfi_def_cfa_register %rsp -; CHECK-X64-NEXT: .cfi_def_cfa_offset 4799999888 -; CHECK-X64-NEXT: movl $1, 264(%rsp) -; CHECK-X64-NEXT: movl $1, 28664(%rsp) -; CHECK-X64-NEXT: movl -128(%rsp), %eax -; CHECK-X64-NEXT: movabsq $4799999880, %rcx # imm = 0x11E1A2F88 +; CHECK-X64-NEXT: .cfi_def_cfa_offset 4799999904 +; CHECK-X64-NEXT: movl $1, 280(%rsp) +; CHECK-X64-NEXT: movl $1, 28680(%rsp) +; CHECK-X64-NEXT: movl -112(%rsp), %eax +; CHECK-X64-NEXT: movabsq $4799999896, %rcx # imm = 0x11E1A2F98 ; CHECK-X64-NEXT: addq %rcx, %rsp ; CHECK-X64-NEXT: .cfi_def_cfa_offset 8 ; CHECK-X64-NEXT: retq @@ -30,10 +30,10 @@ define i32 @foo() local_unnamed_addr #0 { ; CHECK-X86-LABEL: foo: ; CHECK-X86: # %bb.0: ; CHECK-X86-NEXT: ud2 -; CHECK-X86-NEXT: .cfi_def_cfa_offset 4800000016 -; CHECK-X86-NEXT: movl $1, 392(%esp) -; CHECK-X86-NEXT: movl $1, 28792(%esp) -; CHECK-X86-NEXT: movl (%esp), %eax +; CHECK-X86-NEXT: .cfi_def_cfa_offset 4800000032 +; CHECK-X86-NEXT: movl $1, 408(%esp) +; CHECK-X86-NEXT: movl $1, 28808(%esp) +; CHECK-X86-NEXT: movl 16(%esp), %eax ; CHECK-X86-NEXT: ud2 ; CHECK-X86-NEXT: .cfi_def_cfa_offset 4 ; CHECK-X86-NEXT: retl @@ -41,10 +41,10 @@ define i32 @foo() local_unnamed_addr #0 { ; CHECK-X32-LABEL: foo: ; CHECK-X32: # %bb.0: ; CHECK-X32-NEXT: ud2 -; CHECK-X32-NEXT: .cfi_def_cfa_offset 4799999888 -; CHECK-X32-NEXT: movl $1, 264(%esp) -; CHECK-X32-NEXT: movl $1, 28664(%esp) -; CHECK-X32-NEXT: movl -128(%esp), %eax +; CHECK-X32-NEXT: .cfi_def_cfa_offset 4799999904 +; CHECK-X32-NEXT: movl $1, 280(%esp) +; CHECK-X32-NEXT: movl $1, 28680(%esp) +; CHECK-X32-NEXT: movl -112(%esp), %eax ; CHECK-X32-NEXT: ud2 ; CHECK-X32-NEXT: .cfi_def_cfa_offset 8 ; CHECK-X32-NEXT: retq diff --git a/llvm/test/CodeGen/X86/stack-clash-huge.ll b/llvm/test/CodeGen/X86/stack-clash-huge.ll index c999077..0e8c215 100644 --- a/llvm/test/CodeGen/X86/stack-clash-huge.ll +++ b/llvm/test/CodeGen/X86/stack-clash-huge.ll @@ -16,13 +16,13 @@ define i32 @foo() local_unnamed_addr #0 { ; CHECK-X64-NEXT: cmpq %r11, %rsp ; CHECK-X64-NEXT: jne .LBB0_1 ; CHECK-X64-NEXT: # %bb.2: -; CHECK-X64-NEXT: subq $1928, %rsp # imm = 0x788 +; CHECK-X64-NEXT: subq $1944, %rsp # imm = 0x798 ; CHECK-X64-NEXT: .cfi_def_cfa_register %rsp -; CHECK-X64-NEXT: .cfi_def_cfa_offset 2399999888 -; CHECK-X64-NEXT: movl $1, 264(%rsp) -; CHECK-X64-NEXT: movl $1, 28664(%rsp) -; CHECK-X64-NEXT: movl -128(%rsp), %eax -; CHECK-X64-NEXT: movl $2399999880, %ecx # imm = 0x8F0D1788 +; CHECK-X64-NEXT: .cfi_def_cfa_offset 2399999904 +; CHECK-X64-NEXT: movl $1, 280(%rsp) +; CHECK-X64-NEXT: movl $1, 28680(%rsp) +; CHECK-X64-NEXT: movl -112(%rsp), %eax +; CHECK-X64-NEXT: movl $2399999896, %ecx # imm = 0x8F0D1798 ; CHECK-X64-NEXT: addq %rcx, %rsp ; CHECK-X64-NEXT: .cfi_def_cfa_offset 8 ; CHECK-X64-NEXT: retq @@ -39,13 +39,13 @@ define i32 @foo() local_unnamed_addr #0 { ; CHECK-X86-NEXT: cmpl %eax, %esp ; CHECK-X86-NEXT: jne .LBB0_1 ; CHECK-X86-NEXT: # %bb.2: -; CHECK-X86-NEXT: subl $2060, %esp # imm = 0x80C +; CHECK-X86-NEXT: subl $2076, %esp # imm = 0x81C ; CHECK-X86-NEXT: .cfi_def_cfa_register %esp -; CHECK-X86-NEXT: .cfi_def_cfa_offset 2400000016 -; CHECK-X86-NEXT: movl $1, 392(%esp) -; CHECK-X86-NEXT: movl $1, 28792(%esp) -; CHECK-X86-NEXT: movl (%esp), %eax -; CHECK-X86-NEXT: movl $2400000012, %ecx # imm = 0x8F0D180C +; CHECK-X86-NEXT: .cfi_def_cfa_offset 2400000032 +; CHECK-X86-NEXT: movl $1, 408(%esp) +; CHECK-X86-NEXT: movl $1, 28808(%esp) +; CHECK-X86-NEXT: movl 16(%esp), %eax +; CHECK-X86-NEXT: movl $2400000028, %ecx # imm = 0x8F0D181C ; CHECK-X86-NEXT: addl %ecx, %esp ; CHECK-X86-NEXT: .cfi_def_cfa_offset 4 ; CHECK-X86-NEXT: retl @@ -62,13 +62,13 @@ define i32 @foo() local_unnamed_addr #0 { ; CHECK-X32-NEXT: cmpl %r11d, %esp ; CHECK-X32-NEXT: jne .LBB0_1 ; CHECK-X32-NEXT: # %bb.2: -; CHECK-X32-NEXT: subl $1928, %esp # imm = 0x788 +; CHECK-X32-NEXT: subl $1944, %esp # imm = 0x798 ; CHECK-X32-NEXT: .cfi_def_cfa_register %rsp -; CHECK-X32-NEXT: .cfi_def_cfa_offset 2399999888 -; CHECK-X32-NEXT: movl $1, 264(%esp) -; CHECK-X32-NEXT: movl $1, 28664(%esp) -; CHECK-X32-NEXT: movl -128(%esp), %eax -; CHECK-X32-NEXT: movl $2399999880, %ecx # imm = 0x8F0D1788 +; CHECK-X32-NEXT: .cfi_def_cfa_offset 2399999904 +; CHECK-X32-NEXT: movl $1, 280(%esp) +; CHECK-X32-NEXT: movl $1, 28680(%esp) +; CHECK-X32-NEXT: movl -112(%esp), %eax +; CHECK-X32-NEXT: movl $2399999896, %ecx # imm = 0x8F0D1798 ; CHECK-X32-NEXT: addl %ecx, %esp ; CHECK-X32-NEXT: .cfi_def_cfa_offset 8 ; CHECK-X32-NEXT: retq diff --git a/llvm/test/CodeGen/X86/win64-stackprobe-overflow.ll b/llvm/test/CodeGen/X86/win64-stackprobe-overflow.ll index 9555ce0..732fc65 100644 --- a/llvm/test/CodeGen/X86/win64-stackprobe-overflow.ll +++ b/llvm/test/CodeGen/X86/win64-stackprobe-overflow.ll @@ -10,5 +10,5 @@ start: attributes #0 = { nonlazybind uwtable "probe-stack"="probe_stack" "target-cpu"="x86-64" } ; CHECK-LABEL: foo: -; CHECK: movabsq $4294967304, %rax +; CHECK: movabsq $4294967312, %rax ; CHECK-NEXT: callq probe_stack diff --git a/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll b/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll index d609a3f..65542e8 100644 --- a/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll +++ b/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll @@ -1,21 +1,45 @@ ; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+relax %s -o %t.o -; RUN: llvm-readobj -r %t.o | FileCheck -check-prefix=READOBJ-RELOCS %s +; RUN: llvm-readobj -r %t.o | FileCheck -check-prefix=RELOC %s ; RUN: llvm-objdump --source %t.o | FileCheck --check-prefix=OBJDUMP-SOURCE %s -; RUN: llvm-dwarfdump --debug-info %t.o | \ -; RUN: FileCheck -check-prefix=DWARF-DUMP %s -; RUN: llvm-dwarfdump --debug-line -v %t.o | \ -; RUN: FileCheck -check-prefix=LINE-DUMP %s +; RUN: llvm-dwarfdump --debug-info -debug-line -v %t.o | \ +; RUN: FileCheck -check-prefix=DWARF %s -; Check that we actually have relocations, otherwise this is kind of pointless. -; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_info { -; READOBJ-RELOCS: 0x1B R_RISCV_ADD32 .L0 0x0 -; READOBJ-RELOCS-NEXT: 0x1B R_RISCV_SUB32 .L0 0x0 -; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_frame { -; READOBJ-RELOCS: 0x20 R_RISCV_ADD32 .L0 0x0 -; READOBJ-RELOCS-NEXT: 0x20 R_RISCV_SUB32 .L0 0x0 -; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_line { -; READOBJ-RELOCS: 0x5A R_RISCV_ADD16 .L0 0x0 -; READOBJ-RELOCS-NEXT: 0x5A R_RISCV_SUB16 .L0 0x0 +; RELOC: .rela.debug_info { +; RELOC-NEXT: 0x8 R_RISCV_32 .debug_abbrev 0x0 +; RELOC-NEXT: 0x11 R_RISCV_32 .L0 0x0 +; RELOC-NEXT: 0x15 R_RISCV_32 .Lline_table_start0 0x0 +; RELOC-NEXT: 0x1B R_RISCV_ADD32 .L0 0x0 +; RELOC-NEXT: 0x1B R_RISCV_SUB32 .L0 0x0 +; RELOC-NEXT: 0x1F R_RISCV_32 .L0 0x0 +; RELOC-NEXT: 0x25 R_RISCV_ADD32 .L0 0x0 +; RELOC-NEXT: 0x25 R_RISCV_SUB32 .L0 0x0 +; RELOC-NEXT: } +; RELOC-NEXT: .rela.debug_str_offsets { +; RELOC-NEXT: 0x8 R_RISCV_32 .L0 0x0 +; RELOC-NEXT: 0xC R_RISCV_32 .L0 0x0 +; RELOC-NEXT: 0x10 R_RISCV_32 .L0 0x0 +; RELOC-NEXT: 0x14 R_RISCV_32 .L0 0x0 +; RELOC-NEXT: 0x18 R_RISCV_32 .L0 0x0 +; RELOC-NEXT: } +; RELOC-NEXT: .rela.debug_addr { +; RELOC-NEXT: 0x8 R_RISCV_32 .L0 0x0 +; RELOC-NEXT: } +; RELOC-NEXT: .rela.debug_frame { +; RELOC-NEXT: 0x18 R_RISCV_32 .L0 0x0 +; RELOC-NEXT: 0x1C R_RISCV_32 .L0 0x0 +; RELOC-NEXT: 0x20 R_RISCV_ADD32 .L0 0x0 +; RELOC-NEXT: 0x20 R_RISCV_SUB32 .L0 0x0 +; RELOC-NEXT: 0x33 R_RISCV_SET6 .L0 0x0 +; RELOC-NEXT: 0x33 R_RISCV_SUB6 .L0 0x0 +; RELOC-NEXT: } +; RELOC-NEXT: .rela.debug_line { +; RELOC-NEXT: 0x22 R_RISCV_32 .debug_line_str 0x0 +; RELOC-NEXT: 0x31 R_RISCV_32 .debug_line_str 0x2 +; RELOC-NEXT: 0x46 R_RISCV_32 .debug_line_str 0x17 +; RELOC-NEXT: 0x4F R_RISCV_32 .L0 0x0 +; RELOC-NEXT: 0x5B R_RISCV_ADD16 .L0 0x0 +; RELOC-NEXT: 0x5B R_RISCV_SUB16 .L0 0x0 +; RELOC-NEXT: } ; Check that we can print the source, even with relocations. ; OBJDUMP-SOURCE: Disassembly of section .text: @@ -24,70 +48,61 @@ ; OBJDUMP-SOURCE: ; { ; OBJDUMP-SOURCE: ; return 0; -; Check that we correctly dump the DWARF info, even with relocations. -; DWARF-DUMP: DW_AT_name ("dwarf-riscv-relocs.c") -; DWARF-DUMP: DW_AT_comp_dir (".") -; DWARF-DUMP: DW_AT_name ("main") -; DWARF-DUMP: DW_AT_decl_file ("{{.*}}dwarf-riscv-relocs.c") -; DWARF-DUMP: DW_AT_decl_line (1) -; DWARF-DUMP: DW_AT_type (0x00000032 "int") -; DWARF-DUMP: DW_AT_name ("int") -; DWARF-DUMP: DW_AT_encoding (DW_ATE_signed) -; DWARF-DUMP: DW_AT_byte_size (0x04) - -; LINE-DUMP: .debug_line contents: -; LINE-DUMP-NEXT: debug_line[0x00000000] -; LINE-DUMP-NEXT: Line table prologue: -; LINE-DUMP-NEXT: total_length: 0x00000061 -; LINE-DUMP-NEXT: format: DWARF32 -; LINE-DUMP-NEXT: version: 5 -; LINE-DUMP-NEXT: address_size: 4 -; LINE-DUMP-NEXT: seg_select_size: 0 -; LINE-DUMP-NEXT: prologue_length: 0x0000003e -; LINE-DUMP-NEXT: min_inst_length: 1 -; LINE-DUMP-NEXT: max_ops_per_inst: 1 -; LINE-DUMP-NEXT: default_is_stmt: 1 -; LINE-DUMP-NEXT: line_base: -5 -; LINE-DUMP-NEXT: line_range: 14 -; LINE-DUMP-NEXT: opcode_base: 13 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_copy] = 0 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_advance_pc] = 1 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_advance_line] = 1 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_set_file] = 1 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_set_column] = 1 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_negate_stmt] = 0 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_set_basic_block] = 0 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_const_add_pc] = 0 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_fixed_advance_pc] = 1 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_set_prologue_end] = 0 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_set_epilogue_begin] = 0 -; LINE-DUMP-NEXT: standard_opcode_lengths[DW_LNS_set_isa] = 1 -; LINE-DUMP-NEXT: include_directories[ 0] = .debug_line_str[0x00000000] = "." -; LINE-DUMP-NEXT: file_names[ 0]: -; LINE-DUMP-NEXT: name: .debug_line_str[0x00000002] = "dwarf-riscv-relocs.c" -; LINE-DUMP-NEXT: dir_index: 0 -; LINE-DUMP-NEXT: md5_checksum: 05ab89f5481bc9f2d037e7886641e919 -; LINE-DUMP-NEXT: source: .debug_line_str[0x00000017] = "int main()\n{\n return 0;\n}\n" -; LINE-DUMP-EMPTY: -; LINE-DUMP-NEXT: Address Line Column File ISA Discriminator OpIndex Flags -; LINE-DUMP-NEXT: ------------------ ------ ------ ------ --- ------------- ------- ------------- -; LINE-DUMP-NEXT:0x0000004a: 04 DW_LNS_set_file (0) -; LINE-DUMP-NEXT:0x0000004c: 00 DW_LNE_set_address (0x00000000) -; LINE-DUMP-NEXT:0x00000053: 13 address += 0, line += 1, op-index += 0 -; LINE-DUMP-NEXT: 0x0000000000000000 2 0 0 0 0 0 is_stmt -; LINE-DUMP-NEXT:0x00000054: 05 DW_LNS_set_column (5) -; LINE-DUMP-NEXT:0x00000056: 0a DW_LNS_set_prologue_end -; LINE-DUMP-NEXT:0x00000057: 03 DW_LNS_advance_line (3) -; LINE-DUMP-NEXT:0x00000059: 09 DW_LNS_fixed_advance_pc (addr += 0x001c, op-index = 0) -; LINE-DUMP-NEXT:0x0000005c: 01 DW_LNS_copy -; LINE-DUMP-NEXT: 0x000000000000001c 3 5 0 0 0 0 is_stmt prologue_end -; LINE-DUMP-NEXT:0x0000005d: 06 DW_LNS_negate_stmt -; LINE-DUMP-NEXT:0x0000005e: 0b DW_LNS_set_epilogue_begin -; LINE-DUMP-NEXT:0x0000005f: 4a address += 4, line += 0, op-index += 0 -; LINE-DUMP-NEXT: 0x0000000000000020 3 5 0 0 0 0 epilogue_begin -; LINE-DUMP-NEXT:0x00000060: 02 DW_LNS_advance_pc (addr += 16, op-index += 0) -; LINE-DUMP-NEXT:0x00000062: 00 DW_LNE_end_sequence -; LINE-DUMP-NEXT: 0x0000000000000030 3 5 0 0 0 0 end_sequence +; DWARF: .debug_line contents: +; DWARF-NEXT: debug_line[0x00000000] +; DWARF-NEXT: Line table prologue: +; DWARF-NEXT: total_length: 0x00000062 +; DWARF-NEXT: format: DWARF32 +; DWARF-NEXT: version: 5 +; DWARF-NEXT: address_size: 4 +; DWARF-NEXT: seg_select_size: 0 +; DWARF-NEXT: prologue_length: 0x0000003e +; DWARF-NEXT: min_inst_length: 1 +; DWARF-NEXT: max_ops_per_inst: 1 +; DWARF-NEXT: default_is_stmt: 1 +; DWARF-NEXT: line_base: -5 +; DWARF-NEXT: line_range: 14 +; DWARF-NEXT: opcode_base: 13 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_copy] = 0 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_advance_pc] = 1 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_advance_line] = 1 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_set_file] = 1 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_set_column] = 1 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_negate_stmt] = 0 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_set_basic_block] = 0 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_const_add_pc] = 0 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_fixed_advance_pc] = 1 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_set_prologue_end] = 0 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_set_epilogue_begin] = 0 +; DWARF-NEXT: standard_opcode_lengths[DW_LNS_set_isa] = 1 +; DWARF-NEXT: include_directories[ 0] = .debug_line_str[0x00000000] = "." +; DWARF-NEXT: file_names[ 0]: +; DWARF-NEXT: name: .debug_line_str[0x00000002] = "dwarf-riscv-relocs.c" +; DWARF-NEXT: dir_index: 0 +; DWARF-NEXT: md5_checksum: 05ab89f5481bc9f2d037e7886641e919 +; DWARF-NEXT: source: .debug_line_str[0x00000017] = "int main()\n{\n return 0;\n}\n" +; DWARF-EMPTY: +; DWARF-NEXT: Address Line Column File ISA Discriminator OpIndex Flags +; DWARF-NEXT: ------------------ ------ ------ ------ --- ------------- ------- ------------- +; DWARF-NEXT:0x0000004a: 04 DW_LNS_set_file (0) +; DWARF-NEXT:0x0000004c: 00 DW_LNE_set_address (0x00000000) +; DWARF-NEXT:0x00000053: 13 address += 0, line += 1, op-index += 0 +; DWARF-NEXT: 0x0000000000000000 2 0 0 0 0 0 is_stmt +; DWARF-NEXT:0x00000054: 05 DW_LNS_set_column (5) +; DWARF-NEXT:0x00000056: 0a DW_LNS_set_prologue_end +; DWARF-NEXT:0x00000057: f3 address += 16, line += 1, op-index += 0 +; DWARF-NEXT: 0x0000000000000010 3 5 0 0 0 0 is_stmt prologue_end +; DWARF-NEXT:0x00000058: 03 DW_LNS_advance_line (4) +; DWARF-NEXT:0x0000005a: 09 DW_LNS_fixed_advance_pc (addr += 0x0010, op-index = 0) +; DWARF-NEXT:0x0000005d: 01 DW_LNS_copy +; DWARF-NEXT: 0x0000000000000020 4 5 0 0 0 0 is_stmt +; DWARF-NEXT:0x0000005e: 06 DW_LNS_negate_stmt +; DWARF-NEXT:0x0000005f: 0b DW_LNS_set_epilogue_begin +; DWARF-NEXT:0x00000060: 4a address += 4, line += 0, op-index += 0 +; DWARF-NEXT: 0x0000000000000024 4 5 0 0 0 0 epilogue_begin +; DWARF-NEXT:0x00000061: 02 DW_LNS_advance_pc (addr += 16, op-index += 0) +; DWARF-NEXT:0x00000063: 00 DW_LNE_end_sequence +; DWARF-NEXT: 0x0000000000000034 4 5 0 0 0 0 end_sequence ; ModuleID = 'dwarf-riscv-relocs.c' source_filename = "dwarf-riscv-relocs.c" @@ -97,10 +112,8 @@ target triple = "riscv32" ; Function Attrs: noinline nounwind optnone define dso_local i32 @main() #0 !dbg !7 { entry: - call void @ext() - %retval = alloca i32, align 4 - store i32 0, ptr %retval, align 4 - ret i32 0, !dbg !11 + call void asm sideeffect ".cfi_remember_state\0A\09.cfi_adjust_cfa_offset 16\0A\09nop\0A\09call ext\0A\09nop\0A\09.cfi_restore_state\0A\09", ""() #1, !dbg !11 + ret i32 0, !dbg !12 } declare void @ext() @@ -123,3 +136,4 @@ attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-ma !9 = !{!10} !10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) !11 = !DILocation(line: 3, column: 5, scope: !7) +!12 = !DILocation(line: 4, column: 5, scope: !7) diff --git a/llvm/test/ExecutionEngine/MCJIT/stubs-sm-pic.ll b/llvm/test/ExecutionEngine/MCJIT/stubs-sm-pic.ll index 513e252a..9522bfa 100644 --- a/llvm/test/ExecutionEngine/MCJIT/stubs-sm-pic.ll +++ b/llvm/test/ExecutionEngine/MCJIT/stubs-sm-pic.ll @@ -1,5 +1,7 @@ ; RUN: %lli -jit-kind=mcjit -disable-lazy-compilation=false -relocation-model=pic -code-model=small %s -; XFAIL: target={{(mips|mipsel)-.*}}, target={{(i686|i386).*}}, target={{(aarch64|arm).*}} +; XFAIL: target={{(mips|mipsel)-.*}}, target={{(i686|i386).*}}, target={{(aarch64|arm).*}}, target={{.*-(cygwin|windows-cygnus)}} +; This test segfaults on cygwin, but succeeds with cygwin-elf. Unfortunately, +; cygwin-elf breaks the remote tests due to lack of __register_frame. define i32 @main() nounwind { entry: diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s index 887d484..13f1bb0 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s @@ -886,3 +886,282 @@ v_permlane_idx_gen_b32 v5, v1, exec_hi v_permlane_idx_gen_b32 v5, v1, exec_lo // GFX1250: v_permlane_idx_gen_b32 v5, v1, exec_lo ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xfd,0x00,0x00] + +v_cvt_scalef32_pk8_fp8_bf16 v[10:11], v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_fp8_bf16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xb4,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp8_bf16 v[10:11], v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp8_bf16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb4,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_bf8_bf16 v[10:11], v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_bf8_bf16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xb5,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_bf8_bf16 v[10:11], v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_bf8_bf16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb5,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_fp8_f16 v[10:11], v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_fp8_f16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xc4,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp8_f16 v[10:11], v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp8_f16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xc4,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_bf8_f16 v[10:11], v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_bf8_f16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xc6,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_bf8_f16 v[10:11], v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_bf8_f16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xc6,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[20:27], v8 ; encoding: [0x0a,0x00,0xc3,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xc3,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[20:27], v8 ; encoding: [0x0a,0x00,0xc5,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xc5,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_fp4_f32 v10, v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk8_fp4_f32 v10, v[20:27], v8 ; encoding: [0x0a,0x00,0xb0,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp4_f32 v10, v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp4_f32 v10, v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xb0,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_fp4_f16 v10, v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_fp4_f16 v10, v[20:23], v8 ; encoding: [0x0a,0x00,0xb3,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp4_f16 v10, v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp4_f16 v10, v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb3,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_fp4_bf16 v10, v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_fp4_bf16 v10, v[20:23], v8 ; encoding: [0x0a,0x00,0xb8,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp4_bf16 v10, v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp4_bf16 v10, v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb8,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp8_bf16 v[10:11], v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_bf16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xc0,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp8_bf16 v[10:11], v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_bf16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xc0,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_bf8_bf16 v[10:11], v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_bf16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xc2,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_bf8_bf16 v[10:11], v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_bf16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xc2,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp8_f16 v[10:11], v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_f16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xbf,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp8_f16 v[10:11], v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_f16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xbf,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_bf8_f16 v[10:11], v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_f16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xc1,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_bf8_f16 v[10:11], v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_f16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xc1,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0x98,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0x98,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0x99,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0x99,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[20:27], v4, v8 ; encoding: [0x0a,0x00,0x97,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0x97,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp4_f16 v10, v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_f16 v10, v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xb9,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp4_f16 v10, v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_f16 v10, v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xb9,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp4_bf16 v10, v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_bf16 v10, v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xbc,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp4_bf16 v10, v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_bf16 v10, v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xbc,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_perm_pk16_b4_u4 v[2:3], v4, v5, v[6:7] +// GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, v5, v[6:7] ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0b,0x1a,0x04] + +v_perm_pk16_b4_u4 v[2:3], v4, ttmp5, s[6:7] +// GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, ttmp5, s[6:7] ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0xe3,0x18,0x00] + +v_perm_pk16_b4_u4 v[2:3], s4, v5, v[6:7] +// GFX1250: v_perm_pk16_b4_u4 v[2:3], s4, v5, v[6:7] ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0a,0x1a,0x04] + +v_perm_pk16_b4_u4 v[2:3], v4, v5, 100 +// GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, v5, 0x64 ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0b,0xfe,0x03,0x64,0x00,0x00,0x00] + +v_perm_pk16_b4_u4 v[2:3], v4, v5, 4 +// GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, v5, 4 ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0b,0x12,0x02] + +v_perm_pk16_b6_u4 v[2:4], v4, v[8:9], v[6:7] +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[8:9], v[6:7] ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x11,0x1a,0x04] + +v_perm_pk16_b6_u4 v[2:4], v4, ttmp[4:5], s[6:7] +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, ttmp[4:5], s[6:7] ; encoding: [0x02,0x00,0x42,0xd6,0x04,0xe1,0x18,0x00] + +v_perm_pk16_b6_u4 v[2:4], s4, v[4:5], v[6:7] +// GFX1250: v_perm_pk16_b6_u4 v[2:4], s4, v[4:5], v[6:7] ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x08,0x1a,0x04] + +v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 100 +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 0x64 ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x09,0xfe,0x03,0x64,0x00,0x00,0x00] + +v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 4 +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 4 ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x09,0x12,0x02] + +v_perm_pk16_b8_u4 v[2:5], v[4:5], v[8:9], v[6:7] +// GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], v[8:9], v[6:7] ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x11,0x1a,0x04] + +v_perm_pk16_b8_u4 v[2:5], v[4:5], ttmp[4:5], s[6:7] +// GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], ttmp[4:5], s[6:7] ; encoding: [0x02,0x00,0x43,0xd6,0x04,0xe1,0x18,0x00] + +v_perm_pk16_b8_u4 v[2:5], s[4:5], v[4:5], v[6:7] +// GFX1250: v_perm_pk16_b8_u4 v[2:5], s[4:5], v[4:5], v[6:7] ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x08,0x1a,0x04] + +v_perm_pk16_b8_u4 v[2:5], v[4:5], v[4:5], 100 +// GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], v[4:5], 0x64 ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x09,0xfe,0x03,0x64,0x00,0x00,0x00] + +v_perm_pk16_b8_u4 v[2:5], v[4:5], v[4:5], 4 +// GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], v[4:5], 4 ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x09,0x12,0x02] + +v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xcb,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xcb,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], v8 scale_sel:1 +// GFX1250: v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], v8 scale_sel:1 ; encoding: [0x0a,0x08,0xcb,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xca,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xca,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], v8 scale_sel:2 +// GFX1250: v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], v8 scale_sel:2 ; encoding: [0x0a,0x10,0xca,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xc8,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xc8,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], v8 scale_sel:3 +// GFX1250: v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], v8 scale_sel:3 ; encoding: [0x0a,0x18,0xc8,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xc7,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xc7,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], v8 scale_sel:4 +// GFX1250: v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], v8 scale_sel:4 ; encoding: [0x0a,0x20,0xc7,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], v8 ; encoding: [0x0a,0x00,0xc9,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xc9,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], v8 scale_sel:4 +// GFX1250: v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], v8 scale_sel:4 ; encoding: [0x0a,0x20,0xc9,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], v8 ; encoding: [0x0a,0x00,0xcc,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xcc,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], v8 scale_sel:5 +// GFX1250: v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], v8 scale_sel:5 ; encoding: [0x0a,0x28,0xcc,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xd2,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xd2,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xd0,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xd0,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_bf6_f32 v[10:12], v[20:35], 100.0 +// GFX1250: v_cvt_scalef32_pk16_bf6_f32 v[10:12], v[20:35], 0x42c80000 ; encoding: [0x0a,0x00,0xce,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_bf6_f32 v[10:12], v[20:35], v8 +// GFX1250: v_cvt_scalef32_pk16_bf6_f32 v[10:12], v[20:35], v8 ; encoding: [0x0a,0x00,0xce,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xd1,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xd1,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xcf,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xcf,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_fp6_f32 v[10:12], v[20:35], 100.0 +// GFX1250: v_cvt_scalef32_pk16_fp6_f32 v[10:12], v[20:35], 0x42c80000 ; encoding: [0x0a,0x00,0xcd,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_fp6_f32 v[10:12], v[20:35], v8 +// GFX1250: v_cvt_scalef32_pk16_fp6_f32 v[10:12], v[20:35], v8 ; encoding: [0x0a,0x00,0xcd,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd8,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd8,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd6,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd6,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd7,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd7,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd5,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd5,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk16_bf6_f32 v[10:12], v[20:35], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_f32 v[10:12], v[20:35], v4, v8 ; encoding: [0x0a,0x00,0xd4,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_bf6_f32 v[10:12], v[20:35], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_f32 v[10:12], v[20:35], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd4,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk16_fp6_f32 v[10:12], v[20:35], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_f32 v[10:12], v[20:35], v4, v8 ; encoding: [0x0a,0x00,0xd3,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_fp6_f32 v[10:12], v[20:35], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_f32 v[10:12], v[20:35], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd3,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s index c1d23be..1441f38 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s @@ -886,3 +886,282 @@ v_permlane_idx_gen_b32 v5, v1, exec_hi v_permlane_idx_gen_b32 v5, v1, exec_lo // GFX1250: v_permlane_idx_gen_b32 v5, v1, exec_lo ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xfd,0x00,0x00] + +v_cvt_scalef32_pk8_fp8_bf16 v[10:11], v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_fp8_bf16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xb4,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp8_bf16 v[10:11], v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp8_bf16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb4,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_bf8_bf16 v[10:11], v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_bf8_bf16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xb5,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_bf8_bf16 v[10:11], v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_bf8_bf16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb5,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_fp8_f16 v[10:11], v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_fp8_f16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xc4,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp8_f16 v[10:11], v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp8_f16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xc4,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_bf8_f16 v[10:11], v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_bf8_f16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xc6,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_bf8_f16 v[10:11], v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_bf8_f16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xc6,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[20:27], v8 ; encoding: [0x0a,0x00,0xc3,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xc3,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[20:27], v8 ; encoding: [0x0a,0x00,0xc5,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xc5,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_fp4_f32 v10, v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk8_fp4_f32 v10, v[20:27], v8 ; encoding: [0x0a,0x00,0xb0,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp4_f32 v10, v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp4_f32 v10, v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xb0,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_fp4_f16 v10, v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_fp4_f16 v10, v[20:23], v8 ; encoding: [0x0a,0x00,0xb3,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp4_f16 v10, v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp4_f16 v10, v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb3,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk8_fp4_bf16 v10, v[20:23], v8 +// GFX1250: v_cvt_scalef32_pk8_fp4_bf16 v10, v[20:23], v8 ; encoding: [0x0a,0x00,0xb8,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk8_fp4_bf16 v10, v[20:23], 100.0 +// GFX1250: v_cvt_scalef32_pk8_fp4_bf16 v10, v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb8,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp8_bf16 v[10:11], v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_bf16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xc0,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp8_bf16 v[10:11], v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_bf16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xc0,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_bf8_bf16 v[10:11], v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_bf16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xc2,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_bf8_bf16 v[10:11], v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_bf16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xc2,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp8_f16 v[10:11], v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_f16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xbf,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp8_f16 v[10:11], v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_f16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xbf,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_bf8_f16 v[10:11], v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_f16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xc1,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_bf8_f16 v[10:11], v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_f16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xc1,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0x98,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0x98,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0x99,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0x99,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[20:27], v4, v8 ; encoding: [0x0a,0x00,0x97,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0x97,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp4_f16 v10, v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_f16 v10, v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xb9,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp4_f16 v10, v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_f16 v10, v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xb9,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk8_fp4_bf16 v10, v[20:23], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_bf16 v10, v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xbc,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk8_fp4_bf16 v10, v[20:23], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk8_fp4_bf16 v10, v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xbc,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_perm_pk16_b4_u4 v[2:3], v4, v5, v[6:7] +// GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, v5, v[6:7] ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0b,0x1a,0x04] + +v_perm_pk16_b4_u4 v[2:3], v4, ttmp5, s[6:7] +// GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, ttmp5, s[6:7] ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0xe3,0x18,0x00] + +v_perm_pk16_b4_u4 v[2:3], s4, v5, v[6:7] +// GFX1250: v_perm_pk16_b4_u4 v[2:3], s4, v5, v[6:7] ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0a,0x1a,0x04] + +v_perm_pk16_b4_u4 v[2:3], v4, v5, 100 +// GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, v5, 0x64 ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0b,0xfe,0x03,0x64,0x00,0x00,0x00] + +v_perm_pk16_b4_u4 v[2:3], v4, v5, 4 +// GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, v5, 4 ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0b,0x12,0x02] + +v_perm_pk16_b6_u4 v[2:4], v4, v[8:9], v[6:7] +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[8:9], v[6:7] ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x11,0x1a,0x04] + +v_perm_pk16_b6_u4 v[2:4], v4, ttmp[4:5], s[6:7] +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, ttmp[4:5], s[6:7] ; encoding: [0x02,0x00,0x42,0xd6,0x04,0xe1,0x18,0x00] + +v_perm_pk16_b6_u4 v[2:4], s4, v[4:5], v[6:7] +// GFX1250: v_perm_pk16_b6_u4 v[2:4], s4, v[4:5], v[6:7] ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x08,0x1a,0x04] + +v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 100 +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 0x64 ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x09,0xfe,0x03,0x64,0x00,0x00,0x00] + +v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 4 +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 4 ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x09,0x12,0x02] + +v_perm_pk16_b8_u4 v[2:5], v[4:5], v[8:9], v[6:7] +// GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], v[8:9], v[6:7] ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x11,0x1a,0x04] + +v_perm_pk16_b8_u4 v[2:5], v[4:5], ttmp[4:5], s[6:7] +// GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], ttmp[4:5], s[6:7] ; encoding: [0x02,0x00,0x43,0xd6,0x04,0xe1,0x18,0x00] + +v_perm_pk16_b8_u4 v[2:5], s[4:5], v[4:5], v[6:7] +// GFX1250: v_perm_pk16_b8_u4 v[2:5], s[4:5], v[4:5], v[6:7] ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x08,0x1a,0x04] + +v_perm_pk16_b8_u4 v[2:5], v[4:5], v[4:5], 100 +// GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], v[4:5], 0x64 ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x09,0xfe,0x03,0x64,0x00,0x00,0x00] + +v_perm_pk16_b8_u4 v[2:5], v[4:5], v[4:5], 4 +// GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], v[4:5], 4 ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x09,0x12,0x02] + +v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xcb,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xcb,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], v8 scale_sel:1 +// GFX1250: v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], v8 scale_sel:1 ; encoding: [0x0a,0x08,0xcb,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xca,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xca,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], v8 scale_sel:2 +// GFX1250: v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], v8 scale_sel:2 ; encoding: [0x0a,0x10,0xca,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xc8,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xc8,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], v8 scale_sel:3 +// GFX1250: v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], v8 scale_sel:3 ; encoding: [0x0a,0x18,0xc8,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xc7,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xc7,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], v8 scale_sel:4 +// GFX1250: v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], v8 scale_sel:4 ; encoding: [0x0a,0x20,0xc7,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], v8 ; encoding: [0x0a,0x00,0xc9,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xc9,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], v8 scale_sel:4 +// GFX1250: v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], v8 scale_sel:4 ; encoding: [0x0a,0x20,0xc9,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], v8 +// GFX1250: v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], v8 ; encoding: [0x0a,0x00,0xcc,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], 0xcf00 +// GFX1250: v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xcc,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], v8 scale_sel:5 +// GFX1250: v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], v8 scale_sel:5 ; encoding: [0x0a,0x28,0xcc,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xd2,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xd2,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xd0,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xd0,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_bf6_f32 v[10:12], v[20:35], 100.0 +// GFX1250: v_cvt_scalef32_pk16_bf6_f32 v[10:12], v[20:35], 0x42c80000 ; encoding: [0x0a,0x00,0xce,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_bf6_f32 v[10:12], v[20:35], v8 +// GFX1250: v_cvt_scalef32_pk16_bf6_f32 v[10:12], v[20:35], v8 ; encoding: [0x0a,0x00,0xce,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xd1,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xd1,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], 100.0 +// GFX1250: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xcf,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], v8 +// GFX1250: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xcf,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_pk16_fp6_f32 v[10:12], v[20:35], 100.0 +// GFX1250: v_cvt_scalef32_pk16_fp6_f32 v[10:12], v[20:35], 0x42c80000 ; encoding: [0x0a,0x00,0xcd,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_pk16_fp6_f32 v[10:12], v[20:35], v8 +// GFX1250: v_cvt_scalef32_pk16_fp6_f32 v[10:12], v[20:35], v8 ; encoding: [0x0a,0x00,0xcd,0xd6,0x14,0x11,0x02,0x00] + +v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd8,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd8,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd6,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd6,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd7,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd7,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[20:27], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd5,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[20:27], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd5,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk16_bf6_f32 v[10:12], v[20:35], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_f32 v[10:12], v[20:35], v4, v8 ; encoding: [0x0a,0x00,0xd4,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_bf6_f32 v[10:12], v[20:35], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_bf6_f32 v[10:12], v[20:35], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd4,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +v_cvt_scalef32_sr_pk16_fp6_f32 v[10:12], v[20:35], v4, v8 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_f32 v[10:12], v[20:35], v4, v8 ; encoding: [0x0a,0x00,0xd3,0xd6,0x14,0x09,0x22,0x04] + +v_cvt_scalef32_sr_pk16_fp6_f32 v[10:12], v[20:35], s4, 100.0 +// GFX1250: v_cvt_scalef32_sr_pk16_fp6_f32 v[10:12], v[20:35], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd3,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt index e4968fe..4b44c27 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt @@ -869,6 +869,9 @@ 0x05,0x00,0x72,0xd6,0x01,0xd5,0xf4,0x01 # GFX1250: v_permlane_down_b32 v5, v1, vcc_lo, m0 ; encoding: [0x05,0x00,0x72,0xd6,0x01,0xd5,0xf4,0x01] +0x05,0x00,0x71,0xd6,0x01,0xff,0xa8,0x01 +# GFX1250: v_permlane_up_b32 v5, v1, exec_hi, vcc_lo ; encoding: [0x05,0x00,0x71,0xd6,0x01,0xff,0xa8,0x01] + 0x05,0x00,0x71,0xd6,0x01,0xfd,0xf4,0x03 # GFX1250: v_permlane_up_b32 v5, v1, exec_lo, src_scc ; encoding: [0x05,0x00,0x71,0xd6,0x01,0xfd,0xf4,0x03] @@ -937,3 +940,282 @@ 0x05,0x00,0x14,0xd7,0x01,0xd5,0x00,0x00 # GFX1250: v_permlane_idx_gen_b32 v5, v1, vcc_lo ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xd5,0x00,0x00] + +0x0a,0x00,0xb4,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk8_fp8_bf16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb4,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xb4,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk8_fp8_bf16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xb4,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xb5,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk8_bf8_bf16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb5,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xb5,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk8_bf8_bf16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xb5,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xc4,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk8_fp8_f16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xc4,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xc4,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk8_fp8_f16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xc4,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xc6,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk8_bf8_f16 v[10:11], v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xc6,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xc6,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk8_bf8_f16 v[10:11], v[20:23], v8 ; encoding: [0x0a,0x00,0xc6,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xc3,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xc3,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xc3,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[20:27], v8 ; encoding: [0x0a,0x00,0xc3,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xc5,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xc5,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xc5,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[20:27], v8 ; encoding: [0x0a,0x00,0xc5,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xb0,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk8_fp4_f32 v10, v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xb0,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xb0,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk8_fp4_f32 v10, v[20:27], v8 ; encoding: [0x0a,0x00,0xb0,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xb3,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk8_fp4_f16 v10, v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb3,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xb3,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk8_fp4_f16 v10, v[20:23], v8 ; encoding: [0x0a,0x00,0xb3,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xb8,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk8_fp4_bf16 v10, v[20:23], 0x42c80000 ; encoding: [0x0a,0x00,0xb8,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xb8,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk8_fp4_bf16 v10, v[20:23], v8 ; encoding: [0x0a,0x00,0xb8,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xc2,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk8_bf8_bf16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xc2,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xc2,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk8_bf8_bf16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xc2,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0xc1,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk8_bf8_f16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xc1,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xc1,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk8_bf8_f16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xc1,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0x99,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0x99,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0x99,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0x99,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0xbc,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk8_fp4_bf16 v10, v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xbc,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xbc,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk8_fp4_bf16 v10, v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xbc,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0xb9,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk8_fp4_f16 v10, v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xb9,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xb9,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk8_fp4_f16 v10, v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xb9,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0x97,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0x97,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0x97,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[20:27], v4, v8 ; encoding: [0x0a,0x00,0x97,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0xc0,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk8_fp8_bf16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xc0,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xc0,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk8_fp8_bf16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xc0,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0xbf,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk8_fp8_f16 v[10:11], v[20:23], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xbf,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xbf,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk8_fp8_f16 v[10:11], v[20:23], v4, v8 ; encoding: [0x0a,0x00,0xbf,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0x98,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0x98,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0x98,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0x98,0xd6,0x14,0x09,0x22,0x04] + +0x02,0x00,0x3f,0xd6,0x04,0x0a,0x1a,0x04 +# GFX1250: v_perm_pk16_b4_u4 v[2:3], s4, v5, v[6:7] ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0a,0x1a,0x04] + +0x02,0x00,0x3f,0xd6,0x04,0xe3,0x18,0x00 +# GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, ttmp5, s[6:7] ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0xe3,0x18,0x00] + +0x02,0x00,0x3f,0xd6,0x04,0x0b,0xfe,0x03,0x64,0x00,0x00,0x00 +# GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, v5, 0x64 ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0b,0xfe,0x03,0x64,0x00,0x00,0x00] + +0x02,0x00,0x3f,0xd6,0x04,0x0b,0x12,0x02 +# GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, v5, 4 ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0b,0x12,0x02] + +0x02,0x00,0x3f,0xd6,0x04,0x0b,0x1a,0x04 +# GFX1250: v_perm_pk16_b4_u4 v[2:3], v4, v5, v[6:7] ; encoding: [0x02,0x00,0x3f,0xd6,0x04,0x0b,0x1a,0x04] + +0x02,0x00,0x42,0xd6,0x04,0x08,0x1a,0x04 +# GFX1250: v_perm_pk16_b6_u4 v[2:4], s4, v[4:5], v[6:7] ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x08,0x1a,0x04] + +0x02,0x00,0x42,0xd6,0x04,0xe1,0x18,0x00 +# GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, ttmp[4:5], s[6:7] ; encoding: [0x02,0x00,0x42,0xd6,0x04,0xe1,0x18,0x00] + +0x02,0x00,0x42,0xd6,0x04,0x09,0xfe,0x03,0x64,0x00,0x00,0x00 +# GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 0x64 ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x09,0xfe,0x03,0x64,0x00,0x00,0x00] + +0x02,0x00,0x42,0xd6,0x04,0x09,0x12,0x02 +# GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 4 ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x09,0x12,0x02] + +0x02,0x00,0x42,0xd6,0x04,0x11,0x1a,0x04 +# GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[8:9], v[6:7] ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x11,0x1a,0x04] + +0x02,0x00,0x43,0xd6,0x04,0x08,0x1a,0x04 +# GFX1250: v_perm_pk16_b8_u4 v[2:5], s[4:5], v[4:5], v[6:7] ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x08,0x1a,0x04] + +0x02,0x00,0x43,0xd6,0x04,0xe1,0x18,0x00 +# GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], ttmp[4:5], s[6:7] ; encoding: [0x02,0x00,0x43,0xd6,0x04,0xe1,0x18,0x00] + +0x02,0x00,0x43,0xd6,0x04,0x09,0xfe,0x03,0x64,0x00,0x00,0x00 +# GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], v[4:5], 0x64 ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x09,0xfe,0x03,0x64,0x00,0x00,0x00] + +0x02,0x00,0x43,0xd6,0x04,0x09,0x12,0x02 +# GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], v[4:5], 4 ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x09,0x12,0x02] + +0x02,0x00,0x43,0xd6,0x04,0x11,0x1a,0x04 +# GFX1250: v_perm_pk16_b8_u4 v[2:5], v[4:5], v[8:9], v[6:7] ; encoding: [0x02,0x00,0x43,0xd6,0x04,0x11,0x1a,0x04] + +0x0a,0x00,0xcb,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00 +# GFX1250: v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xcb,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +0x0a,0x00,0xcb,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xcb,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x08,0xcb,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_bf16_bf6 v[10:17], v[20:22], v8 scale_sel:1 ; encoding: [0x0a,0x08,0xcb,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xc8,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00 +# GFX1250: v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xc8,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +0x0a,0x00,0xc8,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xc8,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x18,0xc8,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_bf16_fp6 v[10:17], v[20:22], v8 scale_sel:3 ; encoding: [0x0a,0x18,0xc8,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xca,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00 +# GFX1250: v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xca,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +0x0a,0x00,0xca,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xca,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x10,0xca,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_f16_bf6 v[10:17], v[20:22], v8 scale_sel:2 ; encoding: [0x0a,0x10,0xca,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xc7,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00 +# GFX1250: v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xc7,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +0x0a,0x00,0xc7,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], v8 ; encoding: [0x0a,0x00,0xc7,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x20,0xc7,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_f16_fp6 v[10:17], v[20:22], v8 scale_sel:4 ; encoding: [0x0a,0x20,0xc7,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xcc,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00 +# GFX1250: v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xcc,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +0x0a,0x00,0xcc,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], v8 ; encoding: [0x0a,0x00,0xcc,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x28,0xcc,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_f32_bf6 v[10:25], v[20:22], v8 scale_sel:5 ; encoding: [0x0a,0x28,0xcc,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xc9,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00 +# GFX1250: v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], 0xcf00 ; encoding: [0x0a,0x00,0xc9,0xd6,0x14,0xff,0x01,0x00,0x00,0xcf,0x00,0x00] + +0x0a,0x00,0xc9,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], v8 ; encoding: [0x0a,0x00,0xc9,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x20,0xc9,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scale_pk16_f32_fp6 v[10:25], v[20:22], v8 scale_sel:4 ; encoding: [0x0a,0x20,0xc9,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xd2,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xd2,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xd2,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xd2,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xd0,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xd0,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xd0,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xd0,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xce,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk16_bf6_f32 v[10:12], v[20:35], 0x42c80000 ; encoding: [0x0a,0x00,0xce,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xce,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk16_bf6_f32 v[10:12], v[20:35], v8 ; encoding: [0x0a,0x00,0xce,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xd1,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xd1,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xd1,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xd1,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xcf,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], 0x42c80000 ; encoding: [0x0a,0x00,0xcf,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xcf,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], v8 ; encoding: [0x0a,0x00,0xcf,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xcd,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_pk16_fp6_f32 v[10:12], v[20:35], 0x42c80000 ; encoding: [0x0a,0x00,0xcd,0xd6,0x14,0xff,0x01,0x00,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xcd,0xd6,0x14,0x11,0x02,0x00 +# GFX1250: v_cvt_scalef32_pk16_fp6_f32 v[10:12], v[20:35], v8 ; encoding: [0x0a,0x00,0xcd,0xd6,0x14,0x11,0x02,0x00] + +0x0a,0x00,0xd8,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd8,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xd8,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd8,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0xd6,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd6,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xd6,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd6,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0xd4,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk16_bf6_f32 v[10:12], v[20:35], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd4,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xd4,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk16_bf6_f32 v[10:12], v[20:35], v4, v8 ; encoding: [0x0a,0x00,0xd4,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0xd7,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd7,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xd7,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd7,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0xd5,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[20:27], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd5,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xd5,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[20:27], v4, v8 ; encoding: [0x0a,0x00,0xd5,0xd6,0x14,0x09,0x22,0x04] + +0x0a,0x00,0xd3,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42 +# GFX1250: v_cvt_scalef32_sr_pk16_fp6_f32 v[10:12], v[20:35], s4, 0x42c80000 ; encoding: [0x0a,0x00,0xd3,0xd6,0x14,0x09,0xfc,0x03,0x00,0x00,0xc8,0x42] + +0x0a,0x00,0xd3,0xd6,0x14,0x09,0x22,0x04 +# GFX1250: v_cvt_scalef32_sr_pk16_fp6_f32 v[10:12], v[20:35], v4, v8 ; encoding: [0x0a,0x00,0xd3,0xd6,0x14,0x09,0x22,0x04] diff --git a/llvm/test/MC/ELF/many-instructions.s b/llvm/test/MC/ELF/many-instructions.s new file mode 100644 index 0000000..cbdb2a7 --- /dev/null +++ b/llvm/test/MC/ELF/many-instructions.s @@ -0,0 +1,10 @@ +# REQUIRES: asserts +# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o /dev/null -debug-only=mc-dump + +## Test that encodeInstruction may cause a new fragment to be created. +# CHECK: 0 Data Size:16200 +# CHECK: 16200 Data Size:180 + +.rept 16384/10 +movabsq $foo, %rax +.endr diff --git a/llvm/test/MC/ELF/mc-dump.s b/llvm/test/MC/ELF/mc-dump.s index fd6cf95..51b3ff4 100644 --- a/llvm/test/MC/ELF/mc-dump.s +++ b/llvm/test/MC/ELF/mc-dump.s @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t -debug-only=mc-dump-pre,mc-dump 2>&1 | FileCheck %s --match-full-lines --strict-whitespace +# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t -debug-only=mc-dump-pre,mc-dump -stats 2>&1 | FileCheck %s --match-full-lines --strict-whitespace #CHECK-LABEL:assembler backend - pre-layout # CHECK:MCSection Name:.text @@ -30,6 +30,9 @@ # CHECK-NEXT:5 LEB Size:0+1 [15] Value:.Ltmp0-_start Signed:0 # CHECK:] +# CHECK: 2 assembler - Number of fixup evaluations for relaxation +# CHECK: 8 assembler - Number of fixups + # RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t -debug-only=mc-dump -save-temp-labels -g 2>&1 | FileCheck %s --check-prefix=CHECK2 # CHECK2:5 Data Size:16 [48,8b,04,25,00,00,00,00,48,8b,04,25,00,00,00,00] diff --git a/llvm/test/Transforms/InstCombine/load-cmp.ll b/llvm/test/Transforms/InstCombine/load-cmp.ll index df34e7d..f44d27c 100644 --- a/llvm/test/Transforms/InstCombine/load-cmp.ll +++ b/llvm/test/Transforms/InstCombine/load-cmp.ll @@ -68,7 +68,6 @@ define i1 @test1_noinbounds_as1(i32 %x) { %q = load i16, ptr addrspace(1) %p %r = icmp eq i16 %q, 0 ret i1 %r - } define i1 @test1_noinbounds_as2(i64 %x) { @@ -81,7 +80,17 @@ define i1 @test1_noinbounds_as2(i64 %x) { %q = load i16, ptr addrspace(2) %p %r = icmp eq i16 %q, 0 ret i1 %r +} +define i1 @test1_noarrayty(i32 %X) { +; CHECK-LABEL: @test1_noarrayty( +; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[X:%.*]], 9 +; CHECK-NEXT: ret i1 [[R]] +; + %P = getelementptr inbounds i16, ptr @G16, i32 %X + %Q = load i16, ptr %P + %R = icmp eq i16 %Q, 0 + ret i1 %R } define i1 @test2(i32 %X) { @@ -104,7 +113,17 @@ define i1 @test3(i32 %X) { %Q = load double, ptr %P %R = fcmp oeq double %Q, 1.0 ret i1 %R +} +define i1 @test3_noarrayty(i32 %X) { +; CHECK-LABEL: @test3_noarrayty( +; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[X:%.*]], 1 +; CHECK-NEXT: ret i1 [[R]] +; + %P = getelementptr inbounds double, ptr @GD, i32 %X + %Q = load double, ptr %P + %R = fcmp oeq double %Q, 1.0 + ret i1 %R } define i1 @test4(i32 %X) { @@ -325,6 +344,17 @@ define i1 @test10_struct_arr_noinbounds_i64(i64 %x) { ret i1 %r } +define i1 @test10_struct_arr_noarrayty(i32 %x) { +; CHECK-LABEL: @test10_struct_arr_noarrayty( +; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[X:%.*]], 1 +; CHECK-NEXT: ret i1 [[R]] +; + %p = getelementptr inbounds %Foo, ptr @GStructArr, i32 %x, i32 2 + %q = load i32, ptr %p + %r = icmp eq i32 %q, 9 + ret i1 %r +} + @table = internal constant [2 x ptr] [ptr @g, ptr getelementptr (i8, ptr @g, i64 4)], align 16 @g = external global [2 x i32] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll b/llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll index 7308129..a11896a 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll @@ -100,9 +100,9 @@ define void @simple_memset_tailfold(i32 %val, ptr %ptr, i64 %n) "target-features ; DATA_NO_LANEMASK-NEXT: [[N_RND_UP:%.*]] = add i64 [[UMAX]], [[TMP8]] ; DATA_NO_LANEMASK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP5]] ; DATA_NO_LANEMASK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] -; DATA_NO_LANEMASK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[UMAX]], 1 ; DATA_NO_LANEMASK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64() ; DATA_NO_LANEMASK-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP15]], 4 +; DATA_NO_LANEMASK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[UMAX]], 1 ; DATA_NO_LANEMASK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0 ; DATA_NO_LANEMASK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT5]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer ; DATA_NO_LANEMASK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[VAL:%.*]], i64 0 diff --git a/llvm/test/Transforms/LoopVectorize/single-scalar-cast-minbw.ll b/llvm/test/Transforms/LoopVectorize/single-scalar-cast-minbw.ll index b8da9ac..b6a0346 100644 --- a/llvm/test/Transforms/LoopVectorize/single-scalar-cast-minbw.ll +++ b/llvm/test/Transforms/LoopVectorize/single-scalar-cast-minbw.ll @@ -62,3 +62,76 @@ loop: exit: ret void } + +; Test case for https://github.com/llvm/llvm-project/issues/151392. +define void @single_scalar_cast_stored(ptr %src, ptr %dst, i32 %n) { +; CHECK-LABEL: define void @single_scalar_cast_stored( +; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i32 [[N:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]] +; CHECK: [[VECTOR_MEMCHECK]]: +; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 2 +; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC]], i64 2 +; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP1]] +; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]] +; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]] +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[SRC]], align 2, !alias.scope [[META4:![0-9]+]] +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT]], <4 x i16> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i16> [[BROADCAST_SPLAT]], zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i16> [[BROADCAST_SPLAT]], splat (i16 15) +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i1> [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i16> [[TMP2]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP3]], i16 0, i16 [[TMP4]] +; CHECK-NEXT: store i16 [[TMP5]], ptr [[DST]], align 2, !alias.scope [[META7:![0-9]+]], !noalias [[META4]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 +; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] +; CHECK: [[SCALAR_PH]]: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] +; CHECK-NEXT: [[L:%.*]] = load i16, ptr [[SRC]], align 2 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[L]], 0 +; CHECK-NEXT: [[L_EXT:%.*]] = zext i16 [[L]] to i32 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[L_EXT]], 15 +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 0, i32 [[AND]] +; CHECK-NEXT: [[SEL_TRUNC:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: store i16 [[SEL_TRUNC]], ptr [[DST]], align 2 +; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp ne i32 [[IV_NEXT]], [[N]] +; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP10:![0-9]+]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] + %l = load i16, ptr %src, align 2 + %cmp = icmp eq i16 %l, 0 + %l.ext = zext i16 %l to i32 + %and = and i32 %l.ext, 15 + %sel = select i1 %cmp, i32 0, i32 %and + %sel.trunc = trunc i32 %sel to i16 + store i16 %sel.trunc, ptr %dst, align 2 + %iv.next = add nuw i32 %iv, 1 + %ec = icmp ne i32 %iv.next, %n + br i1 %ec, label %loop, label %exit + +exit: + ret void +} diff --git a/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll b/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll index 3d44317..e118520 100644 --- a/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll +++ b/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll @@ -329,19 +329,14 @@ define i8 @test_early_exit_max_vector_tc_eq_16(ptr dereferenceable(17) %A) nosyn ; VF8UF2: [[VECTOR_PH]]: ; VF8UF2-NEXT: br label %[[VECTOR_BODY:.*]] ; VF8UF2: [[VECTOR_BODY]]: -; VF8UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; VF8UF2-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDEX]] -; VF8UF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i32 8 -; VF8UF2-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1 +; VF8UF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 8 +; VF8UF2-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[A]], align 1 ; VF8UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x i8>, ptr [[TMP1]], align 1 ; VF8UF2-NEXT: [[TMP2:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer ; VF8UF2-NEXT: [[TMP3:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD1]], zeroinitializer -; VF8UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; VF8UF2-NEXT: [[TMP4:%.*]] = or <8 x i1> [[TMP2]], [[TMP3]] ; VF8UF2-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP4]]) -; VF8UF2-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16 -; VF8UF2-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]] -; VF8UF2-NEXT: br i1 [[TMP7]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; VF8UF2-NEXT: br label %[[MIDDLE_SPLIT:.*]] ; VF8UF2: [[MIDDLE_SPLIT]]: ; VF8UF2-NEXT: br i1 [[TMP5]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]] ; VF8UF2: [[MIDDLE_BLOCK]]: @@ -360,7 +355,7 @@ define i8 @test_early_exit_max_vector_tc_eq_16(ptr dereferenceable(17) %A) nosyn ; VF8UF2: [[LOOP_LATCH]]: ; VF8UF2-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1 ; VF8UF2-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 17 -; VF8UF2-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]] +; VF8UF2-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]] ; VF8UF2: [[EXIT]]: ; VF8UF2-NEXT: [[RES:%.*]] = phi i8 [ 0, %[[LOOP_HEADER]] ], [ 1, %[[LOOP_LATCH]] ], [ 0, %[[VECTOR_EARLY_EXIT]] ] ; VF8UF2-NEXT: ret i8 [[RES]] @@ -372,15 +367,10 @@ define i8 @test_early_exit_max_vector_tc_eq_16(ptr dereferenceable(17) %A) nosyn ; VF16UF1: [[VECTOR_PH]]: ; VF16UF1-NEXT: br label %[[VECTOR_BODY:.*]] ; VF16UF1: [[VECTOR_BODY]]: -; VF16UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; VF16UF1-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDEX]] -; VF16UF1-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[TMP0]], align 1 +; VF16UF1-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[A]], align 1 ; VF16UF1-NEXT: [[TMP1:%.*]] = icmp eq <16 x i8> [[WIDE_LOAD]], zeroinitializer -; VF16UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; VF16UF1-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP1]]) -; VF16UF1-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16 -; VF16UF1-NEXT: [[TMP4:%.*]] = or i1 [[TMP2]], [[TMP3]] -; VF16UF1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; VF16UF1-NEXT: br label %[[MIDDLE_SPLIT:.*]] ; VF16UF1: [[MIDDLE_SPLIT]]: ; VF16UF1-NEXT: br i1 [[TMP2]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]] ; VF16UF1: [[MIDDLE_BLOCK]]: @@ -399,7 +389,7 @@ define i8 @test_early_exit_max_vector_tc_eq_16(ptr dereferenceable(17) %A) nosyn ; VF16UF1: [[LOOP_LATCH]]: ; VF16UF1-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1 ; VF16UF1-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 17 -; VF16UF1-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]] +; VF16UF1-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]] ; VF16UF1: [[EXIT]]: ; VF16UF1-NEXT: [[RES:%.*]] = phi i8 [ 0, %[[LOOP_HEADER]] ], [ 1, %[[LOOP_LATCH]] ], [ 0, %[[VECTOR_EARLY_EXIT]] ] ; VF16UF1-NEXT: ret i8 [[RES]] diff --git a/llvm/test/lit.cfg.py b/llvm/test/lit.cfg.py index 2462e00..8c2d1a4 100644 --- a/llvm/test/lit.cfg.py +++ b/llvm/test/lit.cfg.py @@ -117,7 +117,12 @@ lli_args = [] # we don't support COFF in MCJIT well enough for the tests, force ELF format on # Windows. FIXME: the process target triple should be used here, but this is # difficult to obtain on Windows. -if re.search(r"cygwin|windows-gnu|windows-msvc", config.host_triple): +# Cygwin is excluded from this workaround, even though it is COFF, because this +# breaks remote tests due to not having a __register_frame function. The only +# test that succeeds with cygwin-elf but fails with cygwin is +# test/ExecutionEngine/MCJIT/stubs-sm-pic.ll so this test is marked as XFAIL +# for cygwin targets. +if re.search(r"windows-gnu|windows-msvc", config.host_triple): lli_args = ["-mtriple=" + config.host_triple + "-elf"] llc_args = [] @@ -396,10 +401,11 @@ if config.target_triple: else: config.available_features.add("target-byteorder-little-endian") -if sys.platform in ["win32"]: +if sys.platform in ["win32", "cygwin"]: # ExecutionEngine, no weak symbols in COFF. config.available_features.add("uses_COFF") -else: + +if sys.platform not in ["win32"]: # Others/can-execute.txt config.available_features.add("can-execute") @@ -668,7 +674,7 @@ if not hasattr(sys, "getwindowsversion") or sys.getwindowsversion().build >= 170 # .debug_frame is not emitted for targeting Windows x64, aarch64/arm64, AIX, or Apple Silicon Mac. if not re.match( - r"^(x86_64|aarch64|arm64|powerpc|powerpc64).*-(windows-gnu|windows-msvc|aix)", + r"^(x86_64|aarch64|arm64|powerpc|powerpc64).*-(windows-cygnus|windows-gnu|windows-msvc|aix)", config.target_triple, ) and not re.match(r"^arm64(e)?-apple-(macos|darwin)", config.target_triple): config.available_features.add("debug_frame") diff --git a/llvm/test/tools/llvm-ir2vec/embeddings.ll b/llvm/test/tools/llvm-ir2vec/embeddings.ll index 993ea86..f9aa108 100644 --- a/llvm/test/tools/llvm-ir2vec/embeddings.ll +++ b/llvm/test/tools/llvm-ir2vec/embeddings.ll @@ -1,10 +1,10 @@ -; RUN: llvm-ir2vec --mode=embeddings --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-DEFAULT -; RUN: llvm-ir2vec --mode=embeddings --level=func --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-FUNC-LEVEL -; RUN: llvm-ir2vec --mode=embeddings --level=func --function=abc --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-FUNC-LEVEL-ABC -; RUN: not llvm-ir2vec --mode=embeddings --level=func --function=def --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s 2>&1 | FileCheck %s -check-prefix=CHECK-FUNC-DEF -; RUN: llvm-ir2vec --mode=embeddings --level=bb --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-BB-LEVEL -; RUN: llvm-ir2vec --mode=embeddings --level=bb --function=abc_repeat --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-BB-LEVEL-ABC-REPEAT -; RUN: llvm-ir2vec --mode=embeddings --level=inst --function=abc_repeat --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-INST-LEVEL-ABC-REPEAT +; RUN: llvm-ir2vec embeddings --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-DEFAULT +; RUN: llvm-ir2vec embeddings --level=func --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-FUNC-LEVEL +; RUN: llvm-ir2vec embeddings --level=func --function=abc --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-FUNC-LEVEL-ABC +; RUN: not llvm-ir2vec embeddings --level=func --function=def --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s 2>&1 | FileCheck %s -check-prefix=CHECK-FUNC-DEF +; RUN: llvm-ir2vec embeddings --level=bb --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-BB-LEVEL +; RUN: llvm-ir2vec embeddings --level=bb --function=abc_repeat --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-BB-LEVEL-ABC-REPEAT +; RUN: llvm-ir2vec embeddings --level=inst --function=abc_repeat --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s | FileCheck %s -check-prefix=CHECK-INST-LEVEL-ABC-REPEAT define dso_local noundef float @abc(i32 noundef %a, float noundef %b) #0 { entry: diff --git a/llvm/test/tools/llvm-ir2vec/entities.ll b/llvm/test/tools/llvm-ir2vec/entities.ll index 57c3d6f..737044c 100644 --- a/llvm/test/tools/llvm-ir2vec/entities.ll +++ b/llvm/test/tools/llvm-ir2vec/entities.ll @@ -1,4 +1,4 @@ -; RUN: llvm-ir2vec --mode=entities | FileCheck %s +; RUN: llvm-ir2vec entities | FileCheck %s CHECK: 92 CHECK-NEXT: Ret 0 diff --git a/llvm/test/tools/llvm-ir2vec/error-handling.ll b/llvm/test/tools/llvm-ir2vec/error-handling.ll index c23c529..b944ea0 100644 --- a/llvm/test/tools/llvm-ir2vec/error-handling.ll +++ b/llvm/test/tools/llvm-ir2vec/error-handling.ll @@ -1,14 +1,7 @@ ; Test error handling and input validation for llvm-ir2vec tool -; RUN: not llvm-ir2vec --mode=embeddings %s 2>&1 | FileCheck %s -check-prefix=CHECK-NO-VOCAB - -; RUN: not llvm-ir2vec --mode=embeddings --function=nonexistent --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s 2>&1 | FileCheck %s -check-prefix=CHECK-FUNC-NOT-FOUND - -; RUN: llvm-ir2vec --mode=triplets --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json --level=inst %s 2>&1 | FileCheck %s -check-prefix=CHECK-UNUSED-LEVEL -; RUN: llvm-ir2vec --mode=entities --level=inst %s 2>&1 | FileCheck %s -check-prefix=CHECK-UNUSED-LEVEL - -; RUN: llvm-ir2vec --mode=triplets --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json --function=dummy %s 2>&1 | FileCheck %s -check-prefix=CHECK-UNUSED-FUNC -; RUN: llvm-ir2vec --mode=entities --function=dummy %s 2>&1 | FileCheck %s -check-prefix=CHECK-UNUSED-FUNC +; RUN: not llvm-ir2vec embeddings %s 2>&1 | FileCheck %s -check-prefix=CHECK-NO-VOCAB +; RUN: not llvm-ir2vec embeddings --function=nonexistent --ir2vec-vocab-path=%ir2vec_test_vocab_dir/dummy_3D_nonzero_opc_vocab.json %s 2>&1 | FileCheck %s -check-prefix=CHECK-FUNC-NOT-FOUND ; Simple test function for valid IR define i32 @test_func(i32 %a) { @@ -18,5 +11,3 @@ entry: ; CHECK-NO-VOCAB: error: IR2Vec vocabulary file path not specified; You may need to set it using --ir2vec-vocab-path ; CHECK-FUNC-NOT-FOUND: Error: Function 'nonexistent' not found -; CHECK-UNUSED-LEVEL: Warning: --level option is ignored -; CHECK-UNUSED-FUNC: Warning: --function option is ignored diff --git a/llvm/test/tools/llvm-ir2vec/triplets.ll b/llvm/test/tools/llvm-ir2vec/triplets.ll index dcd1dc9..a7fd9e4 100644 --- a/llvm/test/tools/llvm-ir2vec/triplets.ll +++ b/llvm/test/tools/llvm-ir2vec/triplets.ll @@ -1,4 +1,4 @@ -; RUN: llvm-ir2vec --mode=triplets %s | FileCheck %s -check-prefix=TRIPLETS +; RUN: llvm-ir2vec triplets %s | FileCheck %s -check-prefix=TRIPLETS define i32 @simple_add(i32 %a, i32 %b) { entry: diff --git a/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp b/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp index f6ed94b..8e17a4a 100644 --- a/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp +++ b/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp @@ -9,22 +9,22 @@ /// \file /// This file implements the IR2Vec embedding generation tool. /// -/// This tool provides three main modes: +/// This tool provides three main subcommands: /// -/// 1. Triplet Generation Mode (--mode=triplets): +/// 1. Triplet Generation (triplets): /// Generates numeric triplets (head, tail, relation) for vocabulary /// training. Output format: MAX_RELATION=N header followed by /// head\ttail\trelation lines. Relations: 0=Type, 1=Next, 2+=Arg0,Arg1,... -/// Usage: llvm-ir2vec --mode=triplets input.bc -o train2id.txt +/// Usage: llvm-ir2vec triplets input.bc -o train2id.txt /// -/// 2. Entities Generation Mode (--mode=entities): +/// 2. Entity Mappings (entities): /// Generates entity mappings for vocabulary training. /// Output format: <total_entities> header followed by entity\tid lines. -/// Usage: llvm-ir2vec --mode=entities input.bc -o entity2id.txt +/// Usage: llvm-ir2vec entities input.bc -o entity2id.txt /// -/// 3. Embedding Generation Mode (--mode=embeddings): +/// 3. Embedding Generation (embeddings): /// Generates IR2Vec embeddings using a trained vocabulary. -/// Usage: llvm-ir2vec --mode=embeddings --ir2vec-vocab-path=vocab.json +/// Usage: llvm-ir2vec embeddings --ir2vec-vocab-path=vocab.json /// --level=func input.bc -o embeddings.txt Levels: --level=inst /// (instructions), --level=bb (basic blocks), --level=func (functions) /// (See IR2Vec.cpp for more embedding generation options) @@ -55,36 +55,33 @@ namespace ir2vec { static cl::OptionCategory IR2VecToolCategory("IR2Vec Tool Options"); +// Subcommands +static cl::SubCommand + TripletsSubCmd("triplets", "Generate triplets for vocabulary training"); +static cl::SubCommand + EntitiesSubCmd("entities", + "Generate entity mappings for vocabulary training"); +static cl::SubCommand + EmbeddingsSubCmd("embeddings", + "Generate embeddings using trained vocabulary"); + +// Common options static cl::opt<std::string> InputFilename(cl::Positional, cl::desc("<input bitcode file or '-' for stdin>"), - cl::init("-"), cl::cat(IR2VecToolCategory)); + cl::init("-"), cl::sub(TripletsSubCmd), + cl::sub(EmbeddingsSubCmd), cl::cat(IR2VecToolCategory)); static cl::opt<std::string> OutputFilename("o", cl::desc("Output filename"), cl::value_desc("filename"), cl::init("-"), cl::cat(IR2VecToolCategory)); -enum ToolMode { - TripletMode, // Generate triplets for vocabulary training - EntityMode, // Generate entity mappings for vocabulary training - EmbeddingMode // Generate embeddings using trained vocabulary -}; - -static cl::opt<ToolMode> Mode( - "mode", cl::desc("Tool operation mode:"), - cl::values(clEnumValN(TripletMode, "triplets", - "Generate triplets for vocabulary training"), - clEnumValN(EntityMode, "entities", - "Generate entity mappings for vocabulary training"), - clEnumValN(EmbeddingMode, "embeddings", - "Generate embeddings using trained vocabulary")), - cl::init(EmbeddingMode), cl::cat(IR2VecToolCategory)); - +// Embedding-specific options static cl::opt<std::string> FunctionName("function", cl::desc("Process specific function only"), cl::value_desc("name"), cl::Optional, cl::init(""), - cl::cat(IR2VecToolCategory)); + cl::sub(EmbeddingsSubCmd), cl::cat(IR2VecToolCategory)); enum EmbeddingLevel { InstructionLevel, // Generate instruction-level embeddings @@ -93,14 +90,15 @@ enum EmbeddingLevel { }; static cl::opt<EmbeddingLevel> - Level("level", cl::desc("Embedding generation level (for embedding mode):"), + Level("level", cl::desc("Embedding generation level:"), cl::values(clEnumValN(InstructionLevel, "inst", "Generate instruction-level embeddings"), clEnumValN(BasicBlockLevel, "bb", "Generate basic block-level embeddings"), clEnumValN(FunctionLevel, "func", "Generate function-level embeddings")), - cl::init(FunctionLevel), cl::cat(IR2VecToolCategory)); + cl::init(FunctionLevel), cl::sub(EmbeddingsSubCmd), + cl::cat(IR2VecToolCategory)); namespace { @@ -291,7 +289,7 @@ public: Error processModule(Module &M, raw_ostream &OS) { IR2VecTool Tool(M); - if (Mode == EmbeddingMode) { + if (EmbeddingsSubCmd) { // Initialize vocabulary for embedding generation // Note: Requires --ir2vec-vocab-path option to be set auto VocabStatus = Tool.initializeVocabulary(); @@ -311,6 +309,7 @@ Error processModule(Module &M, raw_ostream &OS) { Tool.generateEmbeddings(OS); } } else { + // Both triplets and entities use triplet generation Tool.generateTriplets(OS); } return Error::success(); @@ -334,14 +333,6 @@ int main(int argc, char **argv) { "See https://llvm.org/docs/CommandGuide/llvm-ir2vec.html for more " "information.\n"); - // Validate command line options - if (Mode != EmbeddingMode) { - if (Level.getNumOccurrences() > 0) - errs() << "Warning: --level option is ignored\n"; - if (FunctionName.getNumOccurrences() > 0) - errs() << "Warning: --function option is ignored\n"; - } - std::error_code EC; raw_fd_ostream OS(OutputFilename, EC); if (EC) { @@ -349,7 +340,7 @@ int main(int argc, char **argv) { return 1; } - if (Mode == EntityMode) { + if (EntitiesSubCmd) { // Just dump entity mappings without processing any IR IR2VecTool::generateEntityMappings(OS); return 0; diff --git a/llvm/tools/llvm-objdump/COFFDump.cpp b/llvm/tools/llvm-objdump/COFFDump.cpp index b22c9a4..de82561 100644 --- a/llvm/tools/llvm-objdump/COFFDump.cpp +++ b/llvm/tools/llvm-objdump/COFFDump.cpp @@ -187,7 +187,7 @@ void COFFDumper::printPEHeader(const PEHeader &Hdr) const { Size = Data->Size; } outs() << format("Entry %x ", I) << formatAddr(Addr) - << format(" %08x %s\n", uint32_t(Size), DirName[I]); + << format(" %08x %s\n", Size, DirName[I]); } } diff --git a/llvm/unittests/Frontend/CMakeLists.txt b/llvm/unittests/Frontend/CMakeLists.txt index 6e4ba5d..cd7abb7 100644 --- a/llvm/unittests/Frontend/CMakeLists.txt +++ b/llvm/unittests/Frontend/CMakeLists.txt @@ -2,6 +2,7 @@ set(LLVM_LINK_COMPONENTS Analysis Core FrontendHLSL + FrontendOffloading FrontendOpenACC FrontendOpenMP Passes @@ -22,6 +23,7 @@ add_llvm_unittest(LLVMFrontendTests OpenMPDecompositionTest.cpp OpenMPDirectiveNameTest.cpp OpenMPDirectiveNameParserTest.cpp + PropertySetRegistryTest.cpp DEPENDS acc_gen diff --git a/llvm/unittests/Frontend/PropertySetRegistryTest.cpp b/llvm/unittests/Frontend/PropertySetRegistryTest.cpp new file mode 100644 index 0000000..4c1cdb31 --- /dev/null +++ b/llvm/unittests/Frontend/PropertySetRegistryTest.cpp @@ -0,0 +1,76 @@ +//===- llvm/unittest/Frontend/PropertySetRegistry.cpp ---------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/SmallVector.h" +#include "llvm/Frontend/Offloading/PropertySet.h" +#include "llvm/Support/MemoryBuffer.h" +#include "gtest/gtest.h" + +using namespace llvm::offloading; +using namespace llvm; + +void checkSerialization(const PropertySetRegistry &PSR) { + SmallString<0> Serialized; + raw_svector_ostream OS(Serialized); + writePropertiesToJSON(PSR, OS); + auto PSR2 = readPropertiesFromJSON({Serialized, ""}); + ASSERT_EQ("", toString(PSR2.takeError())); + EXPECT_EQ(PSR, *PSR2); +} + +TEST(PropertySetRegistryTest, PropertySetRegistry) { + PropertySetRegistry PSR; + checkSerialization(PSR); + + PSR["Category1"]["Prop1"] = 42U; + PSR["Category1"]["Prop2"] = ByteArray(StringRef("Hello").bytes()); + PSR["Category2"]["A"] = ByteArray{0, 4, 16, 32, 255}; + checkSerialization(PSR); + + PSR = PropertySetRegistry(); + PSR["ABC"]["empty_array"] = ByteArray(); + PSR["ABC"]["max_val"] = std::numeric_limits<uint32_t>::max(); + checkSerialization(PSR); +} + +TEST(PropertySetRegistryTest, IllFormedJSON) { + SmallString<0> Input; + + // Invalid json + Input = "{ invalid }"; + auto Res = readPropertiesFromJSON({Input, ""}); + EXPECT_NE("", toString(Res.takeError())); + + Input = ""; + Res = readPropertiesFromJSON({Input, ""}); + EXPECT_NE("", toString(Res.takeError())); + + // Not a JSON object + Input = "[1, 2, 3]"; + Res = readPropertiesFromJSON({Input, ""}); + EXPECT_NE("", toString(Res.takeError())); + + // Property set not an object + Input = R"({ "Category": 42 })"; + Res = readPropertiesFromJSON({Input, ""}); + EXPECT_NE("", toString(Res.takeError())); + + // Property value has non string/non-integer type + Input = R"({ "Category": { "Prop": [1, 2, 3] } })"; + Res = readPropertiesFromJSON({Input, ""}); + EXPECT_NE("", toString(Res.takeError())); + + // Property value is an invalid base64 string + Input = R"({ "Category": { "Prop": ";" } })"; + Res = readPropertiesFromJSON({Input, ""}); + EXPECT_NE("", toString(Res.takeError())); + + Input = R"({ "Category": { "Prop": "!@#$" } })"; + Res = readPropertiesFromJSON({Input, ""}); + EXPECT_NE("", toString(Res.takeError())); +} diff --git a/llvm/utils/gn/secondary/llvm/lib/Frontend/Offloading/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Frontend/Offloading/BUILD.gn index 1c839b1..33d4246 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Frontend/Offloading/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Frontend/Offloading/BUILD.gn @@ -8,6 +8,7 @@ static_library("Offloading") { ] sources = [ "OffloadWrapper.cpp", + "PropertySet.cpp", "Utility.cpp", ] } diff --git a/llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn index 6890c48..12f7d65 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn @@ -24,5 +24,6 @@ unittest("LLVMFrontendTests") { "OpenMPDirectiveNameTest.cpp", "OpenMPIRBuilderTest.cpp", "OpenMPParsingTest.cpp", + "PropertySetRegistryTest.cpp", ] } diff --git a/llvm/utils/mlgo-utils/IR2Vec/generateTriplets.py b/llvm/utils/mlgo-utils/IR2Vec/generateTriplets.py index c48503e..80ac4c6 100644 --- a/llvm/utils/mlgo-utils/IR2Vec/generateTriplets.py +++ b/llvm/utils/mlgo-utils/IR2Vec/generateTriplets.py @@ -124,7 +124,7 @@ class IR2VecTripletGenerator: # Run llvm-ir2vec with opt's output as input ir2vec_proc = subprocess.Popen( - [self.ir2vec_binary, "--mode=triplets", "-", "-o", "-"], + [self.ir2vec_binary, "triplets", "-", "-o", "-"], stdin=opt_proc.stdout, stdout=subprocess.PIPE, stderr=subprocess.PIPE, @@ -223,7 +223,7 @@ class IR2VecTripletGenerator: def _generate_entity2id(self, output_file: Path) -> None: """Generate entity2id.txt using llvm-ir2vec""" subprocess.run( - [str(self.ir2vec_binary), "--mode=entities", "-o", str(output_file)], + [str(self.ir2vec_binary), "entities", "-o", str(output_file)], check=True, capture_output=True, ) diff --git a/mlir/include/mlir/Dialect/Quant/IR/QuantTypes.h b/mlir/include/mlir/Dialect/Quant/IR/QuantTypes.h index 44062fe..34f47a1 100644 --- a/mlir/include/mlir/Dialect/Quant/IR/QuantTypes.h +++ b/mlir/include/mlir/Dialect/Quant/IR/QuantTypes.h @@ -143,9 +143,11 @@ public: /// Casts from a type based on the storageType to a corresponding type based /// on this type (returns nullptr if the cast is not valid). /// Examples: + /// `candidate type` -> `return type` /// i8 -> !quant.uniform<i8:f32, 1.0> /// tensor<4xi8> -> tensor<4x!quant.uniform<i8:f32, 1.0}>> /// vector<4xi8> -> vector<4x!quant.uniform<i8:f32, 1.0>> + /// It is assumed above that this type's quantization is `<i8:f32, 1.0>`. Type castFromStorageType(Type candidateType); /// Casts from a type based on a QuantizedType to a corresponding type based diff --git a/mlir/lib/Dialect/Quant/IR/QuantTypes.cpp b/mlir/lib/Dialect/Quant/IR/QuantTypes.cpp index 8122c4d..b222779 100644 --- a/mlir/lib/Dialect/Quant/IR/QuantTypes.cpp +++ b/mlir/lib/Dialect/Quant/IR/QuantTypes.cpp @@ -127,7 +127,7 @@ QuantizedType::getQuantizedElementType(Type primitiveOrContainerType) { Type QuantizedType::castFromStorageType(Type candidateType) { if (candidateType == getStorageType()) { - // i.e. i32 -> quant<"uniform[i8:f32]{1.0}"> + // i.e. i8 -> quant<"uniform[i8:f32]{1.0}"> return *this; } if (llvm::isa<RankedTensorType>(candidateType)) { @@ -137,11 +137,11 @@ Type QuantizedType::castFromStorageType(Type candidateType) { getStorageType()); } if (llvm::isa<UnrankedTensorType>(candidateType)) { - // i.e. tensor<i8> -> tensor<!quant<"uniform[i8:f32]{1.0}">> + // i.e. tensor<xi8> -> tensor<x!quant<"uniform[i8:f32]{1.0}">> return UnrankedTensorType::get(getStorageType()); } if (llvm::isa<VectorType>(candidateType)) { - // i.e. tensor<4xi8> -> tensor<4x!quant<"uniform[i8:f32]{1.0}">> + // i.e. vector<4xi8> -> vector<4x!quant<"uniform[i8:f32]{1.0}">> return VectorType::get(llvm::cast<VectorType>(candidateType).getShape(), getStorageType()); } diff --git a/mlir/test/Transforms/test-legalizer-full-rollback.mlir b/mlir/test/Transforms/test-legalizer-full-rollback.mlir new file mode 100644 index 0000000..c61847b --- /dev/null +++ b/mlir/test/Transforms/test-legalizer-full-rollback.mlir @@ -0,0 +1,60 @@ +// RUN: mlir-opt -allow-unregistered-dialect -test-legalize-patterns="test-legalize-mode=full" -split-input-file -verify-diagnostics %s | FileCheck %s + +// Test that region inlining can be properly undone. + +// CHECK-LABEL: func @test_undo_region_inline() { +// CHECK: "test.region"() ({ +// CHECK: ^{{.*}}(%[[arg0:.*]]: i64): +// CHECK: cf.br ^[[bb1:.*]](%[[arg0]] : i64) +// CHECK: ^[[bb1]](%[[arg1:.*]]: i64): +// CHECK: "test.invalid"(%[[arg1]]) : (i64) -> () +// CHECK: }) : () -> () +// CHECK: "test.return"() : () -> () +// CHECK: } + +// expected-remark@+1 {{applyFullConversion failed}} +builtin.module { +func.func @test_undo_region_inline() { + "test.region"() ({ + ^bb1(%i0: i64): + // expected-error@+1 {{failed to legalize operation 'cf.br'}} + cf.br ^bb2(%i0 : i64) + ^bb2(%i1: i64): + "test.invalid"(%i1) : (i64) -> () + }) {} : () -> () + + "test.return"() : () -> () +} +} + +// ----- + +// Test that multiple block erases can be properly undone. + +// CHECK-LABEL: func @test_undo_block_erase() { +// CHECK: "test.region"() ({ +// CHECK: ^{{.*}}(%[[arg0:.*]]: i64): +// CHECK: cf.br ^[[bb2:.*]](%[[arg0]] : i64) +// CHECK: ^[[bb1:.*]](%[[arg1:.*]]: i64): +// CHECK: "test.invalid"(%[[arg1]]) : (i64) -> () +// CHECK: ^[[bb2]](%[[arg2:.*]]: i64): +// CHECK: cf.br ^[[bb1]](%[[arg2]] : i64) +// CHECK: }) {legalizer.erase_old_blocks, legalizer.should_clone} : () -> () +// CHECK: "test.return"() : () -> () +// CHECK: } + +// expected-remark@+1 {{applyFullConversion failed}} +builtin.module { +func.func @test_undo_block_erase() { + // expected-error@+1 {{failed to legalize operation 'test.region'}} + "test.region"() ({ + ^bb1(%i0: i64): + cf.br ^bb3(%i0 : i64) + ^bb2(%i1: i64): + "test.invalid"(%i1) : (i64) -> () + ^bb3(%i2: i64): + cf.br ^bb2(%i2 : i64) + }) {legalizer.should_clone, legalizer.erase_old_blocks} : () -> () + "test.return"() : () -> () +} +} diff --git a/mlir/test/Transforms/test-legalizer-full.mlir b/mlir/test/Transforms/test-legalizer-full.mlir index dcd0172..42cec68 100644 --- a/mlir/test/Transforms/test-legalizer-full.mlir +++ b/mlir/test/Transforms/test-legalizer-full.mlir @@ -9,6 +9,8 @@ func.func @multi_level_mapping() { "test.return"() : () -> () } +// ----- + // Test that operations that are erased don't need to be legalized. // CHECK-LABEL: func @dropped_region_with_illegal_ops func.func @dropped_region_with_illegal_ops() { @@ -19,6 +21,9 @@ func.func @dropped_region_with_illegal_ops() { }) : () -> () "test.return"() : () -> () } + +// ----- + // CHECK-LABEL: func @replace_non_root_illegal_op func.func @replace_non_root_illegal_op() { // CHECK-NEXT: "test.legal_op_b" @@ -30,15 +35,20 @@ func.func @replace_non_root_illegal_op() { // ----- // Test that children of recursively legal operations are ignored. + +// CHECK-LABEL: func @recursively_legal_invalid_op func.func @recursively_legal_invalid_op() { /// Operation that is statically legal. builtin.module attributes {test.recursively_legal} { + // CHECK: "test.illegal_op_f" %ignored = "test.illegal_op_f"() : () -> (i32) } /// Operation that is dynamically legal, i.e. the function has a pattern /// applied to legalize the argument type before it becomes recursively legal. builtin.module { + // CHECK: func @dynamic_func(%{{.*}}: f64) func.func @dynamic_func(%arg: i64) attributes {test.recursively_legal} { + // CHECK: "test.illegal_op_f" %ignored = "test.illegal_op_f"() : () -> (i32) "test.return"() : () -> () } @@ -52,25 +62,6 @@ func.func @recursively_legal_invalid_op() { // expected-remark@+1 {{applyFullConversion failed}} builtin.module { - // Test that region cloning can be properly undone. - func.func @test_undo_region_clone() { - "test.region"() ({ - ^bb1(%i0: i64): - "test.invalid"(%i0) : (i64) -> () - }) {legalizer.should_clone} : () -> () - - // expected-error@+1 {{failed to legalize operation 'test.illegal_op_f'}} - %ignored = "test.illegal_op_f"() : () -> (i32) - "test.return"() : () -> () - } - -} - -// ----- - -// expected-remark@+1 {{applyFullConversion failed}} -builtin.module { - // Test that unknown operations can be dynamically legal. func.func @test_unknown_dynamically_legal() { "foo.unknown_op"() {test.dynamically_legal} : () -> () @@ -81,58 +72,3 @@ builtin.module { } } - -// ----- - -// expected-remark@+1 {{applyFullConversion failed}} -builtin.module { - - // Test that region inlining can be properly undone. - func.func @test_undo_region_inline() { - "test.region"() ({ - ^bb1(%i0: i64): - // expected-error@+1 {{failed to legalize operation 'cf.br'}} - cf.br ^bb2(%i0 : i64) - ^bb2(%i1: i64): - "test.invalid"(%i1) : (i64) -> () - }) {} : () -> () - - "test.return"() : () -> () - } - -} - -// ----- - -// expected-remark@+1 {{applyFullConversion failed}} -builtin.module { - - // Test that multiple block erases can be properly undone. - func.func @test_undo_block_erase() { - // expected-error@+1 {{failed to legalize operation 'test.region'}} - "test.region"() ({ - ^bb1(%i0: i64): - cf.br ^bb3(%i0 : i64) - ^bb2(%i1: i64): - "test.invalid"(%i1) : (i64) -> () - ^bb3(%i2: i64): - cf.br ^bb2(%i2 : i64) - }) {legalizer.should_clone, legalizer.erase_old_blocks} : () -> () - - "test.return"() : () -> () - } - -} - -// ----- - -// expected-remark@+1 {{applyFullConversion failed}} -builtin.module { - - func.func @create_unregistered_op_in_pattern() -> i32 { - // expected-error@+1 {{failed to legalize operation 'test.illegal_op_g'}} - %0 = "test.illegal_op_g"() : () -> (i32) - "test.return"(%0) : (i32) -> () - } - -} diff --git a/mlir/test/Transforms/test-legalizer-rollback.mlir b/mlir/test/Transforms/test-legalizer-rollback.mlir new file mode 100644 index 0000000..460911f --- /dev/null +++ b/mlir/test/Transforms/test-legalizer-rollback.mlir @@ -0,0 +1,163 @@ +// RUN: mlir-opt -allow-unregistered-dialect -split-input-file -test-legalize-patterns -verify-diagnostics -profile-actions-to=- %s | FileCheck %s + +// expected-remark@+1 {{applyPartialConversion failed}} +module { +func.func @fail_to_convert_illegal_op_in_region() { + // expected-error@+1 {{failed to legalize operation 'test.region_builder'}} + "test.region_builder"() : () -> () + return +} +} + +// ----- + +// Check that the entry block arguments of a region are untouched in the case +// of failure. + +// expected-remark@+1 {{applyPartialConversion failed}} +module { +func.func @fail_to_convert_region() { + // CHECK: "test.region" + // CHECK-NEXT: ^bb{{.*}}(%{{.*}}: i64): + "test.region"() ({ + ^bb1(%i0: i64): + // expected-error@+1 {{failed to legalize operation 'test.region_builder'}} + "test.region_builder"() : () -> () + "test.valid"() : () -> () + }) : () -> () + return +} +} + +// ----- + +// CHECK-LABEL: @create_illegal_block +func.func @create_illegal_block() { + // Check that we can undo block creation, i.e. that the block was removed. + // CHECK: test.create_illegal_block + // CHECK-NOT: ^{{.*}}(%{{.*}}: i32, %{{.*}}: i32): + // expected-remark@+1 {{op 'test.create_illegal_block' is not legalizable}} + "test.create_illegal_block"() : () -> () + + // expected-remark@+1 {{op 'func.return' is not legalizable}} + return +} + +// ----- + +// CHECK-LABEL: @undo_block_arg_replace +// expected-remark@+1{{applyPartialConversion failed}} +module { +func.func @undo_block_arg_replace() { + // expected-error@+1{{failed to legalize operation 'test.block_arg_replace' that was explicitly marked illegal}} + "test.block_arg_replace"() ({ + ^bb0(%arg0: i32, %arg1: i16): + // CHECK: ^bb0(%[[ARG0:.*]]: i32, %[[ARG1:.*]]: i16): + // CHECK-NEXT: "test.return"(%[[ARG0]]) : (i32) + + "test.return"(%arg0) : (i32) -> () + }) {trigger_rollback} : () -> () + return +} +} + +// ----- + +// The op in this function is rewritten to itself (and thus remains illegal) by +// a pattern that removes its second block after adding an operation into it. +// Check that we can undo block removal successfully. +// CHECK-LABEL: @undo_block_erase +func.func @undo_block_erase() { + // CHECK: test.undo_block_erase + "test.undo_block_erase"() ({ + // expected-remark@-1 {{not legalizable}} + // CHECK: "unregistered.return"()[^[[BB:.*]]] + "unregistered.return"()[^bb1] : () -> () + // expected-remark@-1 {{not legalizable}} + // CHECK: ^[[BB]] + ^bb1: + // CHECK: unregistered.return + "unregistered.return"() : () -> () + // expected-remark@-1 {{not legalizable}} + }) : () -> () +} + +// ----- + +// The op in this function is attempted to be rewritten to another illegal op +// with an attached region containing an invalid terminator. The terminator is +// created before the parent op. The deletion should not crash when deleting +// created ops in the inverse order, i.e. deleting the parent op and then the +// child op. +// CHECK-LABEL: @undo_child_created_before_parent +func.func @undo_child_created_before_parent() { + // expected-remark@+1 {{is not legalizable}} + "test.illegal_op_with_region_anchor"() : () -> () + // expected-remark@+1 {{op 'func.return' is not legalizable}} + return +} + +// ----- + +// expected-remark@+1 {{applyPartialConversion failed}} +builtin.module { +func.func @create_unregistered_op_in_pattern() -> i32 { + // expected-error@+1 {{failed to legalize operation 'test.illegal_op_g'}} + %0 = "test.illegal_op_g"() : () -> (i32) + "test.return"(%0) : (i32) -> () +} +} + +// ----- + +// CHECK-LABEL: func @test_move_op_before_rollback() +func.func @test_move_op_before_rollback() { + // CHECK: "test.one_region_op"() + // CHECK: "test.hoist_me"() + "test.one_region_op"() ({ + // expected-remark @below{{'test.hoist_me' is not legalizable}} + %0 = "test.hoist_me"() : () -> (i32) + "test.valid"(%0) : (i32) -> () + }) : () -> () + "test.return"() : () -> () +} + +// ----- + +// CHECK-LABEL: func @test_properties_rollback() +func.func @test_properties_rollback() { + // CHECK: test.with_properties a = 32, + // expected-remark @below{{op 'test.with_properties' is not legalizable}} + test.with_properties + a = 32, b = "foo", c = "bar", flag = true, array = [1, 2, 3, 4], array32 = [5, 6] + {modify_inplace} + "test.return"() : () -> () +} + +// ----- + +// expected-remark@+1 {{applyPartialConversion failed}} +builtin.module { +// Test that region cloning can be properly undone. +func.func @test_undo_region_clone() { + "test.region"() ({ + ^bb1(%i0: i64): + "test.invalid"(%i0) : (i64) -> () + }) {legalizer.should_clone} : () -> () + + // expected-error@+1 {{failed to legalize operation 'test.illegal_op_f'}} + %ignored = "test.illegal_op_f"() : () -> (i32) + "test.return"() : () -> () +} +} + +// ----- + +// expected-remark@+1 {{applyPartialConversion failed}} +builtin.module { +func.func @create_unregistered_op_in_pattern() -> i32 { + // expected-error@+1 {{failed to legalize operation 'test.illegal_op_g'}} + %0 = "test.illegal_op_g"() : () -> (i32) + "test.return"(%0) : (i32) -> () +} +} diff --git a/mlir/test/Transforms/test-legalizer.mlir b/mlir/test/Transforms/test-legalizer.mlir index 68c863c..e4406e6 100644 --- a/mlir/test/Transforms/test-legalizer.mlir +++ b/mlir/test/Transforms/test-legalizer.mlir @@ -258,73 +258,6 @@ builtin.module { // ----- -// expected-remark@+1 {{applyPartialConversion failed}} -builtin.module { - - func.func @fail_to_convert_illegal_op_in_region() { - // expected-error@+1 {{failed to legalize operation 'test.region_builder'}} - "test.region_builder"() : () -> () - return - } - -} - -// ----- - -// Check that the entry block arguments of a region are untouched in the case -// of failure. - -// expected-remark@+1 {{applyPartialConversion failed}} -builtin.module { - - func.func @fail_to_convert_region() { - // CHECK: "test.region" - // CHECK-NEXT: ^bb{{.*}}(%{{.*}}: i64): - "test.region"() ({ - ^bb1(%i0: i64): - // expected-error@+1 {{failed to legalize operation 'test.region_builder'}} - "test.region_builder"() : () -> () - "test.valid"() : () -> () - }) : () -> () - return - } - -} - -// ----- - -// CHECK-LABEL: @create_illegal_block -func.func @create_illegal_block() { - // Check that we can undo block creation, i.e. that the block was removed. - // CHECK: test.create_illegal_block - // CHECK-NOT: ^{{.*}}(%{{.*}}: i32, %{{.*}}: i32): - // expected-remark@+1 {{op 'test.create_illegal_block' is not legalizable}} - "test.create_illegal_block"() : () -> () - - // expected-remark@+1 {{op 'func.return' is not legalizable}} - return -} - -// ----- - -// CHECK-LABEL: @undo_block_arg_replace -// expected-remark@+1{{applyPartialConversion failed}} -module { -func.func @undo_block_arg_replace() { - // expected-error@+1{{failed to legalize operation 'test.block_arg_replace' that was explicitly marked illegal}} - "test.block_arg_replace"() ({ - ^bb0(%arg0: i32, %arg1: i16): - // CHECK: ^bb0(%[[ARG0:.*]]: i32, %[[ARG1:.*]]: i16): - // CHECK-NEXT: "test.return"(%[[ARG0]]) : (i32) - - "test.return"(%arg0) : (i32) -> () - }) {trigger_rollback} : () -> () - return -} -} - -// ----- - // CHECK-LABEL: @replace_block_arg_1_to_n func.func @replace_block_arg_1_to_n() { // CHECK: "test.block_arg_replace" @@ -340,42 +273,6 @@ func.func @replace_block_arg_1_to_n() { // ----- -// The op in this function is rewritten to itself (and thus remains illegal) by -// a pattern that removes its second block after adding an operation into it. -// Check that we can undo block removal successfully. -// CHECK-LABEL: @undo_block_erase -func.func @undo_block_erase() { - // CHECK: test.undo_block_erase - "test.undo_block_erase"() ({ - // expected-remark@-1 {{not legalizable}} - // CHECK: "unregistered.return"()[^[[BB:.*]]] - "unregistered.return"()[^bb1] : () -> () - // expected-remark@-1 {{not legalizable}} - // CHECK: ^[[BB]] - ^bb1: - // CHECK: unregistered.return - "unregistered.return"() : () -> () - // expected-remark@-1 {{not legalizable}} - }) : () -> () -} - -// ----- - -// The op in this function is attempted to be rewritten to another illegal op -// with an attached region containing an invalid terminator. The terminator is -// created before the parent op. The deletion should not crash when deleting -// created ops in the inverse order, i.e. deleting the parent op and then the -// child op. -// CHECK-LABEL: @undo_child_created_before_parent -func.func @undo_child_created_before_parent() { - // expected-remark@+1 {{is not legalizable}} - "test.illegal_op_with_region_anchor"() : () -> () - // expected-remark@+1 {{op 'func.return' is not legalizable}} - return -} - -// ----- - // Check that a conversion pattern on `test.blackhole` can mark the producer // for deletion. // CHECK-LABEL: @blackhole @@ -388,19 +285,6 @@ func.func @blackhole() { // ----- -// expected-remark@+1 {{applyPartialConversion failed}} -builtin.module { - - func.func @create_unregistered_op_in_pattern() -> i32 { - // expected-error@+1 {{failed to legalize operation 'test.illegal_op_g'}} - %0 = "test.illegal_op_g"() : () -> (i32) - "test.return"(%0) : (i32) -> () - } - -} - -// ----- - module { // CHECK-LABEL: func.func private @callee() -> (f16, f16) func.func private @callee() -> (f32, i24) @@ -423,32 +307,6 @@ func.func @caller() { // ----- -// CHECK-LABEL: func @test_move_op_before_rollback() -func.func @test_move_op_before_rollback() { - // CHECK: "test.one_region_op"() - // CHECK: "test.hoist_me"() - "test.one_region_op"() ({ - // expected-remark @below{{'test.hoist_me' is not legalizable}} - %0 = "test.hoist_me"() : () -> (i32) - "test.valid"(%0) : (i32) -> () - }) : () -> () - "test.return"() : () -> () -} - -// ----- - -// CHECK-LABEL: func @test_properties_rollback() -func.func @test_properties_rollback() { - // CHECK: test.with_properties a = 32, - // expected-remark @below{{op 'test.with_properties' is not legalizable}} - test.with_properties - a = 32, b = "foo", c = "bar", flag = true, array = [1, 2, 3, 4], array32 = [5, 6] - {modify_inplace} - "test.return"() : () -> () -} - -// ----- - // CHECK: func.func @use_of_replaced_bbarg( // CHECK-SAME: %[[arg0:.*]]: f64) // CHECK: "test.valid"(%[[arg0]]) diff --git a/offload/DeviceRTL/src/State.cpp b/offload/DeviceRTL/src/State.cpp index 62b03e7..4753951 100644 --- a/offload/DeviceRTL/src/State.cpp +++ b/offload/DeviceRTL/src/State.cpp @@ -50,7 +50,7 @@ namespace { /// ///{ extern "C" { -#ifdef __AMDGPU__ +#if defined(__AMDGPU__) && !defined(OMPTARGET_HAS_LIBC) [[gnu::weak]] void *malloc(size_t Size) { return allocator::alloc(Size); } [[gnu::weak]] void free(void *Ptr) { allocator::free(Ptr); } diff --git a/offload/unittests/CMakeLists.txt b/offload/unittests/CMakeLists.txt index 6d165ff..24826a1 100644 --- a/offload/unittests/CMakeLists.txt +++ b/offload/unittests/CMakeLists.txt @@ -40,7 +40,7 @@ function(add_offload_test_device_code test_filename test_name) OUTPUT ${output_file} COMMAND ${CMAKE_C_COMPILER} --target=nvptx64-nvidia-cuda -march=${nvptx_arch} - -nogpulib --cuda-path=${CUDA_ROOT} -flto ${ARGN} + -nogpulib --cuda-path=${cuda_path} -flto ${ARGN} ${SRC_PATH} -o ${output_file} DEPENDS ${SRC_PATH} ) diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index aa635ac..5efd012 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -2386,6 +2386,21 @@ libc_support_library( ) libc_support_library( + name = "__support_math_atanhf16", + hdrs = ["src/__support/math/atanhf16.h"], + deps = [ + ":__support_fputil_fenv_impl", + ":__support_fputil_fp_bits", + ":__support_fputil_polyeval", + ":__support_fputil_cast", + ":__support_fputil_except_value_utils", + ":__support_fputil_multiply_add", + ":__support_macros_config", + ":__support_macros_optimization", + ], +) + +libc_support_library( name = "__support_math_erff", hdrs = ["src/__support/math/erff.h"], deps = [ @@ -3014,6 +3029,13 @@ libc_math_function( ], ) +libc_math_function( + name = "atanhf16", + additional_deps = [ + ":__support_math_atanhf16", + ], +) + libc_math_function(name = "canonicalize") libc_math_function(name = "canonicalizef") |