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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-05-20 21:05:47 -0400 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-05-23 13:24:42 -0400 |
| commit | 76e3dd0a490d7da25ccf35c29b3b7ec34908f7d6 (patch) | |
| tree | 88b5e9e5c84da6ac0f005765930094c76348c18d /llvm/lib | |
| parent | 2e82667f60237c32d8a10eb04825ff434a3e474c (diff) | |
| download | llvm-76e3dd0a490d7da25ccf35c29b3b7ec34908f7d6.zip llvm-76e3dd0a490d7da25ccf35c29b3b7ec34908f7d6.tar.gz llvm-76e3dd0a490d7da25ccf35c29b3b7ec34908f7d6.tar.bz2 | |
AMDGPU: Implement isConstantPhysReg
I don't think any of these registers are used in contexts where this
would do anything yet.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 2 |
2 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 9001967..7657a2d 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1849,3 +1849,16 @@ MCPhysReg SIRegisterInfo::get32BitRegister(MCPhysReg Reg) const { return AMDGPU::NoRegister; } + +bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { + switch (PhysReg) { + case AMDGPU::SGPR_NULL: + case AMDGPU::SRC_SHARED_BASE: + case AMDGPU::SRC_PRIVATE_BASE: + case AMDGPU::SRC_SHARED_LIMIT: + case AMDGPU::SRC_PRIVATE_LIMIT: + return true; + default: + return false; + } +} diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 55ea00a2..0b2920b 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -210,6 +210,8 @@ public: return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); } + bool isConstantPhysReg(MCRegister PhysReg) const override; + bool isDivergentRegClass(const TargetRegisterClass *RC) const override { return !isSGPRClass(RC); } |