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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-03 15:26:46 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-05-23 13:24:42 -0400 |
| commit | 2e82667f60237c32d8a10eb04825ff434a3e474c (patch) | |
| tree | 234dd28f793aff347b6f0bf7b0ab4bfa791b4a3e /llvm/lib | |
| parent | 286ca0f7fd6bf26923f3df464e6a74d032f242ea (diff) | |
| download | llvm-2e82667f60237c32d8a10eb04825ff434a3e474c.zip llvm-2e82667f60237c32d8a10eb04825ff434a3e474c.tar.gz llvm-2e82667f60237c32d8a10eb04825ff434a3e474c.tar.bz2 | |
AMDGPU: Define mode register
This should eventually model FP mode constraints as well as the other
special fields it tracks.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 3 |
3 files changed, 10 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 2c3cbd8..36cc0ea 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -715,6 +715,7 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage( case AMDGPU::SRC_PRIVATE_BASE: case AMDGPU::SRC_PRIVATE_LIMIT: case AMDGPU::SGPR_NULL: + case AMDGPU::MODE: continue; case AMDGPU::SRC_POPS_EXITING_WAVE_ID: diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 255a164..9001967 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -205,6 +205,7 @@ MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg( BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); + Reserved.set(AMDGPU::MODE); // EXEC_LO and EXEC_HI could be allocated and used as regular register, but // this seems likely to result in bugs, so I'm marking them as reserved. @@ -1648,15 +1649,16 @@ SIRegisterInfo::getRegClassForReg(const MachineRegisterInfo &MRI, bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI, Register Reg) const { const TargetRegisterClass *RC = getRegClassForReg(MRI, Reg); - assert(RC && "Register class for the reg not found"); - return hasVGPRs(RC); + // Registers without classes are unaddressable, SGPR-like registers. + return RC && hasVGPRs(RC); } bool SIRegisterInfo::isAGPR(const MachineRegisterInfo &MRI, Register Reg) const { const TargetRegisterClass *RC = getRegClassForReg(MRI, Reg); - assert(RC && "Register class for the reg not found"); - return hasAGPRs(RC); + + // Registers without classes are unaddressable, SGPR-like registers. + return RC && hasAGPRs(RC); } bool SIRegisterInfo::shouldCoalesce(MachineInstr *MI, diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 41b1107..ff1f5c4 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -208,6 +208,9 @@ defm SRC_PRIVATE_BASE : SIRegLoHi16<"src_private_base", 237>; defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>; defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>; +// Not addressable +def MODE : SIReg <"mode", 0>; + def LDS_DIRECT : SIReg <"src_lds_direct", 254> { // There is no physical register corresponding to this. This is an // encoding value in a source field, which will ultimately trigger a |