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2023-07-04Updated Ukranian, Romanian and German translations for various sub-directoriesNick Clifton2-747/+679
2023-07-04arc: Update neg<.f> 0,b encodingClaudiu Zissulescu1-1/+1
2023-07-03Change version number to 2.41.50 and regenerate filesNick Clifton3-375/+211
2023-07-03Add markers for the 2.41 branchNick Clifton1-0/+4
2023-07-03opcodes/loongarch: Mark address offset operands of LVZ/LBT insns as suchWANG Xuerui1-28/+28
2023-07-01RISC-V: Add support for the Zvksh ISA extensionChristoph Müllner1-0/+4
2023-07-01RISC-V: Add support for the Zvksed ISA extensionChristoph Müllner1-0/+5
2023-07-01RISC-V: Add support for the Zvknh[a,b] ISA extensionsChristoph Müllner1-0/+5
2023-07-01RISC-V: Add support for the Zvkned ISA extensionChristoph Müllner1-0/+13
2023-07-01RISC-V: Add support for the Zvkg ISA extensionChristoph Müllner1-0/+4
2023-07-01RISC-V: Add support for the Zvbc extensionNathan Huckleberry1-0/+6
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner2-0/+22
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner2-0/+80
2023-06-30LoongArch: gas: Fix code style issuesmengqinggang1-1682/+1681
2023-06-30LoongArch: gas: Add LVZ and LBT instructions supportmengqinggang2-2/+200
2023-06-30LoongArch: Deprecate $v[01], $fv[01] and $x names per specWANG Xuerui1-4/+4
2023-06-30opcodes/loongarch: print unrecognized insn words with the .word directiveWANG Xuerui1-0/+1
2023-06-30opcodes/loongarch: do not print hex notation for signed immediatesWANG Xuerui1-7/+1
2023-06-30opcodes/loongarch: style disassembled address offsets as suchWANG Xuerui2-28/+41
2023-06-30opcodes/loongarch: implement style support in the disassemblerWANG Xuerui2-23/+27
2023-06-30opcodes/loongarch: remove unused codeWANG Xuerui1-35/+0
2023-06-30LoongArch: support disassembling certain pseudo-instructionsWANG Xuerui2-11/+38
2023-06-28aarch64: Remove version dependencies from featuresAndrew Carlotti1-17/+19
2023-06-28LoongArch: gas: Add lsx and lasx instructions supportmengqinggang1-0/+1465
2023-06-27 RISC-V: Support Zicond extensionPhilipp Tomsich1-0/+4
2023-06-25LoongArch: Support referring to FCSRs as $fcsrXFeiyang Chen2-3/+22
2023-06-21x86: fix expansion of %XVJan Beulich1-7/+8
2023-06-16x86: shrink Masking insn attribute to a single bit (boolean)Jan Beulich3-1635/+1627
2023-06-15Add additional missing Allegrex CPU instructionsDavid Guillen Fandos1-14/+24
2023-06-15Add rotation instructions to MIPS Allegrex CPUDavid Guillen Fandos1-7/+7
2023-06-15Add MIPS Allegrex CPU as a MIPS2-based CPUDavid Guillen Fandos2-26/+32
2023-06-15Revert "MIPS: add MT ASE support for micromips32"Maciej W. Rozycki2-68/+1
2023-06-15Revert "MIPS: sync oprand char usage between mips and micromips"Maciej W. Rozycki1-18/+10
2023-06-05MIPS: sync oprand char usage between mips and micromipsYunQiang Su1-10/+18
2023-06-05MIPS: add MT ASE support for micromips32YunQiang Su2-1/+68
2023-06-05Revert "MIPS: add MT ASE support for micromips32"YunQiang Su2-66/+1
2023-06-05MIPS: add MT ASE support for micromips32YunQiang Su2-1/+66
2023-06-01RISC-V: PR30449, Add lga assembler macro support.Jim Wilson1-0/+1
2023-05-30LoongArch: opcodes: Add support for linker relaxation.mengqinggang1-1/+4
2023-05-26x86: fix disassembler build after 1a3b4f90bc5fJan Beulich1-1/+1
2023-05-26x86: convert two pointers to (indexing) integersJan Beulich1-16/+17
2023-05-26x86: disassembling over-long insnsJan Beulich1-9/+10
2023-05-26x86: use fixed-width type for codep and friendsJan Beulich1-57/+55
2023-05-23Updated Swedish translation for the opcodes directoryNick Clifton2-238/+255
2023-05-23Support Intel FRED LKGSZhang, Jun7-4797/+4953
2023-05-23Revert "Support Intel FRED LKGS"liuhongt4-65/+2
2023-05-23Support Intel FRED LKGSZhang, Jun4-2/+65
2023-05-19RISC-V: Minor improvements for dis-assembler.Nelson Chu3-21/+40
2023-05-17gcc-4.5 build fixesAlan Modra1-14/+14
2023-05-12x86: move a few more disassembler helper functionsJan Beulich1-34/+29