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| author | Feiyang Chen <chenfeiyang@loongson.cn> | 2023-06-16 11:16:10 +0800 |
|---|---|---|
| committer | liuzhensong <liuzhensong@loongson.cn> | 2023-06-25 15:06:32 +0800 |
| commit | 4142b2368353bda6d2e5ff80640c012b80f84024 (patch) | |
| tree | 008063c1b9de2d1e466f13b7b603dbf298a551c5 /opcodes | |
| parent | 0e389a1595b792a70aa76e60dc3e5244a10f2a55 (diff) | |
| download | gdb-4142b2368353bda6d2e5ff80640c012b80f84024.zip gdb-4142b2368353bda6d2e5ff80640c012b80f84024.tar.gz gdb-4142b2368353bda6d2e5ff80640c012b80f84024.tar.bz2 | |
LoongArch: Support referring to FCSRs as $fcsrX
Previously, FCSRs were referred to as $rX, which seemed strange.
We refer to FCSRs as $fcsrX, which ensures compatibility with LLVM
IAS as well.
gas/ChangeLog:
* config/tc-loongarch.c:
(loongarch_fc_normal_name): New definition.
(loongarch_fc_numeric_name): New definition.
(loongarch_single_float_opcodes): Modify `movgr2fcsr` and
`movfcsr2gr`.
testsuite/gas/loongarch/float_op.d: Likewise.
testsuite/gas/loongarch/float_op.s: Likewise.
include/ChangeLog:
* opcode/loongarch.h:
(loongarch_fc_normal_name): New extern.
(loongarch_fc_numeric_name): New extern.
opcodes/ChangeLog:
* opcodes/loongarch-dis.c (loongarch_after_parse_args): Support
referring to FCSRs as $fcsrX.
* opcodes/loongarch-opc.c (loongarch_args_parser_can_match_arg_helper):
Likewise.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/loongarch-dis.c | 11 | ||||
| -rw-r--r-- | opcodes/loongarch-opc.c | 14 |
2 files changed, 22 insertions, 3 deletions
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c index d064d30..0725270 100644 --- a/opcodes/loongarch-dis.c +++ b/opcodes/loongarch-dis.c @@ -61,6 +61,7 @@ get_loongarch_opcode_by_binfmt (insn_t insn) static const char *const *loongarch_r_disname = NULL; static const char *const *loongarch_f_disname = NULL; +static const char *const *loongarch_fc_disname = NULL; static const char *const *loongarch_c_disname = NULL; static const char *const *loongarch_cr_disname = NULL; static const char *const *loongarch_v_disname = NULL; @@ -78,6 +79,7 @@ set_default_loongarch_dis_options (void) loongarch_r_disname = loongarch_r_lp64_name; loongarch_f_disname = loongarch_f_lp64_name; + loongarch_fc_disname = loongarch_fc_normal_name; loongarch_c_disname = loongarch_c_normal_name; loongarch_cr_disname = loongarch_cr_normal_name; loongarch_v_disname = loongarch_v_normal_name; @@ -142,7 +144,14 @@ dis_one_arg (char esc1, char esc2, const char *bit_field, info->fprintf_func (info->stream, "%s", loongarch_r_disname[u_imm]); break; case 'f': - info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]); + switch (esc2) + { + case 'c': + info->fprintf_func (info->stream, "%s", loongarch_fc_disname[u_imm]); + break; + default: + info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]); + } break; case 'c': switch (esc2) diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index 573b691..e557b23 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -77,6 +77,16 @@ const char *const loongarch_f_lp64_name1[32] = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", }; +const char *const loongarch_fc_normal_name[4] = +{ + "$fcsr0", "$fcsr1", "$fcsr2", "$fcsr3", +}; + +const char *const loongarch_fc_numeric_name[4] = +{ + "$r0", "$r1", "$r2", "$r3", +}; + const char *const loongarch_c_normal_name[8] = { "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fcc7", @@ -459,8 +469,8 @@ static struct loongarch_opcode loongarch_single_float_opcodes[] = { 0x0114ac00, 0xfffffc00, "movgr2frh.w", "f0:5,r5:5", 0, 0, 0, 0 }, { 0x0114b400, 0xfffffc00, "movfr2gr.s", "r0:5,f5:5", 0, 0, 0, 0 }, { 0x0114bc00, 0xfffffc00, "movfrh2gr.s", "r0:5,f5:5", 0, 0, 0, 0 }, - { 0x0114c000, 0xfffffc00, "movgr2fcsr", "r0:5,r5:5", 0, 0, 0, 0 }, - { 0x0114c800, 0xfffffc00, "movfcsr2gr", "r0:5,r5:5", 0, 0, 0, 0 }, + { 0x0114c000, 0xfffffc1c, "movgr2fcsr", "fc0:2,r5:5", 0, 0, 0, 0 }, + { 0x0114c800, 0xffffff80, "movfcsr2gr", "r0:5,fc5:2", 0, 0, 0, 0 }, { 0x0114d000, 0xfffffc18, "movfr2cf", "c0:3,f5:5", 0, 0, 0, 0 }, { 0x0114d400, 0xffffff00, "movcf2fr", "f0:5,c5:3", 0, 0, 0, 0 }, { 0x0114d800, 0xfffffc18, "movgr2cf", "c0:3,r5:5", 0, 0, 0, 0 }, |