| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-11-02 | x86: drop bogus Tbyte | Jan Beulich | 2 | -4/+4 |
| 2022-11-02 | Support Intel MSRLIST | Hu, Lin1 | 6 | -4161/+4237 |
| 2022-11-02 | Support Intel WRMSRNS | Hu, Lin1 | 6 | -4160/+4212 |
| 2022-11-02 | Support Intel CMPccXADD | Haochen Jiang | 6 | -4150/+4805 |
| 2022-11-02 | Support Intel AVX-VNNI-INT8 | Cui,Lili | 6 | -456/+612 |
| 2022-11-02 | Support Intel AVX-IFMA | Hongyu Wang | 7 | -4145/+4224 |
| 2022-11-01 | opcodes/arm: don't pass non-string literal to printf like function | Andrew Burgess | 1 | -2/+3 |
| 2022-11-01 | opcodes/arm: silence compiler warning about uninitialized variable use | Andrew Burgess | 1 | -1/+3 |
| 2022-11-01 | opcodes/arm: add disassembler styling for arm | Andrew Burgess | 2 | -1002/+1631 |
| 2022-11-01 | opcodes/arm: use '@' consistently for the comment character | Andrew Burgess | 1 | -48/+48 |
| 2022-10-31 | x86: minor improvements to optimize_imm() (part III) | Jan Beulich | 2 | -6/+0 |
| 2022-10-31 | Updated Romainain translation for the binutils sub-directory and Swedish tran... | Nick Clifton | 1 | -399/+475 |
| 2022-10-31 | Support Intel PREFETCHI | Cui, Lili | 6 | -4141/+4263 |
| 2022-10-31 | RX assembler: switch arguments of thw MVTACGU insn. | Yoshinori Sato | 3 | -8/+13 |
| 2022-10-28 | RISC-V: Output mapping symbols with ISA string. | Nelson Chu | 1 | -0/+9 |
| 2022-10-27 | PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions | Peter Bergner | 1 | -1/+38 |
| 2022-10-27 | PowerPC: Add support for RFC02653 - Dense Math Facility | Peter Bergner | 2 | -26/+191 |
| 2022-10-24 | x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns | Jan Beulich | 6 | -235/+271 |
| 2022-10-21 | Support Intel AMX-FP16 | Cui,Lili | 6 | -4088/+4139 |
| 2022-10-20 | x86: re-work AVX-VNNI support | Jan Beulich | 4 | -7025/+7021 |
| 2022-10-18 | x86: Disable AVX-VNNI when disabling AVX2 | H.J. Lu | 2 | -3/+3 |
| 2022-10-18 | x86: correct CPU_AMX_{BF16,INT8}_FLAGS | Jan Beulich | 2 | -4/+4 |
| 2022-10-17 | Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp} | CaiJingtao | 2 | -7/+17 |
| 2022-10-17 | aarch64: Tweak handling of F_STRICT | Richard Sandiford | 1 | -17/+8 |
| 2022-10-17 | x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns | Jan Beulich | 1 | -6/+6 |
| 2022-10-17 | x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones | Jan Beulich | 3 | -15/+22 |
| 2022-10-16 | PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | Alan Modra | 2 | -1/+9 |
| 2022-10-14 | PowerPC SPE disassembly and tests | Alan Modra | 1 | -2/+2 |
| 2022-10-14 | e200 LSP support | Alan Modra | 2 | -337/+411 |
| 2022-10-14 | opcodes/riscv-dis.c: Remove last_map_state | Tsukasa OI | 1 | -3/+0 |
| 2022-10-14 | opcodes/riscv-dis.c: Make XLEN variable static | Tsukasa OI | 1 | -1/+1 |
| 2022-10-14 | opcodes/riscv-dis.c: Use bool type whenever possible | Tsukasa OI | 1 | -5/+5 |
| 2022-10-14 | opcodes/riscv-dis.c: Tidying with spacing | Tsukasa OI | 1 | -1/+1 |
| 2022-10-14 | opcodes/riscv-dis.c: Tidying with comments/clarity | Tsukasa OI | 1 | -4/+21 |
| 2022-10-14 | RISC-V: Move standard hints before all instructions | Tsukasa OI | 1 | -4/+8 |
| 2022-10-14 | RISC-V: Move certain arrays to riscv-opc.c | Tsukasa OI | 1 | -0/+13 |
| 2022-10-06 | RISC-V: Print XTheadMemPair literal as "immediate" | Tsukasa OI | 1 | -1/+1 |
| 2022-10-06 | RISC-V: Fix T-Head immediate types on printing | Tsukasa OI | 1 | -4/+4 |
| 2022-10-06 | RISC-V: Print comma and tabs as the "text" style | Tsukasa OI | 1 | -11/+20 |
| 2022-10-06 | RISC-V: Optimize riscv_disassemble_data printf | Tsukasa OI | 1 | -6/+4 |
| 2022-10-06 | RISC-V: Fix printf argument types corresponding %x | Tsukasa OI | 1 | -7/+7 |
| 2022-10-06 | RISC-V: Fix immediates to have "immediate" style | Tsukasa OI | 1 | -5/+5 |
| 2022-10-05 | Arm64: support CLEARBHB alias | Jan Beulich | 4 | -1576/+1579 |
| 2022-10-04 | RISC-V: Fix buffer overflow on print_insn_riscv | Tsukasa OI | 1 | -1/+1 |
| 2022-10-04 | RISC-V: Renamed INSN_CLASS for floating point in integer extensions. | Nelson Chu | 1 | -222/+222 |
| 2022-10-04 | opcodes/riscv: style csr names as registers | Andrew Burgess | 1 | -1/+2 |
| 2022-10-03 | RISC-V: Move supervisor instructions after all unprivileged ones | Tsukasa OI | 1 | -32/+32 |
| 2022-09-30 | RISC-V: Relax "fmv.[sdq]" requirements | Tsukasa OI | 1 | -3/+3 |
| 2022-09-30 | RISC-V: fix build after "Add support for arbitrary immediate encoding formats" | Jan Beulich | 1 | -2/+2 |
| 2022-09-30 | RISC-V: drop stray INSN_ALIAS flags | Jan Beulich | 1 | -3/+3 |
