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| author | Alan Modra <amodra@gmail.com> | 2022-10-13 16:10:15 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2022-10-14 22:07:18 +1030 |
| commit | 5abb5d3f67d6469cbb21978df09187f1ae93f5ea (patch) | |
| tree | 51c95396255e9c45b881db9eec885112fd1058fd /opcodes | |
| parent | 61a457e5da46bad626bc3b6985a58fb5ae41842d (diff) | |
| download | gdb-5abb5d3f67d6469cbb21978df09187f1ae93f5ea.zip gdb-5abb5d3f67d6469cbb21978df09187f1ae93f5ea.tar.gz gdb-5abb5d3f67d6469cbb21978df09187f1ae93f5ea.tar.bz2 | |
PowerPC SPE disassembly and tests
Where sub and subf forms of an instruction exist we generally
disassemble to the extended insn sub form rather than the underlying
machine subf instruction. Do so for SPE evsubw and evsubiw too.
spe_ambiguous.d always was a bit too optimistic. There is no sensible
way to disassemble identical bytes back to different and original
source. Instead change the test to check -Mraw results.
gas/
* testsuite/gas/ppc/ppc.exp: Run spe_ambiguous test.
* testsuite/gas/ppc/spe.d: Expect evsubw and evsubiw rather than
evsubfw and evsubifw.
* testsuite/gas/ppc/spe_ambiguous.s: Test evnor form equivalent
to evnot.
* testsuite/gas/ppc/spe_ambiguous.d: Test Mraw.
opcodes/
* ppc-opc.c (powerpc_opcodes): Move evsubw before evsubfw and
evsubiw before evsubifw and mark EXT.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ppc-opc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 1d274c3..e1b6764 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -5201,12 +5201,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evsubw", VX (4, 516), VX_MASK, PPCSPE, EXT, {RS, RB, RA}}, {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, -{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vsrq", VX (4, 517), VX_MASK, POWER10, 0, {VD, VA, VB}}, +{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, EXT, {RS, RB, UIMM}}, {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, -{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |