rocket-tools/riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-01-12	Enable Intel AVX512_VPOPCNTDQ instructions	Igor Tsimbalist	8	-5344/+5432
2017-01-12	Return -1 on memory error in print_insn_msp430	Yao Qi	2	-14/+99
2017-01-05	Prevent an abort in the FRV disassembler if the target bfd name is unknown.	Nick Clifton	2	-3/+11
2017-01-04	[AArch64] Add separate feature flag for weaker release consistent load insns	Szabolcs Nagy	2	-3/+13
2017-01-03	Add support for the Q extension to the RISCV ISA.	Kito Cheng	2	-0/+66
2017-01-03	Add fall through comment.	Dilyan Palauzov	2	-0/+5
2017-01-03	Add new Serbian translation for the opcodes library.	Nick Clifton	4	-2/+1515
2017-01-02	Regen opcodes cgen files	Alan Modra	27	-0/+237
2017-01-02	Update year range in copyright notice of all files.	Alan Modra	275	-278/+282
2017-01-02	ChangeLog rotation	Alan Modra	2	-2167/+2181
2016-12-31	Fix riscv breakage	Alan Modra	2	-0/+6
2016-12-31	PRU Opcode Port	Dimitar Dimitrov	9	-1/+548
2016-12-29	Return 'int' rather than 'unsigned short' in avrdis_opcode	Yao Qi	2	-6/+23
2016-12-28	Check bfd support for bfd_mips_elf_get_abiflags in mips make rule	Alan Modra	7	-132/+38
2016-12-23	MIPS16: Add ASMACRO instruction support	Maciej W. Rozycki	2	-0/+15
2016-12-23	MIPS16: Simplify extended operand handling	Maciej W. Rozycki	3	-20/+25
2016-12-23	MIPS16: Reassign `0' and `4' operand codes	Maciej W. Rozycki	2	-15/+22
2016-12-23	MIPS16: Handle non-extensible instructions correctly	Maciej W. Rozycki	3	-68/+86
2016-12-23	MIPS16: Remove "extended" BREAK/SDBBP handling	Maciej W. Rozycki	2	-2/+6
2016-12-23	MIPS16/GAS: Disallow EXTEND delay-slot scheduling	Maciej W. Rozycki	2	-1/+6
2016-12-23	opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFD	Maciej W. Rozycki	8	-12/+150
2016-12-23	Bump version to 2.28.51	Tristan Gingold	2	-10/+14
2016-12-23	Regenerate pot files.	Tristan Gingold	2	-372/+640
2016-12-22	ChangeLog formatting fixes	Alan Modra	1	-1/+1
2016-12-22	Avoid creating symbol table entries for registers	Andrew Waterman	2	-2/+6
2016-12-20	MIPS16/opcodes: Respect ISA and ASE in disassembly	Maciej W. Rozycki	2	-1/+11
2016-12-20	MIPS16: Switch to 32-bit opcode table interpretation	Maciej W. Rozycki	3	-81/+90
2016-12-20	MIPS16/opcodes: Correct 64-bit macros' ISA membership	Maciej W. Rozycki	2	-6/+12
2016-12-20	MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership	Maciej W. Rozycki	2	-1/+7
2016-12-20	Correct assembler mnemonic for RISC-V aqrl AMOs	Andrew Waterman	2	-22/+27
2016-12-20	Fix disassembly of RISC-V CSR instructions under -Mno-aliases	Andrew Waterman	2	-22/+27
2016-12-20	Add canonical JALR for RISC-V	Andrew Waterman	2	-0/+8
2016-12-20	Re-work RISC-V gas flags: now we just support -mabi and -march	Andrew Waterman	2	-2/+11
2016-12-20	Formatting changes for RISC-V	Andrew Waterman	2	-8/+10
2016-12-20	Add opcodes RISC-V dependencies	Alan Modra	4	-0/+14
2016-12-19	MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLE	Maciej W. Rozycki	2	-1/+6
2016-12-19	MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64	Maciej W. Rozycki	2	-2/+14
2016-12-16	Fix compile time warning building arm-dis.c	Nick Clifton	2	-2/+7
2016-12-14	MIPS/opcodes: Also set disassembler's ASE flags from ELF structures	Maciej W. Rozycki	2	-2/+48
2016-12-14	MIPS/opcodes: Reorder ELF file header flag handling in disassembler	Maciej W. Rozycki	2	-13/+18
2016-12-14	MIPS16: Fix SP-relative SD instruction annotation	Maciej W. Rozycki	2	-2/+7
2016-12-14	MIPS16/opcodes: Fix and clarify MIPS16e commentary	Maciej W. Rozycki	2	-4/+9
2016-12-13	[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field	Renlin Li	6	-25/+29
2016-12-12	Handle memory error in print_insn_rx	Yao Qi	2	-4/+36
2016-12-12	Handle memory error in print_insn_rl78_common	Yao Qi	2	-4/+36
2016-12-09	MIPS16: Remove unused `>' operand code	Maciej W. Rozycki	2	-2/+4
2016-12-09	MIPS16/opcodes: Use hexadecimal interpretation for the `e' operand code	Maciej W. Rozycki	2	-1/+6
2016-12-09	MIPS16/opcodes: Reformat raw EXTEND and undecoded output	Maciej W. Rozycki	2	-4/+11
2016-12-08	MIPS16/opcodes: Fix off-by-one indentation in `print_mips16_insn_arg'	Maciej W. Rozycki	2	-30/+35
2016-12-08	MIPS16/opcodes: Fix PC-relative operation delay-slot adjustment	Maciej W. Rozycki	2	-6/+16