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| author | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2017-01-04 12:27:10 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2017-01-04 12:31:08 +0000 |
| commit | d74d4880e23263bac3690bcb641af56bd13036e6 (patch) | |
| tree | 728a2c19b7ef9f5fc7eda05e30f7a77acd1dd309 /opcodes | |
| parent | 10ab38d930db6159b93082dfe5e41761bdc0d70b (diff) | |
| download | gdb-d74d4880e23263bac3690bcb641af56bd13036e6.zip gdb-d74d4880e23263bac3690bcb641af56bd13036e6.tar.gz gdb-d74d4880e23263bac3690bcb641af56bd13036e6.tar.bz2 | |
[AArch64] Add separate feature flag for weaker release consistent load insns
The weaker release consistency support of ARMv8.3-A is allowed as an optional
extension for ARMv8.2-A, so separate command line option and feature flag is
added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on.
opcodes/
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
(aarch64_opcode_table): Use RCPC_INSN.
include/
* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
(AARCH64_ARCH_V8_3): Update.
gas/
* config/tc-aarch64.c (aarch64_features): Add rcpc.
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.d: This.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.s: This.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 11 |
2 files changed, 13 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d01cbde..555a379 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> + + * aarch64-tbl.h (RCPC, RCPC_INSN): Define. + (aarch64_opcode_table): Use RCPC_INSN. + 2017-01-03 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 4bfee03..472205f 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1940,6 +1940,8 @@ static const aarch64_feature_set aarch64_feature_fp_v8_3 = AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0); static const aarch64_feature_set aarch64_feature_simd_v8_3 = AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_SIMD, 0); +static const aarch64_feature_set aarch64_feature_rcpc = + AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -1958,6 +1960,7 @@ static const aarch64_feature_set aarch64_feature_simd_v8_3 = #define ARMV8_3 &aarch64_feature_v8_3 #define FP_V8_3 &aarch64_feature_fp_v8_3 #define SIMD_V8_3 &aarch64_feature_simd_v8_3 +#define RCPC &aarch64_feature_rcpc #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, NULL } @@ -1986,6 +1989,8 @@ static const aarch64_feature_set aarch64_feature_simd_v8_3 = FLAGS | F_STRICT, TIED, NULL } #define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, NULL } +#define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, NULL } struct aarch64_opcode aarch64_opcode_table[] = { @@ -2982,9 +2987,9 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), CORE_INSN ("stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), CORE_INSN ("ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), - V8_3_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), - V8_3_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), - V8_3_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), + RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), + RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), + RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), /* Limited Ordering Regions load/store instructions. */ _LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), |