aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Expand)AuthorFilesLines
2015-04-27S/390: Fixes for z13 instructions.Andreas Krebbel3-5/+13
2015-04-23x86: disambiguate disassembly of certain AVX512 insnsJan Beulich3-13/+52
2015-04-15Remove the unused PREFIX_UD_XXXH.J. Lu2-6/+9
2015-04-15Check dp->prefix_requirement insteadH.J. Lu2-5/+7
2015-04-15Handle invalid prefixes for rdrand and rdseedH.J. Lu2-5/+35
2015-04-15Replace mandatory_prefix with prefix_requirementH.J. Lu2-310/+349
2015-04-15[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2Renlin Li2-2/+14
2015-04-06x86: Use individual prefix control for each opcode.Ilya Tocar3-1914/+1941
2015-03-30opcodes: d10v: fix old style prototypeMike Frysinger2-1/+5
2015-03-29Add the missing opcodes/ChangeLog entryH.J. Lu1-0/+4
2015-03-29Regenerate opcodes/Makefile.inH.J. Lu1-1/+0
2015-03-26powerpc: Only initialise opcode indices onceAnton Blanchard2-25/+34
2015-03-26powerpc: Add slbfee. instructionAnton Blanchard2-0/+6
2015-03-24Extend arm_feature_set struct to provide more bitsTerry Guo2-1294/+2543
2015-03-17Add znver1 processorGanesh Gopalasubramanian7-5283/+5339
2015-03-13MIPS: Fix constraint issues with the R6 beqc and bnec instructionsAndrew Bennett2-2/+7
2015-03-13Add support for MIPS R6 evp and dvp instructions.Andrew Bennett2-0/+8
2015-03-10S/390: Add more IBM z13 instructionsAndreas Krebbel3-0/+30
2015-03-10[AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang5-490/+439
2015-03-03[ARM] Skip private symbol when doing objdumpJiong Wang2-2/+9
2015-02-25[SH] Fix clrs, sets, pref insn arch memberships.Oleg Endo2-3/+10
2015-02-23Adds a space between the operands of the RL78's MOV instruction for consisten...Vinay3-8/+14
2015-02-19Wrap a few opcodes headers in extern "C" for C++Pedro Alves2-0/+12
2015-02-11Fixes a problem with the RL78 disassembler which would incorrectly disassembl...Nick Clifton3-93/+93
2015-02-10opcodes/microblaze: Rename 'or', 'and', 'xor' to avoid C++ conflictPedro Alves3-4/+13
2015-01-29NDS32: Set branch instruction to relaxable.Kuan-Lin Chen1-1/+2
2015-01-28FT32 initial supportAlan Modra9-0/+292
2015-01-28NDS32/opcodes: Add new system registers.Kuan-Lin Chen2-2/+14
2015-01-16S/390: Add support for IBM z13.Andreas Krebbel5-530/+1203
2015-01-02Regenerate Makeile.in file for copyright updateAlan Modra1-1/+1
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra265-1150/+1168
2014-12-27Limit moxie sto/ldo offsets to 16 bitsAnthony Green3-16/+22
2014-12-24Add mul.x and umul.x instructions to moxie portAnthony Green2-9/+14
2014-12-16Add in a JALRC alias and fix the NAL instruction.Matthew Fortune2-1/+7
2014-12-12Add zex instructions for moxie portAnthony Green2-2/+6
2014-12-06Add Visium support to opcodesEric Botcazou9-0/+886
2014-11-30Power4 should treat mftb as extended mfspr mnemonicAlan Modra2-6/+11
2014-11-28Remove broken nios2 assembler dwim support.Sandra Loosemore2-4/+9
2014-11-28Don't deprecate powerpc mftb insnAlan Modra2-7/+15
2014-11-24Update libtool.m4 from GCC trunkH.J. Lu2-2/+6
2014-11-17Add AVX512VBMI instructionsIlya Tocar8-5445/+5730
2014-11-17Add AVX512IFMA instructionsIlya Tocar8-5512/+5677
2014-11-17Add pcommit instructionIlya Tocar7-5262/+10575
2014-11-17Add clwb instructionIlya Tocar7-5260/+5310
2014-11-06Add mach parameter to nios2_find_opcode_hash.Sandra Loosemore2-3/+9
2014-11-03Import updated translations supplied by the Translation Project.Nick Clifton2-146/+372
2014-10-31MIPS: Add Octeon 3 supportNaveen H.S3-3/+29
2014-10-29Updated/new translations provided by the Translations Project.Nick Clifton2-270/+1059
2014-10-23Refactoring/cleanup of nios2 opcodes and assembler code.Sandra Loosemore3-451/+580
2014-10-21ppc: enable msgclr and msgsnd on Power8Jan Beulich2-2/+6
generated by cgit v1.1 at 2024-11-14 21:57:26 +0000