RISC-V: Add SiFive cease extension v1.0

Add SiFive cease extension,
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf

This aligns LLVM:
* https://llvm.org/docs/RISCVUsage.html
* https://github.com/llvm/llvm-project/pull/83896

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for
	'xsfcease'.
	(riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE.
	(riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE.

gas/ChangeLog:

	* doc/c-riscv.texi: Updated.
	* testsuite/gas/riscv/march-help.l: Updated.
	* testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'.
	* testsuite/gas/riscv/sifive-insns.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and
	mask encoding for 'sf.cease'.
	* opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for
	'xsfcease'.

opcodes/ChangeLog:

    * riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.

1 files changed, 3 insertions, 0 deletions

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e101c3d..f7c0f5c 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -3113,6 +3113,9 @@ const struct riscv_opcode riscv_opcodes[] =
 {"sf.vc.fvw",   0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 },
 {"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 },
 
+/* Vendor-specific (SiFive) cease instruction.  */
+{"sf.cease", 0, INSN_CLASS_XSFCEASE, "", MATCH_SF_CEASE, MASK_SF_CEASE, match_opcode, 0 },
+
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
 };