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authorHau Hsu <hau.hsu@sifive.com>2024-06-18 14:49:04 +0800
committerNelson Chu <nelson@rivosinc.com>2024-06-18 15:06:34 +0800
commit7003edc383feaa72c13310d075d383c2a98a6a6e (patch)
tree5c36a828df0eda14aa56dcec63b53455b26b8590
parent88729e96162f0293177d2324fc8dc6cd78aac793 (diff)
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RISC-V: Add SiFive cease extension v1.0
Add SiFive cease extension, https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf This aligns LLVM: * https://llvm.org/docs/RISCVUsage.html * https://github.com/llvm/llvm-project/pull/83896 bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for 'xsfcease'. (riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE. (riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE. gas/ChangeLog: * doc/c-riscv.texi: Updated. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'. * testsuite/gas/riscv/sifive-insns.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and mask encoding for 'sf.cease'. * opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for 'xsfcease'. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.
-rw-r--r--bfd/elfxx-riscv.c7
-rw-r--r--gas/doc/c-riscv.texi5
-rw-r--r--gas/testsuite/gas/riscv/march-help.l1
-rw-r--r--gas/testsuite/gas/riscv/sifive-insns.d1
-rw-r--r--gas/testsuite/gas/riscv/sifive-insns.s6
-rw-r--r--include/opcode/riscv-opc.h3
-rw-r--r--include/opcode/riscv.h1
-rw-r--r--opcodes/riscv-opc.c3
8 files changed, 26 insertions, 1 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 6dc7193..275b2ef 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1485,7 +1485,8 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadzvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
- {"xsfvcp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0},
+ {"xsfvcp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xsfcease", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
@@ -2736,6 +2737,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xventanacondops");
case INSN_CLASS_XSFVCP:
return riscv_subset_supports (rps, "xsfvcp");
+ case INSN_CLASS_XSFCEASE:
+ return riscv_subset_supports (rps, "xsfcease");
default:
rps->error_handler
(_("internal: unreachable INSN_CLASS_*"));
@@ -3004,6 +3007,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xtheadvector";
case INSN_CLASS_XTHEADZVAMO:
return "xtheadzvamo";
+ case INSN_CLASS_XSFCEASE:
+ return "xsfcease";
default:
rps->error_handler
(_("internal: unreachable INSN_CLASS_*"));
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 61bb7bc..e579eeb 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -850,4 +850,9 @@ VCIX as a low-latency, high-throughput interface to a coprocessor.
It is documented in @url{https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf}.
+@item XSfCease
+XSfCease provides an instruction to instigates power-down sequence.
+
+It is documented in @url{https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf}.
+
@end table
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index e0d597e..c33d856 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -130,3 +130,4 @@ All available -march extensions for RISC-V:
xtheadzvamo 1.0
xventanacondops 1.0
xsfvcp 1.0
+ xsfcease 1.0
diff --git a/gas/testsuite/gas/riscv/sifive-insns.d b/gas/testsuite/gas/riscv/sifive-insns.d
index f7d63d1..610f625 100644
--- a/gas/testsuite/gas/riscv/sifive-insns.d
+++ b/gas/testsuite/gas/riscv/sifive-insns.d
@@ -35,3 +35,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+fc25c05b[ ]+sf.vc.v.xvw[ ]+0x3,v0,v2,a1
[ ]+[0-9a-f]+:[ ]+fc27b05b[ ]+sf.vc.v.ivw[ ]+0x3,v0,v2,15
[ ]+[0-9a-f]+:[ ]+fc25d05b[ ]+sf.vc.v.fvw[ ]+0x1,v0,v2,fa1
+[ ]+[0-9a-f]+:[ ]+30500073[ ]+sf.cease
diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/riscv/sifive-insns.s
index d593692..cdf90c1 100644
--- a/gas/testsuite/gas/riscv/sifive-insns.s
+++ b/gas/testsuite/gas/riscv/sifive-insns.s
@@ -31,3 +31,9 @@
sf.vc.v.ivw 0x3, v0, v2, 15
sf.vc.v.fvw 0x1, v0, v2, fa1
.option pop
+
+ # xscease
+ .option push
+ .option arch, +xsfcease1p0
+ sf.cease
+ .option pop
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index f87822a..8763cdf 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -3155,6 +3155,9 @@
#define MASK_SF_VC_FVW 0xfa00707f
#define MATCH_SF_VC_V_FVW 0xf800505b
#define MASK_SF_VC_V_FVW 0xfa00707f
+/* Vendor-specific (SiFive) cease instruction. */
+#define MATCH_SF_CEASE 0x30500073
+#define MASK_SF_CEASE 0xffffffff
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 20bfdb1..ece2963 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -515,6 +515,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADZVAMO,
INSN_CLASS_XVENTANACONDOPS,
INSN_CLASS_XSFVCP,
+ INSN_CLASS_XSFCEASE,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e101c3d..f7c0f5c 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -3113,6 +3113,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"sf.vc.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 },
{"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 },
+/* Vendor-specific (SiFive) cease instruction. */
+{"sf.cease", 0, INSN_CLASS_XSFCEASE, "", MATCH_SF_CEASE, MASK_SF_CEASE, match_opcode, 0 },
+
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
};