diff options
Diffstat (limited to 'gcc')
156 files changed, 3667 insertions, 283 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 711d040..6c139d7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,129 @@ +2025-07-14 Andrew Stubbs <ams@baylibre.com> + + * config/gcn/gcn-valu.md (vec_cmpu<mode>di_exec): Call gen_vec_cmp*, + not gen_vec_cmpu*. + +2025-07-14 Richard Biener <rguenther@suse.de> + + Revert: + 2025-07-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121059 + * tree-vect-stmts.cc (vectorizable_operation): Record a + loop mask for mask AND operations. + +2025-07-14 Juergen Christ <jchrist@linux.ibm.com> + + * config/s390/vector.md (reduc_plus_scal_<mode>): Implement. + (reduc_plus_scal_v2df): Implement. + (reduc_plus_scal_v4sf): Implement. + (REDUC_FMINMAX): New int iterator. + (reduc_fminmax_name): New int attribute. + (reduc_minmax): New code iterator. + (reduc_minmax_name): New code attribute. + (reduc_<reduc_fminmax_name>_scal_v2df): Implement. + (reduc_<reduc_fminmax_name>_scal_v4sf): Implement. + (reduc_<reduc_minmax_name>_scal_v2df): Implement. + (reduc_<reduc_minmax_name>_scal_v4sf): Implement. + (REDUCBIN): New code iterator. + (reduc_bin_insn): New code attribute. + (reduc_<reduc_bin_insn>_scal_v2di): Implement. + (reduc_<reduc_bin_insn>_scal_v4si): Implement. + (reduc_<reduc_bin_insn>_scal_v8hi): Implement. + (reduc_<reduc_bin_insn>_scal_v16qi): Implement. + +2025-07-14 Juergen Christ <jchrist@linux.ibm.com> + + * config/s390/s390.cc (s390_option_override_internal): Remove override. + +2025-07-14 Andrew Stubbs <ams@baylibre.com> + + * config/gcn/gcn-valu.md (add<mode>3<exec_clobber>): Rename ... + (add<mode>3<exec>): ... to this, remove the clobber, and change the + instruction from v_add_co_u32 to v_add_u32. + (add<mode>3_dup<exec_clobber>): Rename ... + (add<mode>3_dup<exec>): ... to this, and likewise. + (sub<mode>3<exec_clobber>): Rename ... + (sub<mode>3<exec>): ... to this, and likewise + * config/gcn/gcn.md (addsi3): Remove the DI clobber, and change the + instruction from v_add_co_u32 to v_add_u32. + (addsi3_scc): Likewise. + (subsi3): Likewise, but for v_sub_co_u32. + (muldi3): Likewise. + +2025-07-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121059 + * tree-vect-stmts.cc (vectorizable_operation): Record a + loop mask for mask AND operations. + +2025-07-14 Pan Li <pan2.li@intel.com> + + * match.pd: Make sure widen mul has twice bitsize + of the inputs in SAT_MUL pattern. + +2025-07-14 Uros Bizjak <ubizjak@gmail.com> + + PR target/121015 + * config/i386/i386-features.cc (ix86_broadcast_inner): Check all + 0s/1s vectors with standard_sse_constant_p. + +2025-07-14 H.J. Lu <hjl.tools@gmail.com> + + PR target/120881 + * config.in: Regenerated. + * configure: Likewise. + * configure.ac: Add --enable-x86-64-mfentry. + * config/i386/i386-options.cc (ix86_option_override_internal): + Enable __fentry__ in 64-bit mode if ENABLE_X86_64_MFENTRY is set + to 1. Warn -pg without -mfentry with shrink wrapping enabled. + * doc/install.texi: Document --enable-x86-64-mfentry. + +2025-07-14 François-Xavier Coudert <fxcoudert@gcc.gnu.org> + + PR target/120645 + * config/darwin-driver.cc: Account for latest macOS numbering + scheme. + +2025-07-14 Paul-Antoine Arras <parras@baylibre.com> + + PR target/119100 + * config/riscv/autovec-opt.md (*vfwmacc_vf_<mode>): New pattern to + handle both vfwmacc and vfwmsac. + (*extend_vf_<mode>): New pattern that serves as an intermediate combine + step. + * config/riscv/vector-iterators.md (vsubel): New mode attribute. This is + just the lower-case version of VSUBEL. + * config/riscv/vector.md (@pred_widen_mul_<optab><mode>_scalar): Reorder + and swap operands to match the RTL emitted by expand, i.e. first + float_extend then vec_duplicate. + +2025-07-14 Alfie Richards <alfie.richards@arm.com> + + * config/aarch64/aarch64-sme.md (@aarch64_sme_<faminmax_uns_op><mode>): + New patterns. + * config/aarch64/aarch64-sve-builtins-sme.def (svamin): New intrinsics. + (svamax): New intrinsics. + * config/aarch64/aarch64-sve-builtins-sve2.cc (class faminmaximpl): New + class. + (svamin): New function. + (svamax): New function. + +2025-07-14 Haochen Jiang <haochen.jiang@intel.com> + + * config/i386/i386.h (PTA_PANTHERLAKE): Revmoe KL and WIDEKL. + (PTA_CLEARWATERFOREST): Ditto. + * doc/invoke.texi: Revise documentation. + +2025-07-13 Andrew Pinski <quic_apinski@quicinc.com> + + PR middle-end/120866 + * tree.cc: Add include to tm_p.h. + +2025-07-13 Benjamin Wu <bwu25@cs.washington.edu> + + * gimple.h (GTMA_DOES_GO_IRREVOCABLE): Fix typo. + 2025-07-12 Jan Hubicka <hubicka@ucw.cz> * auto-profile.cc (function_instance::~function_instance): diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 7bcb4c4..5c2a452 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250713 +20250715 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 49b4b95..b66c7ba 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,9 @@ +2025-07-14 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/121056 + * sem_ch4.adb (Try_Object_Operation.Try_Primitive_Operation): Add + test on Is_Record_Type before accessing Underlying_Record_View. + 2025-07-10 Jakub Jelinek <jakub@redhat.com> * par-load.adb: Comment spelling fix: bellow -> below. diff --git a/gcc/ada/sem_ch4.adb b/gcc/ada/sem_ch4.adb index dc81467..56dc7c6 100644 --- a/gcc/ada/sem_ch4.adb +++ b/gcc/ada/sem_ch4.adb @@ -10692,6 +10692,7 @@ package body Sem_Ch4 is or else (Has_Unknown_Discriminants (Typ) + and then Is_Record_Type (Base_Type (Obj_Type)) and then Typ = Underlying_Record_View (Base_Type (Obj_Type))) -- Prefix can be dereferenced diff --git a/gcc/cobol/ChangeLog b/gcc/cobol/ChangeLog index 5555b8e..c294ade 100644 --- a/gcc/cobol/ChangeLog +++ b/gcc/cobol/ChangeLog @@ -1,3 +1,142 @@ +2025-07-14 Robert Dubner <rdubner@symas.com> + + * cobol1.cc (cobol_langhook_handle_option): Eliminate cppcheck warnings. + * dts.h: Likewise. + * except.cc (cbl_enabled_exceptions_t::dump): Likewise. + * gcobolspec.cc (lang_specific_driver): Likewise. + * genapi.cc (parser_file_merge): Likewise. + * gengen.cc (gg_unique_in_function): Likewise. + (gg_declare_variable): Likewise. + (gg_peek_fn_decl): Likewise. + (gg_define_function): Likewise. + * genmath.cc (set_up_on_exception_label): Likewise. + (set_up_compute_error_label): Likewise. + (arithmetic_operation): Likewise. + (fast_divide): Likewise. + * genutil.cc (get_and_check_refstart_and_reflen): Likewise. + (get_depending_on_value_from_odo): Likewise. + (get_data_offset): Likewise. + (get_binary_value): Likewise. + (process_this_exception): Likewise. + (copy_little_endian_into_place): Likewise. + (refer_is_clean): Likewise. + (refer_fill_depends): Likewise. + * genutil.h (process_this_exception): Likewise. + (copy_little_endian_into_place): Likewise. + (refer_is_clean): Likewise. + * lexio.cc (check_push_pop_directive): Likewise. + (check_source_format_directive): Likewise. + (location_in): Likewise. + (lexer_input): Likewise. + (cdftext::lex_open): Likewise. + (lexio_dialect_mf): Likewise. + (valid_sequence_area): Likewise. + (cdftext::free_form_reference_format): Likewise. + (cdftext::segment_line): Likewise. + * lexio.h (struct span_t): Likewise. + * scan_ante.h (trim_location): Likewise. + * symbols.cc (symbol_elem_cmp): Likewise. + (symbol_alphabet): Likewise. + (end_of_group): Likewise. + (cbl_field_t::attr_str): Likewise. + (symbols_update): Likewise. + (symbol_typedef_add): Likewise. + (symbol_field_add): Likewise. + (new_temporary_impl): Likewise. + (symbol_label_section_exists): Likewise. + (symbol_program_callables): Likewise. + (file_status_status_of): Likewise. + * symfind.cc (is_data_field): Likewise. + (finalize_symbol_map2): Likewise. + (class in_scope): Likewise. + (symbol_match2): Likewise. + * util.cc (get_current_dir_name): Likewise. + (gb4): Likewise. + (class cdf_directives_t): Likewise. + (cbl_field_t::report_invalid_initial_value): Likewise. + (literal_subscript_oob): Likewise. + (cbl_refer_t::str): Likewise. + (date_time_fmt): Likewise. + (class unique_stack): Likewise. + (cobol_set_pp_option): Likewise. + (cobol_filename): Likewise. + (cobol_filename_restore): Likewise. + (gcc_location_set_impl): Likewise. + (ydferror): Likewise. + (error_msg_direct): Likewise. + (yyerror): Likewise. + (cbl_unimplemented_at): Likewise. + +2025-07-13 Robert Dubner <rdubner@symas.com> + + * Make-lang.in: Eliminate the .cc.o override. + * genapi.cc (level_88_helper): Eliminate cppcheck warning. + (get_level_88_domain): Likewise. + (get_class_condition_string): Likewise. + (parser_call_targets_dump): Likewise. + (parser_compile_ecs): Likewise. + (initialize_variable_internal): Likewise. + (move_tree): Likewise. + (combined_name): Likewise. + (assembler_label): Likewise. + (find_procedure): Likewise. + (parser_perform): Likewise. + (parser_perform_times): Likewise. + (internal_perform_through): Likewise. + (internal_perform_through_times): Likewise. + (psa_FldLiteralN): Likewise. + (psa_FldBlob): Likewise. + (parser_accept): Likewise. + (parser_accept_exception): Likewise. + (parser_accept_exception_end): Likewise. + (parser_accept_command_line): Likewise. + (parser_accept_envar): Likewise. + (parser_display_internal): Likewise. + (parser_display): Likewise. + (parser_assign): Likewise. + (parser_initialize_table): Likewise. + (parser_arith_error): Likewise. + (parser_arith_error_end): Likewise. + (parser_division): Likewise. + (label_fetch): Likewise. + (parser_label_label): Likewise. + (parser_label_goto): Likewise. + (parser_perform_start): Likewise. + (parser_perform_conditional): Likewise. + (parser_perform_conditional_end): Likewise. + (parser_perform_until): Likewise. + (parser_file_delete): Likewise. + (parser_intrinsic_subst): Likewise. + (create_lsearch_address_pairs): Likewise. + (parser_bsearch_start): Likewise. + (is_ascending_key): Likewise. + (parser_sort): Likewise. + (parser_file_sort): Likewise. + (parser_return_start): Likewise. + (parser_file_merge): Likewise. + (parser_string_overflow): Likewise. + (parser_unstring): Likewise. + (parser_string): Likewise. + (parser_call_exception): Likewise. + (create_and_call): Likewise. + (mh_identical): Likewise. + (move_helper): Likewise. + (binary_initial_from_float128): Likewise. + (initial_from_initial): Likewise. + (psa_FldLiteralA): Likewise. + (parser_local_add): Likewise. + (parser_symbol_add): Likewise. + * genapi.h (parser_display): Likewise. + * gengen.cc (gg_call_expr): Explict check for NULL_TREE. + (gg_call): Likewise. + * show_parse.h (SHOW_PARSE_LABEL_OK): Likewise. + (TRACE1_FIELD_VALUE): Likewise. + (CHECK_FIELD): Likewise. + (CHECK_FIELD2): Likewise. + (CHECK_LABEL): Likewise. + * util.cc (cbl_internal_error): Apply [[noreturn]] attribute. + * util.h (cbl_internal_error): Likewise. + 2025-07-11 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> PR cobol/120621 diff --git a/gcc/cobol/cobol1.cc b/gcc/cobol/cobol1.cc index 4bd79f1..3146da5 100644 --- a/gcc/cobol/cobol1.cc +++ b/gcc/cobol/cobol1.cc @@ -357,7 +357,7 @@ cobol_langhook_handle_option (size_t scode, return true; case OPT_M: - cobol_set_pp_option('M'); + cobol_set_pp_option('M'); return true; case OPT_fstatic_call: @@ -368,16 +368,18 @@ cobol_langhook_handle_option (size_t scode, wsclear(cobol_default_byte); return true; - case OPT_fflex_debug: + case OPT_fflex_debug: // cppcheck-suppress syntaxError // The need for this is a mystery yy_flex_debug = 1; cobol_set_debugging( true, yy_debug == 1, cobol_trace_debug == 1 ); return true; + case OPT_fyacc_debug: yy_debug = 1; cobol_set_debugging(yy_flex_debug == 1, true, cobol_trace_debug == 1 ); return true; + case OPT_ftrace_debug: cobol_set_debugging( yy_flex_debug == 1, yy_debug == 1, true ); return true; @@ -406,11 +408,13 @@ cobol_langhook_handle_option (size_t scode, case OPT_fsyntax_only: mode_syntax_only(identification_div_e); break; + case OPT_preprocess: if( ! preprocess_filter_add(arg) ) { cbl_errx( "could not execute preprocessor %s", arg); } return true; + case OPT_include: if( ! include_file_add(arg) ) { cbl_errx( "could not include %s", arg); diff --git a/gcc/cobol/dts.h b/gcc/cobol/dts.h index e12b979..c900c45 100644 --- a/gcc/cobol/dts.h +++ b/gcc/cobol/dts.h @@ -110,6 +110,6 @@ namespace dts { } ); return true; } -}; +} diff --git a/gcc/cobol/except.cc b/gcc/cobol/except.cc index e42aea2..df1c7df 100644 --- a/gcc/cobol/except.cc +++ b/gcc/cobol/except.cc @@ -96,7 +96,7 @@ cbl_enabled_exceptions_t::dump() const { return; } int i = 1; - for( auto& elem : *this ) { + for( auto& elem : *this ) { // cppcheck-suppress constVariableReference dbgmsg("cbl_enabled_exceptions_t: %2d {%s, %s, %lu}", i++, elem.location? "with location" : " no location", diff --git a/gcc/cobol/gcobolspec.cc b/gcc/cobol/gcobolspec.cc index 70784d7..9532d42 100644 --- a/gcc/cobol/gcobolspec.cc +++ b/gcc/cobol/gcobolspec.cc @@ -529,7 +529,8 @@ lang_specific_driver (struct cl_decoded_option **in_decoded_options, // cl_decoded_option size_t new_option_count = new_opt.size(); - struct cl_decoded_option *new_options = XNEWVEC (struct cl_decoded_option, new_option_count); + struct cl_decoded_option *new_options = XNEWVEC (struct cl_decoded_option, + new_option_count); for(size_t i=0; i<new_option_count; i++) { @@ -539,7 +540,7 @@ lang_specific_driver (struct cl_decoded_option **in_decoded_options, #ifdef NOISY verbose = true; #endif - if( verbose && new_options != original_options ) + if( verbose && new_options != original_options ) // cppcheck-suppress knownConditionTrueFalse { fprintf(stderr, _("Driving: (" HOST_SIZE_T_PRINT_DEC ")\n"), (fmt_size_t)new_option_count); diff --git a/gcc/cobol/genapi.cc b/gcc/cobol/genapi.cc index 23a6622..a293912 100644 --- a/gcc/cobol/genapi.cc +++ b/gcc/cobol/genapi.cc @@ -12315,7 +12315,8 @@ parser_file_merge( cbl_file_t *workfile, ELSE ENDIF - cbl_enabled_exceptions_t& enabled_exceptions( cdf_enabled_exceptions() ); + const cbl_enabled_exceptions_t& + enabled_exceptions( cdf_enabled_exceptions() ); for(size_t i=0; i<ninputs; i++) { diff --git a/gcc/cobol/gengen.cc b/gcc/cobol/gengen.cc index 2b688d6..7395350 100644 --- a/gcc/cobol/gengen.cc +++ b/gcc/cobol/gengen.cc @@ -140,7 +140,7 @@ struct cbl_translation_unit_t gg_trans_unit; // the compiler when a source code module makes that mistake. static std::unordered_set<std::string> names_we_have_seen; -// This vector is used to process the function_decls at the point we leave +// This vector is used to process the function_decls at the point we leave // the file. static std::vector<tree> finalized_function_decls; @@ -893,7 +893,7 @@ gg_create_assembler_name(const char *cobol_name) static char * gg_unique_in_function(const char *var_name, gg_variable_scope_t vs_scope) { - char *retval = (char *)xmalloc(strlen(var_name)+32); + char *retval = static_cast<char *>(xmalloc(strlen(var_name)+32)); if( (vs_scope == vs_stack || vs_scope == vs_static) ) { sprintf(retval, "%s." HOST_SIZE_T_PRINT_DEC, var_name, @@ -1028,10 +1028,7 @@ gg_declare_variable(tree type_decl, break; } DECL_INITIAL(var_decl) = initial_value; - if( unique_name ) - { - free(unique_name); - } + free(unique_name); return var_decl; } @@ -2521,12 +2518,12 @@ gg_peek_fn_decl(const char *funcname, tree fndecl_type) } return retval; } - + tree gg_build_fn_decl(const char *funcname, tree fndecl_type) { tree function_decl; - + std::string key = function_decl_key(funcname, fndecl_type); std::unordered_map<std::string, tree>::const_iterator it = map_of_function_decls.find(key); @@ -2617,13 +2614,13 @@ gg_define_function( tree return_type, } va_end(params); + char ach[32]; std::unordered_set<std::string>::const_iterator it = names_we_have_seen.find(funcname); if( it != names_we_have_seen.end() ) { static int bum_counter = 1; // We have seen this name before. Replace it with something unique: - char ach[32]; sprintf(ach, "..no_dupes.%d", bum_counter++); funcname = ach; } diff --git a/gcc/cobol/genmath.cc b/gcc/cobol/genmath.cc index 0a1c12d..e74aebd 100644 --- a/gcc/cobol/genmath.cc +++ b/gcc/cobol/genmath.cc @@ -52,7 +52,8 @@ set_up_on_exception_label(cbl_label_t *arithmetic_label) if( !arithmetic_label->structs.arith_error ) { arithmetic_label->structs.arith_error - = (cbl_arith_error_t *)xmalloc(sizeof(struct cbl_arith_error_t) ); + = static_cast<cbl_arith_error_t *> + (xmalloc(sizeof(struct cbl_arith_error_t))); // Set up the address pairs for this clause gg_create_goto_pair(&arithmetic_label->structs.arith_error->over.go_to, &arithmetic_label->structs.arith_error->over.label); @@ -72,8 +73,8 @@ set_up_compute_error_label(cbl_label_t *compute_label) if( !compute_label->structs.compute_error ) { compute_label->structs.compute_error - = (cbl_compute_error_t *) - xmalloc(sizeof(struct cbl_compute_error_t) ); + = static_cast<cbl_compute_error_t *> + (xmalloc(sizeof(struct cbl_compute_error_t))); compute_label->structs.compute_error->compute_error_code = gg_define_int(0); } @@ -112,7 +113,6 @@ arithmetic_operation(size_t nC, cbl_num_result_t *C, { TRACE1_HEADER TRACE1_TEXT_ABC("calling ", operation, "") - TRACE1_END for(size_t ii=0; ii<nA; ii++) { TRACE1_INDENT @@ -129,7 +129,6 @@ arithmetic_operation(size_t nC, cbl_num_result_t *C, build_int_cst_type(SIZE_T, ii)); TRACE1_REFER("", B[ii], ""); } - TRACE1_END } // We need to split up cbl_num_result_t into two arrays, one for the refer_t @@ -223,7 +222,6 @@ arithmetic_operation(size_t nC, cbl_num_result_t *C, { for(size_t ii=0; ii<nC; ii++) { - break; // Breaks on ADD 1 SUB2 GIVING SUB4 both PIC S9(3) COMP TRACE1_INDENT gg_fprintf( trace_handle, 1, "result: C[%ld]: ", @@ -663,8 +661,10 @@ fast_divide(size_t nC, cbl_num_result_t *C, // We now either divide into C[n] or assign dividend/divisor to C[n]: for(size_t i=0; i<nC; i++ ) { - tree dest_type = tree_type_from_size(C[i].refer.field->data.capacity, 0); - tree dest_addr = gg_add(member(C[i].refer.field->var_decl_node, "data"), + tree dest_type = + tree_type_from_size(C[i].refer.field->data.capacity, 0); + tree dest_addr = gg_add(member( C[i].refer.field->var_decl_node, + "data"), refer_offset(C[i].refer)); tree ptr = gg_cast(build_pointer_type(dest_type), dest_addr); if( nB ) @@ -680,16 +680,15 @@ fast_divide(size_t nC, cbl_num_result_t *C, } // This is where we handle any remainder, keeping in mind that for - // nB != 0, the actual dividend is in the value we have named "divisor". - // - // And, yes, I hate comments like that, too. + // nB != 0, the actual dividend is in the value we have named + // "divisor". // We calculate the remainder by calculating // dividend minus quotient * divisor if( remainder.field ) { - tree dest_addr = gg_add(member(remainder.field->var_decl_node, "data"), - refer_offset(remainder)); + dest_addr = gg_add( member(remainder.field->var_decl_node, "data"), + refer_offset(remainder)); dest_type = tree_type_from_size(remainder.field->data.capacity, 0); ptr = gg_cast(build_pointer_type(dest_type), dest_addr); diff --git a/gcc/cobol/genutil.cc b/gcc/cobol/genutil.cc index e09b1bf..20b47ab 100644 --- a/gcc/cobol/genutil.cc +++ b/gcc/cobol/genutil.cc @@ -307,7 +307,8 @@ get_and_check_refstart_and_reflen( tree refstart,// LONG returned value tree reflen, // LONG returned value cbl_refer_t &refer) { - cbl_enabled_exceptions_t& enabled_exceptions( cdf_enabled_exceptions() ); + const cbl_enabled_exceptions_t& + enabled_exceptions( cdf_enabled_exceptions() ); if( !enabled_exceptions.match(ec_bound_ref_mod_e) ) { @@ -460,7 +461,8 @@ get_depending_on_value_from_odo(tree retval, cbl_field_t *odo) declarative with a RESUME NEXT STATEMENT, or before the default_condition processing can do a controlled exit. */ - cbl_enabled_exceptions_t& enabled_exceptions( cdf_enabled_exceptions() ); + const cbl_enabled_exceptions_t& + enabled_exceptions( cdf_enabled_exceptions() ); cbl_field_t *depending_on; depending_on = cbl_field_of(symbol_at(odo->occurs.depending_on)); @@ -474,8 +476,8 @@ get_depending_on_value_from_odo(tree retval, cbl_field_t *odo) return; } - // Bounds checking is enabled, so we test the DEPENDING ON value to be between - // the lower and upper OCCURS limits: + // Bounds checking is enabled, so we test the DEPENDING ON value to be + // between the lower and upper OCCURS limits: get_integer_value(retval, depending_on, NULL, @@ -485,23 +487,28 @@ get_depending_on_value_from_odo(tree retval, cbl_field_t *odo) { // This needs to evaluate to an integer set_exception_code(ec_bound_odo_e); - gg_assign(retval, build_int_cst_type(TREE_TYPE(retval), odo->occurs.bounds.lower)); + gg_assign(retval, build_int_cst_type( TREE_TYPE(retval), + odo->occurs.bounds.lower)); gg_assign(var_decl_rdigits, integer_zero_node); } ELSE ENDIF - IF( retval, gt_op, build_int_cst_type(TREE_TYPE(retval), odo->occurs.bounds.upper) ) + IF( retval, gt_op, build_int_cst_type(TREE_TYPE(retval), + odo->occurs.bounds.upper) ) { set_exception_code(ec_bound_odo_e); - gg_assign(retval, build_int_cst_type(TREE_TYPE(retval), odo->occurs.bounds.lower)); + gg_assign(retval, build_int_cst_type( TREE_TYPE(retval), + odo->occurs.bounds.lower)); } ELSE { - IF( retval, lt_op, build_int_cst_type(TREE_TYPE(retval), odo->occurs.bounds.lower) ) + IF( retval, lt_op, build_int_cst_type(TREE_TYPE(retval), + odo->occurs.bounds.lower) ) { set_exception_code(ec_bound_odo_e); - gg_assign(retval, build_int_cst_type(TREE_TYPE(retval), odo->occurs.bounds.lower)); + gg_assign(retval, build_int_cst_type( TREE_TYPE(retval), + odo->occurs.bounds.lower)); } ELSE ENDIF @@ -551,7 +558,6 @@ get_data_offset(cbl_refer_t &refer, // We have a refer. // At the very least, we have an constant offset int all_flags = 0; - int all_flag_bit = 1; if( refer.nsubscript() ) { @@ -571,6 +577,7 @@ get_data_offset(cbl_refer_t &refer, // Establish the field_t pointer for walking up through our ancestors: cbl_field_t *parent = refer.field; + int all_flag_bit = 1; // Note the backwards test, because refer->nsubscript is an unsigned value for(size_t i=refer.nsubscript()-1; i<refer.nsubscript(); i-- ) { @@ -604,7 +611,8 @@ get_data_offset(cbl_refer_t &refer, } else { - cbl_enabled_exceptions_t& enabled_exceptions( cdf_enabled_exceptions() ); + const cbl_enabled_exceptions_t& + enabled_exceptions( cdf_enabled_exceptions() ); if( !enabled_exceptions.match(ec_bound_subscript_e) ) { // With no exception testing, just pick up the value @@ -629,21 +637,25 @@ get_data_offset(cbl_refer_t &refer, } ELSE { - IF( subscript, lt_op, gg_cast(TREE_TYPE(subscript), integer_one_node) ) + IF( subscript, lt_op, gg_cast(TREE_TYPE(subscript), + integer_one_node) ) { // The subscript is too small set_exception_code(ec_bound_subscript_e); - gg_assign(subscript, build_int_cst_type(TREE_TYPE(subscript), 1)); + gg_assign(subscript, build_int_cst_type(TREE_TYPE(subscript), + 1)); } ELSE { IF( subscript, ge_op, - build_int_cst_type(TREE_TYPE(subscript), parent->occurs.ntimes()) ) + build_int_cst_type( TREE_TYPE(subscript), + parent->occurs.ntimes()) ) { // The subscript is too large set_exception_code(ec_bound_subscript_e); - gg_assign(subscript, build_int_cst_type(TREE_TYPE(subscript), 1)); + gg_assign(subscript, build_int_cst_type(TREE_TYPE(subscript), + 1)); } ELSE { @@ -658,16 +670,19 @@ get_data_offset(cbl_refer_t &refer, all_flag_bit <<= 1; - // Although we strictly don't need to look at the ODO value at this point, - // we do want it checked for the purposes of ec-bound-odo + // Although we strictly don't need to look at the ODO value at this + // point, we do want it checked for the purposes of ec-bound-odo - cbl_enabled_exceptions_t& enabled_exceptions( cdf_enabled_exceptions() ); + const cbl_enabled_exceptions_t& + enabled_exceptions( cdf_enabled_exceptions() ); if( enabled_exceptions.match(ec_bound_odo_e) ) { if( parent->occurs.depending_on ) { - static tree value64 = gg_define_variable(LONG, ".._gdos_value64", vs_file_static); + static tree value64 = gg_define_variable( LONG, + ".._gdos_value64", + vs_file_static); cbl_field_t *odo = symbol_find_odo(parent); get_depending_on_value_from_odo(value64, odo); } @@ -1244,20 +1259,15 @@ get_binary_value( tree value, break; } - case FldAlphanumeric: - { - - } - - default: { - fprintf(stderr, "%s(): We know not how to" - " get a binary value from %s\n", - __func__, - cbl_field_type_str(field->type) ); + char *err = xasprintf("%s(): We know not how to" + " get a binary value from %s\n", + __func__, + cbl_field_type_str(field->type) ); + cbl_internal_error("%s", err); abort(); - break; + // break; // break not needed after abort(); } } @@ -1673,9 +1683,9 @@ set_exception_code_func(ec_type_t ec, int /*line*/, int from_raise_statement) } bool -process_this_exception(ec_type_t ec) +process_this_exception(const ec_type_t ec) { - cbl_enabled_exceptions_t& enabled_exceptions( cdf_enabled_exceptions() ); + const cbl_enabled_exceptions_t& enabled_exceptions( cdf_enabled_exceptions() ); bool retval; if( enabled_exceptions.match(ec) || !skip_exception_processing ) { @@ -1707,7 +1717,7 @@ copy_little_endian_into_place(cbl_field_t *dest, tree value, int rhs_rdigits, bool check_for_error, - tree &size_error) + const tree &size_error) { if( check_for_error ) { @@ -1933,7 +1943,7 @@ get_literal_string(cbl_field_t *field) } bool -refer_is_clean(cbl_refer_t &refer) +refer_is_clean(const cbl_refer_t &refer) { if( !refer.field || refer.field->type == FldLiteralN ) { @@ -1980,7 +1990,7 @@ refer_refmod_length(cbl_refer_t &refer) static tree // size_t -refer_fill_depends(cbl_refer_t &refer) +refer_fill_depends(const cbl_refer_t &refer) { REFER(""); // This returns a positive number which is the amount a depends-limited diff --git a/gcc/cobol/genutil.h b/gcc/cobol/genutil.h index 0d9028e..20783e1 100644 --- a/gcc/cobol/genutil.h +++ b/gcc/cobol/genutil.h @@ -118,7 +118,7 @@ void set_exception_code_func(ec_type_t ec, int line, int from_raise_statement=0); #define set_exception_code(ec) set_exception_code_func(ec, __LINE__) -bool process_this_exception(ec_type_t ec); +bool process_this_exception(const ec_type_t ec); #define CHECK_FOR_FRACTIONAL_DIGITS true void get_integer_value(tree value, // This is always a LONG cbl_field_t *field, @@ -130,7 +130,7 @@ void copy_little_endian_into_place(cbl_field_t *dest, tree value, int rhs_rdigits, bool check_for_error, - tree &size_error); + const tree &size_error); tree build_array_of_size_t( size_t N, const size_t *values); void parser_display_internal_field(tree file_descriptor, @@ -138,7 +138,7 @@ void parser_display_internal_field(tree file_descriptor, bool advance=DISPLAY_NO_ADVANCE); char *get_literal_string(cbl_field_t *field); -bool refer_is_clean(cbl_refer_t &refer); +bool refer_is_clean(const cbl_refer_t &refer); tree refer_offset(cbl_refer_t &refer, int *pflags=NULL); diff --git a/gcc/cobol/lexio.cc b/gcc/cobol/lexio.cc index dc632c2..52d1aff 100644 --- a/gcc/cobol/lexio.cc +++ b/gcc/cobol/lexio.cc @@ -344,7 +344,7 @@ check_push_pop_directive( filespan_t& mfile ) { std::swap(*mfile.eol, eol); // see implementation for excuses bool ok = regex_search(p, const_cast<const char *>(mfile.eol), cm, re); std::swap(*mfile.eol, eol); - + if( ok ) { gcc_assert(cm.size() > 1); bool push = TOUPPER(cm[1].first[1]) == 'U'; @@ -400,7 +400,7 @@ check_source_format_directive( filespan_t& mfile ) { std::swap(*mfile.eol, eol); // see implementation for excuses bool ok = regex_search(p, const_cast<const char *>(mfile.eol), cm, re); std::swap(*mfile.eol, eol); - + if( ok ) { gcc_assert(cm.size() > 1); switch( cm[3].length() ) { @@ -417,7 +417,7 @@ check_source_format_directive( filespan_t& mfile ) { dbgmsg( "%s:%d: %s format set, on line " HOST_SIZE_T_PRINT_UNSIGNED, __func__, __LINE__, - cdf_source_format().description(), + cdf_source_format().description(), (fmt_size_t)mfile.lineno() ); char *bol = cdf_source_format().is_fixed()? mfile.cur : const_cast<char*>(cm[0].first); gcc_assert(cm[0].second <= mfile.eol); @@ -941,7 +941,7 @@ location_in( const filespan_t& mfile, const csub_match& cm ) { gcc_assert(mfile.cur <= cm.first && cm.second <= mfile.eodata); auto nline = std::count(cm.first, cm.second, '\n'); if( nline ) { - gcc_assert(loc.first_line < nline); + gcc_assert(nline < loc.first_line); loc.first_line -= nline; auto p = static_cast<const char*>(memrchr(cm.first, '\n', cm.length())); loc.last_column = (cm.second) - p; @@ -1379,13 +1379,13 @@ lexer_input( char buf[], int max_size, FILE *input ) { for( auto p = mfile.cur; p < next; *output.pos++ = *p++ ) { static bool at_bol = false; if( at_bol ) { - auto nonblank = std::find_if( p, next, + auto nonblank_l = std::find_if( p, next, []( char ch ) { return !isblank(ch); } ); - if( nonblank + 1 < next ) { - if( *nonblank == '\r' ) nonblank++; // Windows - if( *nonblank == '\n' ) { - p = nonblank; + if( nonblank_l + 1 < next ) { + if( *nonblank_l == '\r' ) nonblank_l++; // Windows + if( *nonblank_l == '\n' ) { + p = nonblank_l; continue; } } @@ -1513,7 +1513,6 @@ cdftext::lex_open( const char filename[] ) { // Process any files supplied by the -include command-line option. for( auto name : included_files ) { - int input; if( -1 == (input = open(name, O_RDONLY)) ) { yyerrorvl(1, "", "cannot open -include file %s", name); continue; @@ -1686,7 +1685,7 @@ bool lexio_dialect_mf(); */ static const char * valid_sequence_area( const char *data, const char *eodata ) { - + for( const char *p = data; (p = std::find_if(p, eodata, is_p)) != eodata; p++ ) @@ -1709,7 +1708,7 @@ valid_sequence_area( const char *data, const char *eodata ) { } } } - return nullptr; + return nullptr; } /* @@ -1745,7 +1744,7 @@ cdftext::free_form_reference_format( int input ) { } current( mfile.data ); /* - * Infer source code format. + * Infer source code format. */ if( cdf_source_format().inference_pending() ) { const char *bol = valid_sequence_area(mfile.data, mfile.eodata); @@ -1983,15 +1982,15 @@ cdftext::segment_line( filespan_t& mfile ) { struct { unsigned long ante, post; } lineno = { gb4(mfile.lineno()), gb4(mfile.lineno() + segment.after.nlines()) }; - char *directive = lineno.ante == lineno.post? + const char *directive = lineno.ante == lineno.post? nullptr : xasprintf("\n#line %lu \"%s\"\n", lineno.ante, cobol_filename()); - if( directive ) + if( directive ) output.push_back( span_t(strlen(directive), directive) ); output.push_back( span_t(mfile.cur, segment.before.p) ); output.push_back( span_t(segment.after.p, segment.after.pend ) ); - if( directive ) + if( directive ) output.push_back( span_t(strlen(directive), directive) ); mfile.cur = const_cast<char*>(segment.before.pend); diff --git a/gcc/cobol/lexio.h b/gcc/cobol/lexio.h index eb41068..ba4ef0a 100644 --- a/gcc/cobol/lexio.h +++ b/gcc/cobol/lexio.h @@ -244,8 +244,8 @@ struct span_t { return span_t(output, eout); } const char * has_nul() const { - auto p = std::find(this->p, pend, '\0'); - return p != pend? p : NULL; + auto p_l = std::find(this->p, pend, '\0'); + return p_l != pend? p_l : NULL; } bool at_eol() const { diff --git a/gcc/cobol/scan_ante.h b/gcc/cobol/scan_ante.h index 88a8e8c..6128a3f 100644 --- a/gcc/cobol/scan_ante.h +++ b/gcc/cobol/scan_ante.h @@ -490,7 +490,8 @@ trim_location( int nkeep) { (fmt_size_t)nline, (fmt_size_t)rescan.size()); if( nline ) { gcc_assert( yylloc.first_line + nline <= yylloc.last_line ); - yylloc.last_line =- int(nline); + yylloc.last_line -= int(nline); + gcc_assert( yylloc.first_line <= yylloc.last_line ); char *p = static_cast<char*>(memrchr(rescan.p, '\n', rescan.size())); yylloc.last_column = rescan.pend - ++p; return; diff --git a/gcc/cobol/symbols.cc b/gcc/cobol/symbols.cc index 4b34729..aaaa6f3 100644 --- a/gcc/cobol/symbols.cc +++ b/gcc/cobol/symbols.cc @@ -500,13 +500,13 @@ symbol_elem_cmp( const void *K, const void *E ) } return strcasecmp(key.name, elem.name); } - break; + // break; // This break not needed if all options do a return. case SymSpecial: return special_pair_cmp(k->elem.special, e->elem.special)? 0 : 1; - break; + // break; // This break not needed after return. case SymAlphabet: return strcasecmp(k->elem.alphabet.name, e->elem.alphabet.name); - break; + // break; // This break not needed after return. case SymFile: // If the key is global, so must be the found element. if( (cbl_file_of(k)->attr & global_e) == global_e && @@ -514,7 +514,7 @@ symbol_elem_cmp( const void *K, const void *E ) return 1; } return strcasecmp(k->elem.file.name, e->elem.file.name); - break; + // break; // This break not needed after return. } assert(k->type == SymField); @@ -672,7 +672,7 @@ symbol_special( size_t program, const char name[] ) struct symbol_elem_t * symbol_alphabet( size_t program, const char name[] ) { - cbl_alphabet_t alphabet(YYLTYPE(), custom_encoding_e); + cbl_alphabet_t alphabet(YYLTYPE(), custom_encoding_e); // cppcheck-suppress syntaxError assert(strlen(name) < sizeof alphabet.name); strcpy(alphabet.name, name); @@ -931,7 +931,7 @@ end_of_group( size_t igroup ) { if( e->program != group->program ) return isym; if( e->type == SymLabel ) return isym; // end of data division if( e->type == SymField ) { - const auto f = cbl_field_of(e); + const cbl_field_t * f = cbl_field_of(e); if( f->level == LEVEL77 || f->level == 66 ) return isym; if( f->level == 1 && f->parent != igroup ) { return isym; @@ -1174,7 +1174,7 @@ static struct symbol_elem_t * // If an 01 record exists for the FD/SD, use its capacity as the // default_record capacity. if( p != symbols_end() ) { - const auto record = cbl_field_of(p); + const cbl_field_t * record = cbl_field_of(p); assert(record->level == 1); e = calculate_capacity(p); auto record_size = std::max(record->data.memsize, @@ -1262,7 +1262,7 @@ static struct symbol_elem_t * // If group has a parent that is a record area, expand it, too. if( 0 < group->parent ) { - auto redefined = symbol_redefines(group); + redefined = symbol_redefines(group); if( redefined && is_record_area(redefined) ) { if( redefined->data.capacity < group->data.memsize ) { redefined->data.capacity = group->data.memsize; @@ -1434,11 +1434,11 @@ cbl_field_t::attr_str( const std::vector<cbl_field_attr_t>& attrs ) const const char *sep = ""; char *out = NULL; - for( auto attr : attrs ) { + for( auto attr_l : attrs ) { char *part = out; - if( has_attr(attr) ) { + if( has_attr(attr_l) ) { int erc = asprintf(&out, "%s%s%s", - part? part : "", sep, cbl_field_attr_str(attr)); + part? part : "", sep, cbl_field_attr_str(attr_l)); if( -1 == erc ) return part; free(part); sep = ", "; @@ -1745,7 +1745,7 @@ symbols_update( size_t first, bool parsed_ok ) { bool size_invalid = field->data.memsize > 0 && symbol_redefines(field); if( size_invalid ) { // redefine of record area is ok - const auto redefined = symbol_redefines(field); + const cbl_field_t * redefined = symbol_redefines(field); size_invalid = ! is_record_area(redefined); } if( !field->is_valid() || size_invalid ) @@ -1828,7 +1828,7 @@ symbols_update( size_t first, bool parsed_ok ) { } // Verify REDEFINing field has no ODO components - const auto parent = symbol_redefines(field); + const cbl_field_t * parent = symbol_redefines(field); if( parent && !is_record_area(parent) && is_variable_length(field) ) { ERROR_FIELD(field, "line %d: REDEFINES field %s cannot be variable length", field->line, field->name); @@ -2470,7 +2470,7 @@ symbol_typedef_add( size_t program, struct cbl_field_t *field ) { auto e = symbols_end() - 1; assert( symbols_begin() < e ); if( e->type == SymField ) { - const auto f = cbl_field_of(e); + const cbl_field_t * f = cbl_field_of(e); if( f == field ) return e; } @@ -2520,7 +2520,8 @@ symbol_field_add( size_t program, struct cbl_field_t *field ) if( is_numeric(parent->usage) && parent->data.capacity > 0 ) { field->type = parent->usage; field->data = parent->data; - field->data = 0; + field->data = 0; // cppcheck-suppress redundantAssignment + // // cppcheck doesn't understand multiple overloaded operator= field->data.initial = NULL; } } @@ -3144,7 +3145,6 @@ static cbl_field_t * new_temporary_impl( enum cbl_field_type_t type, const cbl_name_t name = nullptr ) { extern int yylineno; - static int nstack, nliteral; static const struct cbl_field_t empty_alpha = { 0, FldAlphanumeric, FldInvalid, intermediate_e, 0, 0, 0, nonarray, 0, "", @@ -3213,8 +3213,10 @@ new_temporary_impl( enum cbl_field_type_t type, const cbl_name_t name = nullptr f->line = yylineno; if( is_literal(type) ) { + static int nliteral = 0; snprintf(f->name, sizeof(f->name), "_literal%d",++nliteral); } else { + static int nstack = 0; snprintf(f->name, sizeof(f->name), "_stack%d",++nstack); } @@ -3728,6 +3730,12 @@ symbol_label_add( size_t program, cbl_label_t *input ) bool symbol_label_section_exists( size_t eval_label_index ) { auto eval = symbols_begin(eval_label_index); + /* cppcheck warns that the following statement depends on the order of + evaluation of side effects. Since this isn't my code, and since I don't + think the warning can be eliminated without rewriting it, I am just + supprressing it. + -- Bob Dubner, 2025-07-14 */ + // cppcheck-suppress unknownEvaluationOrder bool has_section = std::any_of( ++eval, symbols_end(), [program = eval->program]( const auto& sym ) { if( program == sym.program && sym.type == SymLabel ) { @@ -4187,7 +4195,7 @@ symbol_program_callables( size_t program ) { if( e->type != SymLabel ) continue; if( e->elem.label.type != LblProgram ) continue; - const auto prog = cbl_label_of(e); + const cbl_label_t * prog = cbl_label_of(e); if( program == symbol_index(e) && !prog->recursive ) continue; if( (self->parent == prog->parent && prog->common) || @@ -4658,9 +4666,11 @@ file_status_status_of( file_status_t status ) { size_t n = COUNT_OF(file_status_fields); const file_status_field_t *fs, key { status }; - fs = (file_status_field_t*)lfind( &key, file_status_fields, - &n, sizeof(*fs), cbl_file_status_cmp ); - + fs = static_cast<file_status_field_t*>(lfind( &key, + file_status_fields, + &n, + sizeof(*fs), + cbl_file_status_cmp )); return fs? (long)fs->status : -1; } diff --git a/gcc/cobol/symfind.cc b/gcc/cobol/symfind.cc index c04bb0f..8141b22 100644 --- a/gcc/cobol/symfind.cc +++ b/gcc/cobol/symfind.cc @@ -48,7 +48,7 @@ extern int yydebug; static bool is_data_field( symbol_elem_t& e ) { if( e.type != SymField ) return false; - const auto f = cbl_field_of(&e); + const cbl_field_t *f = cbl_field_of(&e); if( f->name[0] == '\0' ) return false; if( is_filler(f) ) return false; @@ -129,7 +129,7 @@ finalize_symbol_map2() { for( auto& elem : symbol_map2 ) { auto& fields( elem.second ); fields.remove_if( []( auto isym ) { - const auto f = cbl_field_of(symbol_at(isym)); + const cbl_field_t *f = cbl_field_of(symbol_at(isym)); return f->type == FldInvalid; } ); if( fields.empty() ) empties.insert(elem.first); @@ -316,9 +316,9 @@ public: if( p != item.second.end() ) { // Preserve symbol's index at front of ancestor list. symbol_map_t::mapped_type shorter(1 + ancestors->size()); - auto p = shorter.begin(); - *p = item.second.front(); - shorter.insert( ++p, ancestors->begin(), ancestors->end() ); + auto p_l = shorter.begin(); + *p_l = item.second.front(); + shorter.insert( ++p_l, ancestors->begin(), ancestors->end() ); return make_pair(item.first, shorter); } } @@ -341,7 +341,7 @@ class in_scope { size_t program; static size_t prog_of( size_t program ) { - const auto L = cbl_label_of(symbol_at(program)); + const cbl_label_t *L = cbl_label_of(symbol_at(program)); return L->parent; } @@ -430,7 +430,7 @@ symbol_match2( size_t program, auto plist = symbol_map2.find(key); if( plist != symbol_map2.end() ) { for( auto candidate : plist->second ) { - const auto e = symbol_at(candidate); + const symbol_elem_t *e = symbol_at(candidate); if( name_has_names( e, names, local ) ) { fields.push_back( symbol_index(e) ); } diff --git a/gcc/cobol/util.cc b/gcc/cobol/util.cc index afa1597..6439f23 100644 --- a/gcc/cobol/util.cc +++ b/gcc/cobol/util.cc @@ -93,7 +93,7 @@ static inline char * get_current_dir_name () { /* Use libiberty's allocator here. */ - char *buf = (char *) xmalloc (PATH_MAX); + char *buf = static_cast<char *>(xmalloc (PATH_MAX)); return getcwd (buf, PATH_MAX); } #endif @@ -101,7 +101,7 @@ get_current_dir_name () /* * For printing messages, usually the size of the thing is some kind of string * length, and doesn't really need a size_t. For message formatting, use a - * simple unsigned long, and warn if that's no good. "gb4" here stands for + * simple unsigned long, and warn if that's no good. "gb4" here stands for * "4 Gigabytes". */ unsigned long @@ -113,7 +113,7 @@ gb4( size_t input ) { } return input; } - + /* * Most CDF Directives -- those that have state -- can be pushed and popped. * This class maintains stacks of them, with each stack having a "default @@ -140,20 +140,20 @@ gb4( size_t input ) { * PAGE * PROPAGATE * REF-MOD-ZERO-LENGTH - * - * >>PUSH ALL calls the class's push() method. - * >>POP ALL calls the class's pop() method. + * + * >>PUSH ALL calls the class's push() method. + * >>POP ALL calls the class's pop() method. */ class cdf_directives_t { template <typename T> - class cdf_stack_t : private std::stack<T> { + class cdf_stack_t : private std::stack<T> { // cppcheck-suppress noConstructor T default_value; const T& top() const { return std::stack<T>::top(); } bool empty() const { return std::stack<T>::empty(); } public: void value( const T& value ) { - T& output( empty()? default_value : std::stack<T>::top() ); + T& output( empty()? default_value : std::stack<T>::top() ); // cppcheck-suppress constVariableReference output = value; dbgmsg("cdf_directives_t::%s: %s", __func__, str(output).c_str()); } @@ -166,7 +166,7 @@ class cdf_directives_t } void pop() { if( empty() ) { - error_msg(YYLTYPE(), "CDF stack empty"); + error_msg(YYLTYPE(), "CDF stack empty"); // cppcheck-suppress syntaxError return; } default_value = top(); @@ -190,7 +190,6 @@ class cdf_directives_t static std::string str(cbl_enabled_exceptions_t) { return "<enabled_exceptions>"; } - }; public: @@ -203,7 +202,7 @@ class cdf_directives_t cdf_directives_t() { call_convention.value() = cbl_call_cobol_e; } - + void push() { call_convention.push(); cobol_words.push(); @@ -995,7 +994,7 @@ cbl_field_t::report_invalid_initial_value(const YYLTYPE& loc) const { // 8 or more, we need do no further testing because we assume // everything fits. if( data.capacity < 8 ) { - const auto p = strchr(data.initial, symbol_decimal_point()); + const char *p = strchr(data.initial, symbol_decimal_point()); if( p && atoll(p+1) != 0 ) { error_msg(loc, "integer type %s VALUE '%s' " "requires integer VALUE", @@ -1141,7 +1140,7 @@ literal_subscript_oob( const cbl_refer_t& r, size_t& isub /* output */) { pdim++; return ! occurs.subscript_ok(r.field); } ); - isub = psub - r.subscripts.begin(); + isub = psub - r.subscripts.begin(); return psub == r.subscripts.end()? NULL : dims[isub]; } @@ -1154,12 +1153,12 @@ cbl_refer_t::subscripts_set( const std::list<cbl_refer_t>& subs ) { const char * cbl_refer_t::str() const { - static char subscripts[64]; - sprintf(subscripts, "(%u of " HOST_SIZE_T_PRINT_UNSIGNED " dimensions)", + static char subscripts_l[64]; + sprintf(subscripts_l, "(%u of " HOST_SIZE_T_PRINT_UNSIGNED " dimensions)", nsubscript(), (fmt_size_t)dimensions(field)); char *output = xasprintf("%s %s %s", field? field_str(field) : "(none)", - 0 < dimensions(field)? subscripts : "", + 0 < dimensions(field)? subscripts_l : "", is_refmod_reference()? "(refmod)" : "" ); return output; } @@ -1861,12 +1860,13 @@ date_time_fmt( const char input[] ) { { regex_t(), 'd', "^(" DATE_FMT_B "|" DATE_FMT_E ")$" }, { regex_t(), 't', "^(" TIME_FMT_B "|" TIME_FMT_E ")$" }, }; - int erc, cflags = REG_EXTENDED | REG_ICASE, eflags=0; + int cflags = REG_EXTENDED | REG_ICASE, eflags=0; regmatch_t m[5]; char result = 0; if( ! compiled ) { for( auto& fmt : fmts ) { + int erc; if( (erc = regcomp(&fmt.reg, fmt.pattern, cflags)) != 0 ) { char msg[80]; regerror(erc, &fmt.reg, msg, sizeof(msg)); @@ -1924,7 +1924,7 @@ class unique_stack : public std::stack<input_file_t> friend void cobol_set_pp_option(int opt); bool option_m; std::set<std::string> all_names; - + const char * no_wd( const char *wd, const char *name ) { int i; @@ -1935,7 +1935,7 @@ class unique_stack : public std::stack<input_file_t> public: unique_stack() : option_m(false) {} - + bool push( const value_type& value ) { auto ok = std::none_of( c.cbegin(), c.cend(), [value]( const auto& that ) { @@ -1969,8 +1969,8 @@ class unique_stack : public std::stack<input_file_t> const input_file_t& peek( size_t n ) const { gcc_assert( n < size() ); return c.at(size() - ++n); - } - + } + void option( int opt ) { // capture other preprocessor options eventually assert(opt == 'M'); option_m = true; @@ -1983,7 +1983,7 @@ class unique_stack : public std::stack<input_file_t> std::string input( top().name ); printf( "%s: ", input.c_str() ); for( const auto& name : all_names ) { - if( name != input ) + if( name != input ) printf( "\\\n\t%s ", name.c_str() ); } printf("\n"); @@ -2000,7 +2000,7 @@ void cobol_set_pp_option(int opt) { assert(opt == 'M'); input_filenames.option_m = true; } - + /* * Maintain a stack of input filenames. Ensure the files are unique (by * inode), to prevent copybook cycles. Before pushing a new name, Record the @@ -2011,7 +2011,7 @@ void cobol_set_pp_option(int opt) { * to enforce uniqueness, and the scanner to maintain line numbers. */ bool cobol_filename( const char *name, ino_t inode ) { - const line_map *lines = NULL; + //const line_map *lines = NULL; if( inode == 0 ) { auto p = old_filenames.find(name); if( p == old_filenames.end() ) { @@ -2021,8 +2021,10 @@ bool cobol_filename( const char *name, ino_t inode ) { } cbl_errx( "logic error: missing inode for %s", name); } - inode = p->second; - assert(inode != 0); + else { + inode = p->second; + assert(inode != 0); + } } linemap_add(line_table, LC_ENTER, sysp, name, 1); input_filename_vestige = name; @@ -2071,7 +2073,7 @@ cobol_filename_restore() { input_filenames.pop(); if( input_filenames.empty() ) return; - auto& input = input_filenames.top(); + const auto& input = input_filenames.top(); linemap_add(line_table, LC_LEAVE, sysp, NULL, 0); } @@ -2083,7 +2085,7 @@ location_t location_from_lineno() { return token_location; } template <typename LOC> static void gcc_location_set_impl( const LOC& loc ) { - // Set the position to the first line & column in the location. + // Set the position to the first line & column in the location. token_location = linemap_line_start( line_table, loc.first_line, 80 ); token_location = linemap_position_for_column( line_table, loc.first_column); location_dump(__func__, __LINE__, "parser", loc); @@ -2144,8 +2146,8 @@ ydferror( const char gmsgid[], ... ) { va_list ap; va_start (ap, gmsgid); rich_location richloc (line_table, token_location); - bool ret = global_dc->diagnostic_impl (&richloc, nullptr, option_zero, - gmsgid, &ap, DK_ERROR); + /*bool ret =*/ global_dc->diagnostic_impl (&richloc, nullptr, option_zero, + gmsgid, &ap, DK_ERROR); va_end (ap); } @@ -2222,8 +2224,8 @@ void error_msg_direct( const char gmsgid[], ... ) { auto_diagnostic_group d; va_list ap; va_start (ap, gmsgid); - auto ret = emit_diagnostic_valist( DK_ERROR, token_location, - option_zero, gmsgid, &ap ); + /*auto ret = */emit_diagnostic_valist( DK_ERROR, token_location, + option_zero, gmsgid, &ap ); va_end (ap); } @@ -2236,8 +2238,11 @@ yyerror( const char gmsgid[], ... ) { va_list ap; va_start (ap, gmsgid); rich_location richloc (line_table, token_location); - bool ret = global_dc->diagnostic_impl (&richloc, nullptr, option_zero, - gmsgid, &ap, DK_ERROR); + /*bool ret =*/ global_dc->diagnostic_impl ( &richloc, + nullptr, + option_zero, + gmsgid, + &ap, DK_ERROR); va_end (ap); global_dc->end_group(); } @@ -2483,8 +2488,8 @@ cbl_unimplemented_at( const YYLTYPE& loc, const char *gmsgid, ... ) { va_end(ap); } -/* - * analogs to err(3) and errx(3). +/* + * analogs to err(3) and errx(3). */ #pragma GCC diagnostic push @@ -2619,7 +2624,7 @@ static const std::set<std::string> reserved_words = { "VOLATILE", "XML", "END-START", - + // ISO 2023 keywords "ACCEPT", "ACCESS", diff --git a/gcc/config.in b/gcc/config.in index ab62c15..353d1bc 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -318,6 +318,12 @@ #endif +/* Define to enable -mfentry by default on x86-64. */ +#ifndef USED_FOR_TARGET +#undef ENABLE_X86_64_MFENTRY +#endif + + /* Define to the name of a file containing a list of extra machine modes for this architecture. */ #ifndef USED_FOR_TARGET diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md index b8bb4cc..bfe368e 100644 --- a/gcc/config/aarch64/aarch64-sme.md +++ b/gcc/config/aarch64/aarch64-sme.md @@ -38,6 +38,7 @@ ;; ---- Binary arithmetic on ZA tile ;; ---- Binary arithmetic on ZA slice ;; ---- Binary arithmetic, writing to ZA slice +;; ---- Absolute minimum/maximum ;; ;; == Ternary arithmetic ;; ---- [INT] Dot product @@ -1264,6 +1265,23 @@ "<sme_int_op>\tza.<Vetype>[%w0, %1, vgx<vector_count>], %2, %3.<Vetype>" ) +;; ------------------------------------------------------------------------- +;; ---- Absolute minimum/maximum +;; ------------------------------------------------------------------------- +;; Includes: +;; - svamin (SME2+faminmax) +;; - svamin (SME2+faminmax) +;; ------------------------------------------------------------------------- + +(define_insn "@aarch64_sme_<faminmax_uns_op><mode>" + [(set (match_operand:SVE_Fx24 0 "register_operand" "=Uw<vector_count>") + (unspec:SVE_Fx24 [(match_operand:SVE_Fx24 1 "register_operand" "%0") + (match_operand:SVE_Fx24 2 "register_operand" "Uw<vector_count>")] + FAMINMAX_UNS))] + "TARGET_SME2 && TARGET_FAMINMAX" + "<faminmax_uns_op>\t%0, %1, %2" +) + ;; ========================================================================= ;; == Ternary arithmetic ;; ========================================================================= diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def b/gcc/config/aarch64/aarch64-sve-builtins-sme.def index f75c0a5..8e6aadc 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def @@ -92,6 +92,11 @@ DEF_SME_FUNCTION (svstr_zt, str_zt, none, none) DEF_SME_FUNCTION (svzero_zt, inherent_zt, none, none) #undef REQUIRED_EXTENSIONS +#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2 && AARCH64_FL_FAMINMAX) +DEF_SME_FUNCTION_GS (svamin, binary_opt_single_n, all_float, x24, none) +DEF_SME_FUNCTION_GS (svamax, binary_opt_single_n, all_float, x24, none) +#undef REQUIRED_EXTENSIONS + /* The d_za entries in this section just declare C _za64 overloads, which will then be resolved to either an integer function or a floating-point function. They are needed because the integer and diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc index abe21a8..73004a8 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc @@ -930,6 +930,44 @@ public: unsigned int m_bits; }; +/* The same as cond_or_uncond_unspec_function but the intrinsics with vector + modes are SME2 extensions instead of SVE. */ +class faminmaximpl : public function_base +{ +public: + CONSTEXPR faminmaximpl (int cond_unspec, int uncond_unspec) + : m_cond_unspec (cond_unspec), m_uncond_unspec (uncond_unspec) + {} + + rtx + expand (function_expander &e) const override + { + if (e.group_suffix ().vectors_per_tuple > 1) + { + /* SME2+faminmax intrinsics. */ + gcc_assert (e.pred == PRED_none); + auto mode = e.tuple_mode (0); + auto icode = (code_for_aarch64_sme (m_uncond_unspec, mode)); + return e.use_exact_insn (icode); + } + /* SVE+faminmax intrinsics. */ + else if (e.pred == PRED_none) + { + auto mode = e.tuple_mode (0); + auto icode = (e.mode_suffix_id == MODE_single + ? code_for_aarch64_sve_single (m_uncond_unspec, mode) + : code_for_aarch64_sve (m_uncond_unspec, mode)); + return e.use_exact_insn (icode); + } + return e.map_to_unspecs (m_cond_unspec, m_cond_unspec, m_cond_unspec); + } + + /* The unspecs for the conditional and unconditional instructions, + respectively. */ + int m_cond_unspec; + int m_uncond_unspec; +}; + } /* end anonymous namespace */ namespace aarch64_sve { @@ -958,10 +996,8 @@ FUNCTION (svaesd, fixed_insn_function, (CODE_FOR_aarch64_sve2_aesd)) FUNCTION (svaese, fixed_insn_function, (CODE_FOR_aarch64_sve2_aese)) FUNCTION (svaesimc, fixed_insn_function, (CODE_FOR_aarch64_sve2_aesimc)) FUNCTION (svaesmc, fixed_insn_function, (CODE_FOR_aarch64_sve2_aesmc)) -FUNCTION (svamax, cond_or_uncond_unspec_function, - (UNSPEC_COND_FAMAX, UNSPEC_FAMAX)) -FUNCTION (svamin, cond_or_uncond_unspec_function, - (UNSPEC_COND_FAMIN, UNSPEC_FAMIN)) +FUNCTION (svamax, faminmaximpl, (UNSPEC_COND_FAMAX, UNSPEC_FAMAX)) +FUNCTION (svamin, faminmaximpl, (UNSPEC_COND_FAMIN, UNSPEC_FAMIN)) FUNCTION (svandqv, reduction, (UNSPEC_ANDQV, UNSPEC_ANDQV, -1)) FUNCTION (svbcax, CODE_FOR_MODE0 (aarch64_sve2_bcax),) FUNCTION (svbdep, unspec_based_function, (UNSPEC_BDEP, UNSPEC_BDEP, -1)) diff --git a/gcc/config/darwin-driver.cc b/gcc/config/darwin-driver.cc index 224e0a0..e83b7cd 100644 --- a/gcc/config/darwin-driver.cc +++ b/gcc/config/darwin-driver.cc @@ -64,7 +64,8 @@ validate_macosx_version_min (const char *version_str) major = strtoul (version_str, &end, 10); - /* macOS 10, 11, and 12 are known. clang accepts up to 99. */ + /* macOS 10, 11, 12, 13, 14, 15 and 26 are known. + clang accepts up to 99. */ if (major < 10 || major > 99) return NULL; @@ -159,15 +160,16 @@ darwin_find_version_from_kernel (void) if (*version_p++ != '.') goto parse_failed; - /* Darwin20 sees a transition to macOS 11. In this, it seems that the - mapping to macOS minor version and patch level is now always 0, 0 - (at least for macOS 11 and 12). */ - if (major_vers >= 20) - { - /* Apple clang doesn't include the minor version or the patch level - in the object file, nor does it pass it to ld */ - asprintf (&new_flag, "%d.00.00", major_vers - 9); - } + /* Darwin25 saw a transition to macOS 26. */ + if (major_vers >= 25) + /* Apple clang doesn't include the minor version or the patch level + in the object file, nor does it pass it to ld */ + asprintf (&new_flag, "%d.00.00", major_vers + 1); + /* Darwin20 saw a transition to macOS 11. */ + else if (major_vers >= 20) + /* Apple clang doesn't include the minor version or the patch level + in the object file, nor does it pass it to ld */ + asprintf (&new_flag, "%d.00.00", major_vers - 9); else if (major_vers - 4 <= 4) /* On 10.4 and earlier, the old linker is used which does not support three-component system versions. diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 4b21302..71a3916 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -1455,28 +1455,26 @@ ;; }}} ;; {{{ ALU special case: add/sub -(define_insn "add<mode>3<exec_clobber>" +(define_insn "add<mode>3<exec>" [(set (match_operand:V_INT_1REG 0 "register_operand") (plus:V_INT_1REG (match_operand:V_INT_1REG 1 "register_operand") - (match_operand:V_INT_1REG 2 "gcn_alu_operand"))) - (clobber (reg:DI VCC_REG))] + (match_operand:V_INT_1REG 2 "gcn_alu_operand")))] "" {@ [cons: =0, %1, 2; attrs: type, length] - [v,v,vSvA;vop2,4] v_add_co_u32\t%0, vcc, %2, %1 + [v,v,vSvA;vop2,4] {v_add_u32|v_add_nc_u32}\t%0, %2, %1 [v,v,vSvB;vop2,8] ^ }) -(define_insn "add<mode>3_dup<exec_clobber>" +(define_insn "add<mode>3_dup<exec>" [(set (match_operand:V_INT_1REG 0 "register_operand") (plus:V_INT_1REG (vec_duplicate:V_INT_1REG (match_operand:<SCALAR_MODE> 2 "gcn_alu_operand")) - (match_operand:V_INT_1REG 1 "register_operand"))) - (clobber (reg:DI VCC_REG))] + (match_operand:V_INT_1REG 1 "register_operand")))] "" {@ [cons: =0, 1, 2; attrs: type, length] - [v,v,SvA;vop2,4] v_add_co_u32\t%0, vcc, %2, %1 + [v,v,SvA;vop2,4] {v_add_u32|v_add_nc_u32}\t%0, %2, %1 [v,v,SvB;vop2,8] ^ }) @@ -1551,16 +1549,15 @@ [(set_attr "type" "vop2,vop3b") (set_attr "length" "4,8")]) -(define_insn "sub<mode>3<exec_clobber>" +(define_insn "sub<mode>3<exec>" [(set (match_operand:V_INT_1REG 0 "register_operand" "= v, v") (minus:V_INT_1REG (match_operand:V_INT_1REG 1 "gcn_alu_operand" "vSvB, v") - (match_operand:V_INT_1REG 2 "gcn_alu_operand" " v,vSvB"))) - (clobber (reg:DI VCC_REG))] + (match_operand:V_INT_1REG 2 "gcn_alu_operand" " v,vSvB")))] "" "@ - v_sub_co_u32\t%0, vcc, %1, %2 - v_subrev_co_u32\t%0, vcc, %2, %1" + {v_sub_u32|v_sub_nc_u32}\t%0, %1, %2 + {v_subrev_u32|v_subrev_nc_u32}\t%0, %2, %1" [(set_attr "type" "vop2") (set_attr "length" "8,8")]) @@ -3795,9 +3792,9 @@ /* Unsigned comparisons use the same patterns as signed comparisons, except that they use unsigned operators (e.g. LTU vs LT). The '%E1' directive then does the Right Thing. */ - emit_insn (gen_vec_cmpu<mode>di_exec (operands[0], operands[1], - operands[2], operands[3], - operands[4])); + emit_insn (gen_vec_cmp<mode>di_exec (operands[0], operands[1], + operands[2], operands[3], + operands[4])); DONE; }) diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index 2ce2e05..9193461 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -1136,14 +1136,13 @@ [(set (match_operand:SI 0 "register_operand" "= Sg, Sg, Sg, v") (plus:SI (match_operand:SI 1 "gcn_alu_operand" "%SgA, 0,SgA, v") (match_operand:SI 2 "gcn_alu_operand" " SgA,SgJ, B,vBSv"))) - (clobber (match_scratch:BI 3 "= cs, cs, cs, X")) - (clobber (match_scratch:DI 4 "= X, X, X, cV"))] + (clobber (match_scratch:BI 3 "= cs, cs, cs, X"))] "" "@ s_add_i32\t%0, %1, %2 s_addk_i32\t%0, %2 s_add_i32\t%0, %1, %2 - v_add_co_u32\t%0, vcc, %2, %1" + {v_add_u32|v_add_nc_u32}\t%0, %2, %1" [(set_attr "type" "sop2,sopk,sop2,vop2") (set_attr "length" "4,4,8,8")]) @@ -1151,8 +1150,7 @@ [(parallel [(set (match_operand:SI 0 "register_operand") (plus:SI (match_operand:SI 1 "gcn_alu_operand") (match_operand:SI 2 "gcn_alu_operand"))) - (clobber (reg:BI SCC_REG)) - (clobber (scratch:DI))])] + (clobber (reg:BI SCC_REG))])] "" {}) @@ -1332,14 +1330,13 @@ [(set (match_operand:SI 0 "register_operand" "=Sg, Sg, v, v") (minus:SI (match_operand:SI 1 "gcn_alu_operand" "SgA,SgA, v,vBSv") (match_operand:SI 2 "gcn_alu_operand" "SgA, B, vBSv, v"))) - (clobber (match_scratch:BI 3 "=cs, cs, X, X")) - (clobber (match_scratch:DI 4 "= X, X, cV, cV"))] + (clobber (match_scratch:BI 3 "=cs, cs, X, X"))] "" "@ s_sub_i32\t%0, %1, %2 s_sub_i32\t%0, %1, %2 - v_subrev_co_u32\t%0, vcc, %2, %1 - v_sub_co_u32\t%0, vcc, %1, %2" + {v_subrev_u32|v_subrev_nc_u32}\t%0, %2, %1 + {v_sub_u32|v_sub_nc_u32}\t%0, %1, %2" [(set_attr "type" "sop2,sop2,vop2,vop2") (set_attr "length" "4,8,8,8")]) @@ -1569,8 +1566,7 @@ (mult:DI (match_operand:DI 1 "register_operand" "%Sg, Sg, v, v") (match_operand:DI 2 "nonmemory_operand" "Sg, i,vSv, A"))) (clobber (match_scratch:SI 3 "=&Sg,&Sg,&v,&v")) - (clobber (match_scratch:BI 4 "=cs, cs, X, X")) - (clobber (match_scratch:DI 5 "=X, X,cV,cV"))] + (clobber (match_scratch:BI 4 "=cs, cs, X, X"))] "" "#" "reload_completed" @@ -1585,15 +1581,13 @@ emit_insn (gen_umulsidi3 (operands[0], op1lo, op2lo)); emit_insn (gen_mulsi3 (tmp, op1lo, op2hi)); rtx add = gen_rtx_SET (dsthi, gen_rtx_PLUS (SImode, dsthi, tmp)); - rtx clob1 = gen_rtx_CLOBBER (VOIDmode, operands[4]); - rtx clob2 = gen_rtx_CLOBBER (VOIDmode, operands[5]); - add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, add, clob1, clob2)); + rtx clob = gen_rtx_CLOBBER (VOIDmode, operands[4]); + add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, add, clob)); emit_insn (add); emit_insn (gen_mulsi3 (tmp, op1hi, op2lo)); add = gen_rtx_SET (dsthi, gen_rtx_PLUS (SImode, dsthi, tmp)); - clob1 = gen_rtx_CLOBBER (VOIDmode, operands[4]); - clob2 = gen_rtx_CLOBBER (VOIDmode, operands[5]); - add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, add, clob1, clob2)); + clob = gen_rtx_CLOBBER (VOIDmode, operands[4]); + add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, add, clob)); emit_insn (add); DONE; }) diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc index 054f8d5..734ab70 100644 --- a/gcc/config/i386/i386-features.cc +++ b/gcc/config/i386/i386-features.cc @@ -3534,22 +3534,20 @@ ix86_broadcast_inner (rtx op, machine_mode mode, machine_mode *scalar_mode_p, x86_cse_kind *kind_p, rtx_insn **insn_p) { - if (op == const0_rtx || op == CONST0_RTX (mode)) + switch (standard_sse_constant_p (op, mode)) { + case 1: *scalar_mode_p = QImode; *kind_p = X86_CSE_CONST0_VECTOR; *insn_p = nullptr; return const0_rtx; - } - else if ((GET_MODE_CLASS (mode) == MODE_VECTOR_INT - && (op == constm1_rtx || op == CONSTM1_RTX (mode))) - || (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT - && float_vector_all_ones_operand (op, mode))) - { + case 2: *scalar_mode_p = QImode; *kind_p = X86_CSE_CONSTM1_VECTOR; *insn_p = nullptr; return constm1_rtx; + default: + break; } mode = GET_MODE (op); diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 09cb133..5365849 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -2839,7 +2839,9 @@ ix86_option_override_internal (bool main_args_p, /* Set the default value for -mfentry. */ if (!opts_set->x_flag_fentry) - opts->x_flag_fentry = TARGET_SEH; + opts->x_flag_fentry = (TARGET_SEH + || (TARGET_64BIT_P (opts->x_ix86_isa_flags) + && ENABLE_X86_64_MFENTRY)); else { if (!TARGET_64BIT_P (opts->x_ix86_isa_flags) && opts->x_flag_pic @@ -2850,6 +2852,13 @@ ix86_option_override_internal (bool main_args_p, sorry ("%<-mno-fentry%> isn%'t compatible with SEH"); } + if (!opts->x_flag_fentry + && (TARGET_64BIT_P (opts->x_ix86_isa_flags) || !opts->x_flag_pic) + && opts->x_flag_shrink_wrap + && opts->x_profile_flag) + warning (0, "%<-pg%> without %<-mfentry%> may be unreliable with " + "shrink wrapping"); + if (TARGET_SEH && TARGET_CALL_MS2SYSV_XLOGUES) sorry ("%<-mcall-ms2sysv-xlogues%> isn%'t currently supported with SEH"); diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 3f7ad68..bfc6c6f 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2465,10 +2465,11 @@ constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_ALDERLAKE | PTA_AVXIFMA | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_UINTR; constexpr wide_int_bitmask PTA_ARROWLAKE_S = PTA_ARROWLAKE | PTA_AVXVNNIINT16 | PTA_SHA512 | PTA_SM3 | PTA_SM4; -constexpr wide_int_bitmask PTA_CLEARWATERFOREST = PTA_SIERRAFOREST - | PTA_AVXVNNIINT16 | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_USER_MSR - | PTA_PREFETCHI; -constexpr wide_int_bitmask PTA_PANTHERLAKE = PTA_ARROWLAKE_S | PTA_PREFETCHI; +constexpr wide_int_bitmask PTA_CLEARWATERFOREST = + (PTA_SIERRAFOREST & (~(PTA_KL | PTA_WIDEKL))) | PTA_AVXVNNIINT16 | PTA_SHA512 + | PTA_SM3 | PTA_SM4 | PTA_USER_MSR | PTA_PREFETCHI; +constexpr wide_int_bitmask PTA_PANTHERLAKE = + (PTA_ARROWLAKE_S & (~(PTA_KL | PTA_WIDEKL))) | PTA_PREFETCHI; constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_GRANITERAPIDS_D | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 | PTA_AVXVNNIINT8 | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2 diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 8df7f64..f372f0e 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1725,6 +1725,8 @@ ;; - vfmsac.vf ;; - vfnmacc.vf ;; - vfnmsac.vf +;; - vfwmacc.vf +;; - vfwmsac.vf ;; ============================================================================= ;; vfmadd.vf, vfmsub.vf, vfmacc.vf, vfmsac.vf @@ -1796,3 +1798,49 @@ } [(set_attr "type" "vfmuladd")] ) + +;; vfwmacc.vf, vfwmsac.vf +(define_insn_and_split "*vfwmacc_vf_<mode>" + [(set (match_operand:VWEXTF 0 "register_operand") + (plus_minus:VWEXTF + (mult:VWEXTF + (float_extend:VWEXTF + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand")) + (vec_duplicate:VWEXTF + (float_extend:<VEL> + (match_operand:<VSUBEL> 2 "register_operand")))) + (match_operand:VWEXTF 1 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + rtx ops[] = {operands[0], operands[1], operands[2], operands[3]}; + riscv_vector::emit_vlmax_insn (code_for_pred_widen_mul_scalar (<CODE>, <MODE>mode), + riscv_vector::WIDEN_TERNARY_OP_FRM_DYN, ops); + DONE; + } + [(set_attr "type" "vfwmuladd")] +) + +;; Intermediate pattern for vfwmacc.vf and vfwmsac.vf used by combine +(define_insn_and_split "*extend_vf_<mode>" + [(set (match_operand:VWEXTF 0 "register_operand") + (vec_duplicate:VWEXTF + (float_extend:<VEL> + (match_operand:<VSUBEL> 1 "register_operand"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + rtx tmp = gen_reg_rtx (<VEL>mode); + emit_insn (gen_extend<vsubel><vel>2(tmp, operands[1])); + + rtx ops[] = {operands[0], tmp}; + riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode), + riscv_vector::UNARY_OP, ops); + DONE; + } + [(set_attr "type" "vfwmuladd")] +) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index e60e3a8..5f6cc42 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -2418,6 +2418,47 @@ (RVVM1x2DF "rvvm1df") ]) +(define_mode_attr vsubel [ + (RVVM8HI "qi") (RVVM4HI "qi") (RVVM2HI "qi") (RVVM1HI "qi") (RVVMF2HI "qi") (RVVMF4HI "qi") + + (RVVM8SI "hi") (RVVM4SI "hi") (RVVM2SI "hi") (RVVM1SI "hi") (RVVMF2SI "hi") + + (RVVM8SF "hf") (RVVM4SF "hf") (RVVM2SF "hf") (RVVM1SF "hf") (RVVMF2SF "hf") + + (RVVM8DI "si") (RVVM4DI "si") (RVVM2DI "si") (RVVM1DI "si") + + (RVVM8DF "sf") (RVVM4DF "sf") (RVVM2DF "sf") (RVVM1DF "sf") + + ;; VLS modes. + (V1HI "qi") (V2HI "qi") (V4HI "qi") (V8HI "qi") (V16HI "qi") (V32HI "qi") (V64HI "qi") (V128HI "qi") (V256HI "qi") + (V512HI "qi") (V1024HI "qi") (V2048HI "qi") + (V1SI "hi") (V2SI "hi") (V4SI "hi") (V8SI "hi") (V16SI "hi") (V32SI "hi") (V64SI "hi") (V128SI "hi") (V256SI "hi") + (V512SI "hi") (V1024SI "hi") + (V1DI "si") (V2DI "si") (V4DI "si") (V8DI "si") (V16DI "si") (V32DI "si") (V64DI "si") (V128DI "si") (V256DI "si") (V512DI "si") + + (V1SF "hf") + (V2SF "hf") + (V4SF "hf") + (V8SF "hf") + (V16SF "hf") + (V32SF "hf") + (V64SF "hf") + (V128SF "hf") + (V256SF "hf") + (V512SF "hf") + (V1024SF "hf") + (V1DF "sf") + (V2DF "sf") + (V4DF "sf") + (V8DF "sf") + (V16DF "sf") + (V32DF "sf") + (V64DF "sf") + (V128DF "sf") + (V256DF "sf") + (V512DF "sf") +]) + (define_mode_attr VSUBEL [ (RVVM8HI "QI") (RVVM4HI "QI") (RVVM2HI "QI") (RVVM1HI "QI") (RVVMF2HI "QI") (RVVMF4HI "QI") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index c5b23b3..baf215b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7299,10 +7299,10 @@ (plus_minus:VWEXTF (mult:VWEXTF (float_extend:VWEXTF - (vec_duplicate:<V_DOUBLE_TRUNC> - (match_operand:<VSUBEL> 3 "register_operand" " f"))) - (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))) + (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")) + (vec_duplicate:VWEXTF + (float_extend:<VEL> + (match_operand:<VSUBEL> 3 "register_operand" " f")))) (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc index de9c15c..737b176 100644 --- a/gcc/config/s390/s390.cc +++ b/gcc/config/s390/s390.cc @@ -16566,9 +16566,6 @@ s390_option_override_internal (struct gcc_options *opts, else SET_OPTION_IF_UNSET (opts, opts_set, param_vect_partial_vector_usage, 0); - /* Do not vectorize loops with a low trip count for now. */ - SET_OPTION_IF_UNSET (opts, opts_set, param_min_vect_loop_bound, 2); - /* Set the default alignment. */ s390_default_align (opts); diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 26753c0..c63360f 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -3572,11 +3572,6 @@ "veval\t%v0,%v1,%v2,%v3,%b4" [(set_attr "op_type" "VRI")]) -; reduc_smin -; reduc_smax -; reduc_umin -; reduc_umax - ; vec_pack_sfix_trunc: convert + pack ? ; vec_pack_ufix_trunc ; vec_unpacks_float_hi @@ -3627,3 +3622,291 @@ (const_int 4)] UNSPEC_FMIN))] "TARGET_VXE") + +; reduc_plus +(define_expand "reduc_plus_scal_<mode>" + [(set (match_dup 4) + (unspec:V4SI [(match_operand:VI_HW_QH 1 "register_operand") + (match_dup 2)] + UNSPEC_VEC_VSUM)) + (set (match_dup 5) + (unspec:V2DI [(match_dup 4) (match_dup 3)] UNSPEC_VEC_VSUMQ)) + (set (match_operand:<non_vec> 0 "register_operand") + (vec_select:<non_vec> (match_dup 6) + (parallel [(match_dup 7)])))] + "TARGET_VX" +{ + operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode)); + operands[3] = simplify_gen_subreg (V4SImode, operands[2], <MODE>mode, 0); + operands[4] = gen_reg_rtx (V4SImode); + operands[5] = gen_reg_rtx (V2DImode); + operands[6] = simplify_gen_subreg (<MODE>mode, operands[5], V2DImode, 0); + operands[7] = GEN_INT (16 / GET_MODE_SIZE (<non_vec>mode) - 1); +}) + +(define_expand "reduc_plus_scal_<mode>" + [(set (match_dup 3) + (unspec:V2DI [(match_operand:VI_HW_SD 1 "register_operand") + (match_dup 2)] + UNSPEC_VEC_VSUMQ)) + (set (match_operand:<non_vec> 0 "register_operand") + (vec_select:<non_vec> (match_dup 4) + (parallel [(match_dup 5)])))] + "TARGET_VX" +{ + operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode)); + operands[3] = gen_reg_rtx (V2DImode); + operands[4] = simplify_gen_subreg (<MODE>mode, operands[3], V2DImode, 0); + operands[5] = GEN_INT (16 / GET_MODE_SIZE (<non_vec>mode) - 1); +}) + +(define_expand "reduc_plus_scal_v2df" + [(set (match_dup 2) + (unspec:V2DF [(match_operand:V2DF 1 "register_operand") + (match_dup 1) + (const_int 8)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 3) (plus:V2DF (match_dup 1) (match_dup 2))) + (set (match_operand:DF 0 "register_operand") + (vec_select:DF (match_dup 3) (parallel [(const_int 0)])))] + "TARGET_VX" +{ + operands[2] = gen_reg_rtx (V2DFmode); + operands[3] = gen_reg_rtx (V2DFmode); +}) + +(define_expand "reduc_plus_scal_v4sf" + [(set (match_dup 2) + (unspec:V4SF [(match_operand:V4SF 1 "register_operand") + (match_dup 1) + (const_int 4)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 3) (plus:V4SF (match_dup 1) (match_dup 2))) + (set (match_dup 4) + (unspec:V4SF [(match_dup 3) (match_dup 3) (const_int 8)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 5) (plus:V4SF (match_dup 3) (match_dup 4))) + (set (match_operand:SF 0 "register_operand") + (vec_select:SF (match_dup 5) (parallel [(const_int 0)])))] + "TARGET_VXE" +{ + operands[2] = gen_reg_rtx (V4SFmode); + operands[3] = gen_reg_rtx (V4SFmode); + operands[4] = gen_reg_rtx (V4SFmode); + operands[5] = gen_reg_rtx (V4SFmode); +}) + +; reduc_fmin, reduc_fmax, reduc_smin, reduc_smax + +(define_int_iterator REDUC_FMINMAX [UNSPEC_FMAX UNSPEC_FMIN]) +(define_int_attr reduc_fminmax_name [(UNSPEC_FMAX "fmax") (UNSPEC_FMIN "fmin")]) +(define_code_iterator REDUC_MINMAX [smin smax]) +(define_code_attr reduc_minmax_name [(smin "smin") (smax "smax")]) + +(define_expand "reduc_<reduc_fminmax_name>_scal_v2df" + [(set (match_dup 2) + (unspec:V2DF [(match_operand:V2DF 1 "register_operand") + (match_dup 1) + (const_int 8)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 3) + (unspec:V2DF [(match_dup 1) (match_dup 2) (const_int 4)] REDUC_FMINMAX)) + (set (match_operand:DF 0 "register_operand" "") + (vec_select:DF (match_dup 3) (parallel [(const_int 0)])))] + "TARGET_VX" +{ + operands[2] = gen_reg_rtx (V2DFmode); + operands[3] = gen_reg_rtx (V2DFmode); +}) + +(define_expand "reduc_<reduc_fminmax_name>_scal_v4sf" + [(set (match_dup 2) + (unspec:V4SF [(match_operand:V4SF 1 "register_operand") + (match_dup 1) + (const_int 4)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 3) + (unspec:V4SF [(match_dup 1) (match_dup 2) (const_int 4)] REDUC_FMINMAX)) + (set (match_dup 4) + (unspec:V4SF [(match_dup 3) + (match_dup 3) + (const_int 8)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 5) + (unspec:V4SF [(match_dup 3) (match_dup 4) (const_int 4)] REDUC_FMINMAX)) + (set (match_operand:SF 0 "register_operand") + (vec_select:SF (match_dup 5) (parallel [(const_int 0)])))] + "TARGET_VXE" +{ + operands[2] = gen_reg_rtx (V4SFmode); + operands[3] = gen_reg_rtx (V4SFmode); + operands[4] = gen_reg_rtx (V4SFmode); + operands[5] = gen_reg_rtx (V4SFmode); +}) + +(define_expand "reduc_<reduc_minmax_name>_scal_v2df" + [(set (match_dup 2) + (unspec:V2DF [(match_operand:V2DF 1 "register_operand") + (match_dup 1) + (const_int 8)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 3) + (REDUC_MINMAX:V2DF (match_dup 1) (match_dup 2))) + (set (match_operand:DF 0 "register_operand" "") + (vec_select:DF (match_dup 3) (parallel [(const_int 0)])))] + "TARGET_VX" +{ + operands[2] = gen_reg_rtx (V2DFmode); + operands[3] = gen_reg_rtx (V2DFmode); +}) + +(define_expand "reduc_<reduc_minmax_name>_scal_v4sf" + [(set (match_dup 2) + (unspec:V4SF [(match_operand:V4SF 1 "register_operand") + (match_dup 1) + (const_int 4)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 3) + (REDUC_MINMAX:V4SF (match_dup 1) (match_dup 2))) + (set (match_dup 4) + (unspec:V4SF [(match_dup 3) + (match_dup 3) + (const_int 8)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 5) + (REDUC_MINMAX:V4SF (match_dup 3) (match_dup 4))) + (set (match_operand:SF 0 "register_operand" "") + (vec_select:SF (match_dup 5) (parallel [(const_int 0)])))] + "TARGET_VXE" +{ + operands[2] = gen_reg_rtx (V4SFmode); + operands[3] = gen_reg_rtx (V4SFmode); + operands[4] = gen_reg_rtx (V4SFmode); + operands[5] = gen_reg_rtx (V4SFmode); +}) + +; reduce_and, reduc_ior, reduc_xor +; reduc_smin, reduc_smax, reduc_umin, reduc_umax + +(define_code_iterator REDUCBIN [and xor ior smin smax umin umax]) +(define_code_attr reduc_bin_insn [(and "and") (xor "xor") (ior "ior") + (smin "smin") (smax "smax") + (umin "umin") (umax "umax")]) + +(define_expand "reduc_<reduc_bin_insn>_scal_v2di" + [(set (match_dup 2) + (unspec:V2DI [(match_operand:V2DI 1 "register_operand") + (match_dup 1) + (const_int 8)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 3) + (REDUCBIN:V2DI (match_dup 1) (match_dup 2))) + (set (match_operand:DI 0 "register_operand" "") + (vec_select:DI (match_dup 3) (parallel [(const_int 0)])))] + "TARGET_VX" +{ + operands[2] = gen_reg_rtx (V2DImode); + operands[3] = gen_reg_rtx (V2DImode); +}) + +(define_expand "reduc_<reduc_bin_insn>_scal_v4si" + [(set (match_dup 2) + (unspec:V4SI [(match_operand:V4SI 1 "register_operand") + (match_dup 1) + (const_int 4)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 3) + (REDUCBIN:V4SI (match_dup 1) (match_dup 2))) + (set (match_dup 4) + (unspec:V4SI [(match_dup 3) + (match_dup 3) + (const_int 8)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 5) + (REDUCBIN:V4SI (match_dup 3) (match_dup 4))) + (set (match_operand:SI 0 "register_operand" "") + (vec_select:SI (match_dup 5) (parallel [(const_int 0)])))] + "TARGET_VX" +{ + operands[2] = gen_reg_rtx (V4SImode); + operands[3] = gen_reg_rtx (V4SImode); + operands[4] = gen_reg_rtx (V4SImode); + operands[5] = gen_reg_rtx (V4SImode); +}) + +(define_expand "reduc_<reduc_bin_insn>_scal_v8hi" + [(set (match_dup 2) + (unspec:V8HI [(match_operand:V8HI 1 "register_operand") + (match_dup 1) + (const_int 2)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 3) + (REDUCBIN:V8HI (match_dup 1) (match_dup 2))) + (set (match_dup 4) + (unspec:V8HI [(match_dup 3) + (match_dup 3) + (const_int 4)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 5) + (REDUCBIN:V8HI (match_dup 3) (match_dup 4))) + (set (match_dup 6) + (unspec:V8HI [(match_dup 5) + (match_dup 5) + (const_int 8)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 7) + (REDUCBIN:V8HI (match_dup 5) (match_dup 6))) + (set (match_operand:HI 0 "register_operand" "") + (vec_select:HI (match_dup 7) (parallel [(const_int 0)])))] + "TARGET_VX" +{ + operands[2] = gen_reg_rtx (V8HImode); + operands[3] = gen_reg_rtx (V8HImode); + operands[4] = gen_reg_rtx (V8HImode); + operands[5] = gen_reg_rtx (V8HImode); + operands[6] = gen_reg_rtx (V8HImode); + operands[7] = gen_reg_rtx (V8HImode); +}) + +(define_expand "reduc_<reduc_bin_insn>_scal_v16qi" + [(set (match_dup 2) + (unspec:V16QI [(match_operand:V16QI 1 "register_operand") + (match_dup 1) + (const_int 1)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 3) + (REDUCBIN:V16QI (match_dup 1) (match_dup 2))) + (set (match_dup 4) + (unspec:V16QI [(match_dup 3) + (match_dup 3) + (const_int 2)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 5) + (REDUCBIN:V16QI (match_dup 3) (match_dup 4))) + (set (match_dup 6) + (unspec:V16QI [(match_dup 5) + (match_dup 5) + (const_int 4)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 7) + (REDUCBIN:V16QI (match_dup 5) (match_dup 6))) + (set (match_dup 8) + (unspec:V16QI [(match_dup 7) + (match_dup 7) + (const_int 8)] + UNSPEC_VEC_SLDBYTE)) + (set (match_dup 9) + (REDUCBIN:V16QI (match_dup 7) (match_dup 8))) + (set (match_operand:QI 0 "register_operand" "") + (vec_select:QI (match_dup 9) (parallel [(const_int 0)])))] + "TARGET_VX" +{ + operands[2] = gen_reg_rtx (V16QImode); + operands[3] = gen_reg_rtx (V16QImode); + operands[4] = gen_reg_rtx (V16QImode); + operands[5] = gen_reg_rtx (V16QImode); + operands[6] = gen_reg_rtx (V16QImode); + operands[7] = gen_reg_rtx (V16QImode); + operands[8] = gen_reg_rtx (V16QImode); + operands[9] = gen_reg_rtx (V16QImode); +}) diff --git a/gcc/configure b/gcc/configure index f056cfe..7537da2 100755 --- a/gcc/configure +++ b/gcc/configure @@ -1064,6 +1064,7 @@ enable_versioned_jit enable_default_pie enable_cet enable_s390_excess_float_precision +enable_x86_64_mfentry ' ac_precious_vars='build_alias host_alias @@ -1842,6 +1843,7 @@ Optional Features: --enable-s390-excess-float-precision on s390 targets, evaluate float with double precision when in standards-conforming mode + --enable-x86-64-mfentry enable -mfentry by default on x86-64 targets Optional Packages: --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] @@ -21520,7 +21522,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 21523 "configure" +#line 21525 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -21626,7 +21628,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 21629 "configure" +#line 21631 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -35022,6 +35024,46 @@ $as_echo "#define ENABLE_S390_EXCESS_FLOAT_PRECISION 1" >>confdefs.h ;; esac +# On x86-64, when profiling is enabled with shrink wrapping, the mcount +# call may not be placed at the function entry after +# pushq %rbp +# movq %rsp,%rbp +# As the result, the profile data may be skewed which makes PGO less +# effective: +# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120881 +# Enable -mfentry by default on x86-64 to put the profiling counter call +# before the prologue. +# Check whether --enable-x86-64-mfentry was given. +if test "${enable_x86_64_mfentry+set}" = set; then : + enableval=$enable_x86_64_mfentry; case "${enableval}" in + yes | no | auto) + enable_x86_64_mfentry=$enableval + ;; + *) + as_fn_error $? "'$enable_x86_64_mfentry' is an invalid value for --enable-x86-64-mfentry. Valid choices are 'yes', 'no' and 'auto'." "$LINENO" 5 + ;; + esac +else + enable_x86_64_mfentry=auto +fi + + +if test x"$enable_x86_64_mfentry" = xauto; then + case "${target}" in + i?86-*-*gnu* | x86_64-*-*gnu*) + # Enable -mfentry by default with glibc on x86. + enable_x86_64_mfentry=yes + ;; + esac +fi + +gif=`if test x$enable_x86_64_mfentry = xyes; then echo 1; else echo 0; fi` + +cat >>confdefs.h <<_ACEOF +#define ENABLE_X86_64_MFENTRY $gif +_ACEOF + + # Check if the linker supports '-z now' ld_now_support=no { $as_echo "$as_me:${as_lineno-$LINENO}: checking linker -z now option" >&5 diff --git a/gcc/configure.ac b/gcc/configure.ac index 58bf63f..24e0aa6 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -7972,6 +7972,41 @@ standards-compatible mode on s390 targets.]) ;; esac +# On x86-64, when profiling is enabled with shrink wrapping, the mcount +# call may not be placed at the function entry after +# pushq %rbp +# movq %rsp,%rbp +# As the result, the profile data may be skewed which makes PGO less +# effective: +# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120881 +# Enable -mfentry by default on x86-64 to put the profiling counter call +# before the prologue. +AC_ARG_ENABLE(x86-64-mfentry, + [AS_HELP_STRING([--enable-x86-64-mfentry], + [enable -mfentry by default on x86-64 targets])], + [case "${enableval}" in + yes | no | auto) + enable_x86_64_mfentry=$enableval + ;; + *) + AC_MSG_ERROR(['$enable_x86_64_mfentry' is an invalid value for --enable-x86-64-mfentry. Valid choices are 'yes', 'no' and 'auto'.]) + ;; + esac], + [enable_x86_64_mfentry=auto]) + +if test x"$enable_x86_64_mfentry" = xauto; then + case "${target}" in + i?86-*-*gnu* | x86_64-*-*gnu*) + # Enable -mfentry by default with glibc on x86. + enable_x86_64_mfentry=yes + ;; + esac +fi + +gif=`if test x$enable_x86_64_mfentry = xyes; then echo 1; else echo 0; fi` +AC_DEFINE_UNQUOTED(ENABLE_X86_64_MFENTRY, $gif, +[Define to enable -mfentry by default on x86-64.]) + # Check if the linker supports '-z now' ld_now_support=no AC_MSG_CHECKING(linker -z now option) diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 80ee2cd..09ea87a 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -2667,6 +2667,17 @@ target binutils supports @code{Intel CET} instructions and disabled otherwise. In this case, the target libraries are configured to get additional @option{-fcf-protection} option. +@item --enable-x86-64-mfentry +@itemx --disable-x86-64-mfentry +Enable @option {-mfentry} by default on x86-64 to put the profiling +counter call, @code{__fentry__}, before the prologue so that @option{-pg} +can be used with @option{-fshrink-wrap} which is enabled at @option{-O1}. +This configure option is 64-bit only because @code{__fentry__} doesn't +support PIC in 32-bit mode. + +@option{--enable-x86-64-mfentry=auto} is default. @option{-mfentry} is +enabled on Linux/x86-64 by default. + @item --with-riscv-attribute=@samp{yes}, @samp{no} or @samp{default} Generate RISC-V attribute by default, in order to record extra build information in object. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9a1aa37..f60865b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -34892,9 +34892,9 @@ Intel Panther Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, -VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR, AVXIFMA, -AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and -PREFETCHI instruction set support. +VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, UINTR, AVXIFMA, AVXVNNIINT8, +AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and PREFETCHI +instruction set support. @item sapphirerapids @itemx emeraldrapids @@ -34997,9 +34997,9 @@ Intel Clearwater Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, -LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -ENQCMD, UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, -SHA512, SM3, SM4, USER_MSR and PREFETCHI instruction set support. +LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, ENQCMD, +UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, +SM3, SM4, USER_MSR and PREFETCHI instruction set support. @item k6 AMD K6 CPU with MMX instruction set support. diff --git a/gcc/match.pd b/gcc/match.pd index 67b33ee..7f84d51 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -3605,11 +3605,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) unsigned widen_prec = TYPE_PRECISION (TREE_TYPE (@3)); unsigned cvt5_prec = TYPE_PRECISION (TREE_TYPE (@5)); unsigned cvt6_prec = TYPE_PRECISION (TREE_TYPE (@6)); - unsigned hw_int_prec = sizeof (HOST_WIDE_INT) * 8; wide_int c2 = wi::to_wide (@2); wide_int max = wi::mask (prec, false, widen_prec); bool c2_is_max_p = wi::eq_p (c2, max); - bool widen_mult_p = cvt5_prec == cvt6_prec && hw_int_prec == cvt5_prec; + bool widen_mult_p = cvt5_prec == cvt6_prec && widen_prec == cvt6_prec * 2; } (if (widen_prec > prec && c2_is_max_p && widen_mult_p))))) ) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 49f7f91..f132b84 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,169 @@ +2025-07-14 Richard Biener <rguenther@suse.de> + + Revert: + 2025-07-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121059 + * gcc.dg/vect/pr121059.c: New testcase. + +2025-07-14 Juergen Christ <jchrist@linux.ibm.com> + + * lib/target-supports.exp: Add s390 to vect_logical_reduc targets. + * gcc.target/s390/vector/reduc-binops-1.c: New test. + * gcc.target/s390/vector/reduc-minmax-1.c: New test. + * gcc.target/s390/vector/reduc-plus-1.c: New test. + +2025-07-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121059 + * gcc.dg/vect/pr121059.c: New testcase. + +2025-07-14 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c: New test. + +2025-07-14 Uros Bizjak <ubizjak@gmail.com> + + PR target/121015 + * gcc.target/i386/pr121015.c: New test. + +2025-07-14 H.J. Lu <hjl.tools@gmail.com> + + PR target/120881 + * gcc.dg/20021014-1.c: Add additional -mfentry -fno-pic options + for x86. + * gcc.dg/aru-2.c: Likewise. + * gcc.dg/nest.c: Likewise. + * gcc.dg/pr32450.c: Likewise. + * gcc.dg/pr43643.c: Likewise. + * gcc.target/i386/pr104447.c: Likewise. + * gcc.target/i386/pr113122-3.c: Likewise. + * gcc.target/i386/pr119386-1.c: Add additional -mfentry if not + ia32. + * gcc.target/i386/pr119386-2.c: Likewise. + * gcc.target/i386/pr120881-1a.c: New test. + * gcc.target/i386/pr120881-1b.c: Likewise. + * gcc.target/i386/pr120881-1c.c: Likewise. + * gcc.target/i386/pr120881-1d.c: Likewise. + * gcc.target/i386/pr120881-2a.c: Likewise. + * gcc.target/i386/pr120881-2b.c: Likewise. + * gcc.target/i386/pr82699-1.c: Add additional -mfentry. + * lib/target-supports.exp (check_effective_target_fentry): New. + +2025-07-14 François-Xavier Coudert <fxcoudert@gcc.gnu.org> + + * gcc.dg/darwin-minversion-link.c: Account for macOS 26. + +2025-07-14 Paul-Antoine Arras <parras@baylibre.com> + + PR target/119100 + * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfwmacc and + vfwmsac. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. Also check + for fcvt and vfmv. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Add vfwmacc and + vfwmsac. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. Also check + for fcvt and vfmv. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h: Add support for + widening variants. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h: New test + helper. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c: New test. + +2025-07-14 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/deref4.adb: New test. + * gnat.dg/deref4_pkg.ads: New helper. + +2025-07-14 Alfie Richards <alfie.richards@arm.com> + + * gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c: New test. + * gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c: New test. + +2025-07-14 panciyan <panciyan@eswincomputing.com> + + * gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Unsigned vector SAT_SUB form11 form12. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c: Use ussub instead of usub. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c: New test. + 2025-07-12 Xi Ruoyao <xry111@xry111.site> PR rtl-optimization/87600 diff --git a/gcc/testsuite/gcc.dg/20021014-1.c b/gcc/testsuite/gcc.dg/20021014-1.c index e43f7b2..f5f6fcf 100644 --- a/gcc/testsuite/gcc.dg/20021014-1.c +++ b/gcc/testsuite/gcc.dg/20021014-1.c @@ -2,6 +2,7 @@ /* { dg-require-profiling "-p" } */ /* { dg-options "-O2 -p" } */ /* { dg-options "-O2 -p -static" { target hppa*-*-hpux* } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ /* { dg-error "profiler" "No profiler support" { target xstormy16-*-* } 0 } */ /* { dg-message "" "consider using `-pg' instead of `-p' with gprof(1)" { target *-*-freebsd* } 0 } */ diff --git a/gcc/testsuite/gcc.dg/aru-2.c b/gcc/testsuite/gcc.dg/aru-2.c index 054223c..102ece1 100644 --- a/gcc/testsuite/gcc.dg/aru-2.c +++ b/gcc/testsuite/gcc.dg/aru-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ static int __attribute__((noinline)) bar (int x) diff --git a/gcc/testsuite/gcc.dg/darwin-minversion-link.c b/gcc/testsuite/gcc.dg/darwin-minversion-link.c index af712a1b..55f7c7e 100644 --- a/gcc/testsuite/gcc.dg/darwin-minversion-link.c +++ b/gcc/testsuite/gcc.dg/darwin-minversion-link.c @@ -20,6 +20,7 @@ /* { dg-additional-options "-mmacosx-version-min=013.000.00 -DCHECK=130000" { target *-*-darwin22* } } */ /* { dg-additional-options "-mmacosx-version-min=014.000.00 -DCHECK=140000" { target *-*-darwin23* } } */ /* { dg-additional-options "-mmacosx-version-min=015.000.00 -DCHECK=150000" { target *-*-darwin24* } } */ +/* { dg-additional-options "-mmacosx-version-min=026.000.00 -DCHECK=260000" { target *-*-darwin25* } } */ int main () diff --git a/gcc/testsuite/gcc.dg/nest.c b/gcc/testsuite/gcc.dg/nest.c index 5734c11..9221ed1 100644 --- a/gcc/testsuite/gcc.dg/nest.c +++ b/gcc/testsuite/gcc.dg/nest.c @@ -3,6 +3,7 @@ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ /* { dg-options "-O2 -pg -static" { target hppa*-*-hpux* } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ /* { dg-error "profiler" "No profiler support" { target xstormy16-*-* } 0 } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/pr32450.c b/gcc/testsuite/gcc.dg/pr32450.c index 9606e30..4aaeb7d 100644 --- a/gcc/testsuite/gcc.dg/pr32450.c +++ b/gcc/testsuite/gcc.dg/pr32450.c @@ -3,7 +3,7 @@ /* { dg-do run } */ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ -/* { dg-options "-O2 -pg -mtune=core2" { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-O2 -pg -mtune=core2 -mfentry -fno-pic" { target { i?86-*-* x86_64-*-* } } } */ /* { dg-options "-O2 -pg -static" { target hppa*-*-hpux* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/pr43643.c b/gcc/testsuite/gcc.dg/pr43643.c index 43896ab..a62586d 100644 --- a/gcc/testsuite/gcc.dg/pr43643.c +++ b/gcc/testsuite/gcc.dg/pr43643.c @@ -4,6 +4,7 @@ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ /* { dg-options "-O2 -pg -static" { target hppa*-*-hpux* } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ extern char *strdup (const char *); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c new file mode 100644 index 0000000..90b5438 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c @@ -0,0 +1,97 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat16x2_t, z0, + svamax_f16_x2 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat16x2_t, z0, + svamax_f16_x2 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.h - z29\.h} +** | +** famax [^\n]+, {z28\.h - z29\.h} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat16x2_t, z0, + svamax_f16_x2 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** famax {z18\.h - z19\.h}, {z18\.h - z19\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat16x2_t, z18, + svamax_f16_x2 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z18\.h - z19\.h} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z18, svfloat16x2_t, z23, + svamax_f16_x2 (z23, z18), + svamax (z23, z18)) + +/* +** amax_z28_z28_z0: +** famax {z28\.h - z29\.h}, {z28\.h - z29\.h}, {z0\.h - z1\.h} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat16x2_t, z28, + svamax_f16_x2 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** famax {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z18\.h - z19\.h} +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat16x2_t, z0, + svamax_f16_x2 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** | +** famax {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat16x2_t, z4, + svamax_f16_x2 (z4, z23), + svamax (z4, z23)) + diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c new file mode 100644 index 0000000..d168ad7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat16x4_t, z0, + svamax_f16_x4 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat16x4_t, z0, + svamax_f16_x4 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.h - z31\.h} +** | +** famax [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat16x4_t, z0, + svamax_f16_x4 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z4\.h - z7\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat16x4_t, z18, + svamax_f16_x4 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z28, svfloat16x4_t, z23, + svamax_f16_x4 (z23, z28), + svamax (z23, z28)) + +/* +** amax_z28_z28_z0: +** famax {z28\.h - z31\.h}, {z28\.h - z31\.h}, {z0\.h - z3\.h} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat16x4_t, z28, + svamax_f16_x4 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** | +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat16x4_t, z0, + svamax_f16_x4 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** | +** famax {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat16x4_t, z4, + svamax_f16_x4 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c new file mode 100644 index 0000000..618d50b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat32x2_t, z0, + svamax_f32_x2 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat32x2_t, z0, + svamax_f32_x2 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.s - z29\.s} +** | +** famax [^\n]+, {z28\.s - z29\.s} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat32x2_t, z0, + svamax_f32_x2 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** famax {z18\.s - z19\.s}, {z18\.s - z19\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat32x2_t, z18, + svamax_f32_x2 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z18\.s - z19\.s} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z18, svfloat32x2_t, z23, + svamax_f32_x2 (z23, z18), + svamax (z23, z18)) + +/* +** amax_z28_z28_z0: +** famax {z28\.s - z29\.s}, {z28\.s - z29\.s}, {z0\.s - z1\.s} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat32x2_t, z28, + svamax_f32_x2 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** famax {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z18\.s - z19\.s} +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat32x2_t, z0, + svamax_f32_x2 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** | +** famax {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat32x2_t, z4, + svamax_f32_x2 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c new file mode 100644 index 0000000..981e78c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c @@ -0,0 +1,129 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat32x4_t, z0, + svamax_f32_x4 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat32x4_t, z0, + svamax_f32_x4 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.s - z31\.s} +** | +** famax [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat32x4_t, z0, + svamax_f32_x4 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z4\.s - z7\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat32x4_t, z18, + svamax_f32_x4 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z28, svfloat32x4_t, z23, + svamax_f32_x4 (z23, z28), + svamax (z23, z28)) + +/* +** amax_z28_z28_z0: +** famax {z28\.s - z31\.s}, {z28\.s - z31\.s}, {z0\.s - z3\.s} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat32x4_t, z28, + svamax_f32_x4 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** | +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat32x4_t, z0, + svamax_f32_x4 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** | +** famax {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat32x4_t, z4, + svamax_f32_x4 (z4, z23), + svamax (z4, z23)) + diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c new file mode 100644 index 0000000..e93a409 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat64x2_t, z0, + svamax_f64_x2 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat64x2_t, z0, + svamax_f64_x2 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.d - z29\.d} +** | +** famax [^\n]+, {z28\.d - z29\.d} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat64x2_t, z0, + svamax_f64_x2 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** famax {z18\.d - z19\.d}, {z18\.d - z19\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat64x2_t, z18, + svamax_f64_x2 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z18\.d - z19\.d} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z18, svfloat64x2_t, z23, + svamax_f64_x2 (z23, z18), + svamax (z23, z18)) + +/* +** amax_z28_z28_z0: +** famax {z28\.d - z29\.d}, {z28\.d - z29\.d}, {z0\.d - z1\.d} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat64x2_t, z28, + svamax_f64_x2 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** famax {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z18\.d - z19\.d} +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat64x2_t, z0, + svamax_f64_x2 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** | +** famax {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat64x2_t, z4, + svamax_f64_x2 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c new file mode 100644 index 0000000..2db629e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat64x4_t, z0, + svamax_f64_x4 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat64x4_t, z0, + svamax_f64_x4 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.d - z31\.d} +** | +** famax [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat64x4_t, z0, + svamax_f64_x4 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z4\.d - z7\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat64x4_t, z18, + svamax_f64_x4 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z28, svfloat64x4_t, z23, + svamax_f64_x4 (z23, z28), + svamax (z23, z28)) + +/* +** amax_z28_z28_z0: +** famax {z28\.d - z31\.d}, {z28\.d - z31\.d}, {z0\.d - z3\.d} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat64x4_t, z28, + svamax_f64_x4 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** | +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat64x4_t, z0, + svamax_f64_x4 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** | +** famax {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat64x4_t, z4, + svamax_f64_x4 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c new file mode 100644 index 0000000..74604e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat16x2_t, z0, + svamin_f16_x2 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat16x2_t, z0, + svamin_f16_x2 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.h - z29\.h} +** | +** famin [^\n]+, {z28\.h - z29\.h} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat16x2_t, z0, + svamin_f16_x2 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** famin {z18\.h - z19\.h}, {z18\.h - z19\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat16x2_t, z18, + svamin_f16_x2 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z18\.h - z19\.h} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z18, svfloat16x2_t, z23, + svamin_f16_x2 (z23, z18), + svamin (z23, z18)) + +/* +** amin_z28_z28_z0: +** famin {z28\.h - z29\.h}, {z28\.h - z29\.h}, {z0\.h - z1\.h} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat16x2_t, z28, + svamin_f16_x2 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** famin {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z18\.h - z19\.h} +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat16x2_t, z0, + svamin_f16_x2 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** | +** famin {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat16x2_t, z4, + svamin_f16_x2 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c new file mode 100644 index 0000000..bc3779b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat16x4_t, z0, + svamin_f16_x4 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat16x4_t, z0, + svamin_f16_x4 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.h - z31\.h} +** | +** famin [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat16x4_t, z0, + svamin_f16_x4 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z4\.h - z7\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat16x4_t, z18, + svamin_f16_x4 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z28, svfloat16x4_t, z23, + svamin_f16_x4 (z23, z28), + svamin (z23, z28)) + +/* +** amin_z28_z28_z0: +** famin {z28\.h - z31\.h}, {z28\.h - z31\.h}, {z0\.h - z3\.h} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat16x4_t, z28, + svamin_f16_x4 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** | +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat16x4_t, z0, + svamin_f16_x4 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** | +** famin {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat16x4_t, z4, + svamin_f16_x4 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c new file mode 100644 index 0000000..43e3075 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat32x2_t, z0, + svamin_f32_x2 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat32x2_t, z0, + svamin_f32_x2 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.s - z29\.s} +** | +** famin [^\n]+, {z28\.s - z29\.s} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat32x2_t, z0, + svamin_f32_x2 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** famin {z18\.s - z19\.s}, {z18\.s - z19\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat32x2_t, z18, + svamin_f32_x2 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z18\.s - z19\.s} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z18, svfloat32x2_t, z23, + svamin_f32_x2 (z23, z18), + svamin (z23, z18)) + +/* +** amin_z28_z28_z0: +** famin {z28\.s - z29\.s}, {z28\.s - z29\.s}, {z0\.s - z1\.s} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat32x2_t, z28, + svamin_f32_x2 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** famin {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z18\.s - z19\.s} +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat32x2_t, z0, + svamin_f32_x2 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** | +** famin {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat32x2_t, z4, + svamin_f32_x2 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c new file mode 100644 index 0000000..6bd20f8f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat32x4_t, z0, + svamin_f32_x4 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat32x4_t, z0, + svamin_f32_x4 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.s - z31\.s} +** | +** famin [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat32x4_t, z0, + svamin_f32_x4 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z4\.s - z7\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat32x4_t, z18, + svamin_f32_x4 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z28, svfloat32x4_t, z23, + svamin_f32_x4 (z23, z28), + svamin (z23, z28)) + +/* +** amin_z28_z28_z0: +** famin {z28\.s - z31\.s}, {z28\.s - z31\.s}, {z0\.s - z3\.s} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat32x4_t, z28, + svamin_f32_x4 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** | +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat32x4_t, z0, + svamin_f32_x4 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** | +** famin {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat32x4_t, z4, + svamin_f32_x4 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c new file mode 100644 index 0000000..3bbef3f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat64x2_t, z0, + svamin_f64_x2 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat64x2_t, z0, + svamin_f64_x2 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.d - z29\.d} +** | +** famin [^\n]+, {z28\.d - z29\.d} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat64x2_t, z0, + svamin_f64_x2 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** famin {z18\.d - z19\.d}, {z18\.d - z19\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat64x2_t, z18, + svamin_f64_x2 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z18\.d - z19\.d} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z18, svfloat64x2_t, z23, + svamin_f64_x2 (z23, z18), + svamin (z23, z18)) + +/* +** amin_z28_z28_z0: +** famin {z28\.d - z29\.d}, {z28\.d - z29\.d}, {z0\.d - z1\.d} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat64x2_t, z28, + svamin_f64_x2 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** famin {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z18\.d - z19\.d} +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat64x2_t, z0, + svamin_f64_x2 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** | +** famin {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat64x2_t, z4, + svamin_f64_x2 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c new file mode 100644 index 0000000..6f4c9b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat64x4_t, z0, + svamin_f64_x4 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat64x4_t, z0, + svamin_f64_x4 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.d - z31\.d} +** | +** famin [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat64x4_t, z0, + svamin_f64_x4 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z4\.d - z7\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat64x4_t, z18, + svamin_f64_x4 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z28, svfloat64x4_t, z23, + svamin_f64_x4 (z23, z28), + svamin (z23, z28)) + +/* +** amin_z28_z28_z0: +** famin {z28\.d - z31\.d}, {z28\.d - z31\.d}, {z0\.d - z3\.d} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat64x4_t, z28, + svamin_f64_x4 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** | +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat64x4_t, z0, + svamin_f64_x4 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** | +** famin {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat64x4_t, z4, + svamin_f64_x4 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/i386/pr104447.c b/gcc/testsuite/gcc.target/i386/pr104447.c index cb618c7..f58170d 100644 --- a/gcc/testsuite/gcc.target/i386/pr104447.c +++ b/gcc/testsuite/gcc.target/i386/pr104447.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-profiling "-pg" } */ -/* { dg-options "-O2 -pg" } */ +/* { dg-options "-O2 -pg -mfentry -fno-pic" } */ int bar (int x) diff --git a/gcc/testsuite/gcc.target/i386/pr113122-3.c b/gcc/testsuite/gcc.target/i386/pr113122-3.c index 71aa240..c46805d 100644 --- a/gcc/testsuite/gcc.target/i386/pr113122-3.c +++ b/gcc/testsuite/gcc.target/i386/pr113122-3.c @@ -1,7 +1,7 @@ /* PR target/113122 */ /* { dg-do assemble { target *-*-linux* } } */ /* { dg-require-effective-target masm_intel } */ -/* { dg-options "-fprofile -O2 -masm=intel" } */ +/* { dg-options "-fprofile -mfentry -fno-pic -O2 -masm=intel" } */ void func (void) diff --git a/gcc/testsuite/gcc.target/i386/pr119386-1.c b/gcc/testsuite/gcc.target/i386/pr119386-1.c index 9a0dc64..39a3e1d 100644 --- a/gcc/testsuite/gcc.target/i386/pr119386-1.c +++ b/gcc/testsuite/gcc.target/i386/pr119386-1.c @@ -1,7 +1,9 @@ /* PR target/119386 */ /* { dg-do compile { target *-*-linux* } } */ /* { dg-options "-O2 -fpic -pg" } */ -/* { dg-final { scan-assembler "call\[ \t\]+mcount@PLT" } } */ +/* { dg-additional-options "-mfentry" { target { ! ia32 } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+mcount@PLT" { target ia32 } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+__fentry__@PLT" { target { ! ia32 } } } } */ int main () diff --git a/gcc/testsuite/gcc.target/i386/pr119386-2.c b/gcc/testsuite/gcc.target/i386/pr119386-2.c index 3ea978e..d516aa9 100644 --- a/gcc/testsuite/gcc.target/i386/pr119386-2.c +++ b/gcc/testsuite/gcc.target/i386/pr119386-2.c @@ -1,7 +1,8 @@ /* PR target/119386 */ /* { dg-do compile { target *-*-linux* } } */ /* { dg-options "-O2 -fpic -fno-plt -pg" } */ -/* { dg-final { scan-assembler "call\[ \t\]+\\*mcount@GOTPCREL\\(" { target { ! ia32 } } } } */ +/* { dg-additional-options "-mfentry" { target { ! ia32 } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*__fentry__@GOTPCREL" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "call\[ \t\]+\\*mcount@GOT\\(" { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1a.c b/gcc/testsuite/gcc.target/i386/pr120881-1a.c new file mode 100644 index 0000000..3d9ac0e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1a.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fno-pic" } */ +/* { dg-message "'-pg' without '-mfentry' may be unreliable with shrink wrapping" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1b.c b/gcc/testsuite/gcc.target/i386/pr120881-1b.c new file mode 100644 index 0000000..0826407 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1b.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target { fpic && { ! ia32 } } } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fpic" } */ +/* { dg-message "'-pg' without '-mfentry' may be unreliable with shrink wrapping" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1c.c b/gcc/testsuite/gcc.target/i386/pr120881-1c.c new file mode 100644 index 0000000..c21979f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1c.c @@ -0,0 +1,3 @@ +/* { dg-do compile { target { fpic && ia32 } } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fpic" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1d.c b/gcc/testsuite/gcc.target/i386/pr120881-1d.c new file mode 100644 index 0000000..f74af23 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1d.c @@ -0,0 +1,3 @@ +/* { dg-do compile { target { fpic && ia32 } } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fno-shrink-wrap -fno-pic" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-2a.c b/gcc/testsuite/gcc.target/i386/pr120881-2a.c new file mode 100644 index 0000000..52e3e52 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-2a.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target fentry } } */ +/* { dg-options "-O2 -pg" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**f2: +**.LFB[0-9]+: +** .cfi_startproc +** call __fentry__ +**... +*/ + +extern void f1 (void); + +void +f2 (int count) +{ + for (int i = 0; i < count; ++i) + f1 (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr120881-2b.c b/gcc/testsuite/gcc.target/i386/pr120881-2b.c new file mode 100644 index 0000000..43a12f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-2b.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue -march=x86-64" } */ +/* { dg-final { scan-rtl-dump "Now spread 1 times" "pro_and_epilogue" } } */ + +#include "pr120881-2a.c" + diff --git a/gcc/testsuite/gcc.target/i386/pr121015.c b/gcc/testsuite/gcc.target/i386/pr121015.c new file mode 100644 index 0000000..57c8bff --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121015.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3" } */ + +extern union { + int i; + float f; +} int_as_float_u; + +extern int render_result_from_bake_w; +extern int render_result_from_bake_h_seed_pass; +extern float *render_result_from_bake_h_primitive; +extern float *render_result_from_bake_h_seed; + +float +int_as_float(int i) +{ + int_as_float_u.i = i; + return int_as_float_u.f; +} + +void +render_result_from_bake_h(int tx) +{ + while (render_result_from_bake_w) { + for (; tx < render_result_from_bake_w; tx++) + render_result_from_bake_h_primitive[1] = + render_result_from_bake_h_primitive[2] = int_as_float(-1); + if (render_result_from_bake_h_seed_pass) { + *render_result_from_bake_h_seed = 0; + } + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr82699-1.c b/gcc/testsuite/gcc.target/i386/pr82699-1.c index 272d079..96e3ccb 100644 --- a/gcc/testsuite/gcc.target/i386/pr82699-1.c +++ b/gcc/testsuite/gcc.target/i386/pr82699-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fno-pic -fcf-protection -pg -fasynchronous-unwind-tables" } */ +/* { dg-options "-O2 -mfentry -fno-pic -fcf-protection -pg -fasynchronous-unwind-tables" } */ /* { dg-final { scan-assembler-times {\t\.cfi_startproc\n\tendbr} 1 } } */ extern int bar (int); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h index 9e4b4f4..93c29f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h @@ -531,6 +531,40 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ #define DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) \ DEF_VEC_SAT_U_SUB_FMT_10(T) +#define DEF_VEC_SAT_U_SUB_FMT_11(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_11 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = overflow ? 0 : ret; \ + } \ +} +#define DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_11(T) + +#define DEF_VEC_SAT_U_SUB_FMT_12(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_12 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = !overflow ? ret : 0; \ + } \ +} +#define DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_12(T) + #define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \ @@ -737,6 +771,16 @@ vec_sat_s_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_11(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_11(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_SUB_FMT_12(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_12(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12(T, out, op_1, op_2, N) + #define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N) #define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h index 4469f0e..7647439 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h @@ -744,7 +744,7 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] = }, }; -uint8_t TEST_UNARY_DATA(uint8_t, usub)[][3][N] = { +uint8_t TEST_UNARY_DATA(uint8_t, ussub)[][3][N] = { { { 0, 0, 0, 0, @@ -807,7 +807,7 @@ uint8_t TEST_UNARY_DATA(uint8_t, usub)[][3][N] = { }, }; -uint16_t TEST_UNARY_DATA(uint16_t, usub)[][3][N] = { +uint16_t TEST_UNARY_DATA(uint16_t, ussub)[][3][N] = { { { 0, 0, 0, 0, @@ -870,7 +870,7 @@ uint16_t TEST_UNARY_DATA(uint16_t, usub)[][3][N] = { }, }; -uint32_t TEST_UNARY_DATA(uint32_t, usub)[][3][N] = { +uint32_t TEST_UNARY_DATA(uint32_t, ussub)[][3][N] = { { { 0, 0, 4, 0, @@ -933,7 +933,7 @@ uint32_t TEST_UNARY_DATA(uint32_t, usub)[][3][N] = { }, }; -uint64_t TEST_UNARY_DATA(uint64_t, usub)[][3][N] = { +uint64_t TEST_UNARY_DATA(uint64_t, ussub)[][3][N] = { { { 0, 9, 0, 0, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c new file mode 100644 index 0000000..57da9e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c new file mode 100644 index 0000000..b5264a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c new file mode 100644 index 0000000..1a68b5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c new file mode 100644 index 0000000..a1c5c19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c new file mode 100644 index 0000000..fd987e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c new file mode 100644 index 0000000..bc380fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c new file mode 100644 index 0000000..c03163f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c new file mode 100644 index 0000000..91e1909 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c index 5fc747b..5878c5b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c index c9976d0..f74979f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c index 10a0b0c..1250e5b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c index 7b22863..a2a77dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c index a6b2dc4..19c8fa0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c index 91e749e..ada136f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c index b7a6314..488c158 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c index 1d55798..127c27a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c new file mode 100644 index 0000000..4b49467 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c new file mode 100644 index 0000000..80b55ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c new file mode 100644 index 0000000..6a89d0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c new file mode 100644 index 0000000..974493e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c new file mode 100644 index 0000000..28778b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c new file mode 100644 index 0000000..936a39a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c new file mode 100644 index 0000000..b8fa65b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c new file mode 100644 index 0000000..6bff1e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c index dcd6d17..45bef88 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c index 98a1fff..6d8a653 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c index 5445b01..0132d46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c index 3aaec4d..425f86f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c index 99e58cd..97a8e08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c index bd7bcd0..9124899 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c index 96ee0c8..1e54ede 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c index b9fa957..d8d53b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c index 6d4f377..b293823 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c index 1425017..f0f1c4f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c index 149d481..27c28e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c index 12195cd..7911825 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c index 9cd2577..6ae7b36 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c index 638e054..4e6b9e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c index db86baf..6b26913 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c index b277e1c..2bd28cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c index e79e2fc..69b0be9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c index cd9cbfc..2450586 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c index 7c0f753..0b97910 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c index d97a834..afb23f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c index 3b8c870..0466d4c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c index 065d898..14b8701 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c index f6783a8..7e0afd8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c index 6b9ae2d..40b1a6a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c index 27c4563..bd33048 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c index 2dba875..36f78f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c index 149a522..3bc5d5d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c index 739850e..3964d1b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c index 3eb91ef..4c0809a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c index 3e8d6fb..3e700bd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c index bb09035..81b8dc8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c index 1dc3191..8bc52ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c index 05cf57c..b17fd8e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c @@ -11,6 +11,8 @@ DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, +, acc) DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, +, sac) DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, -, nacc) DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, -, nsac) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -20,3 +22,5 @@ DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, -, nsac) /* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c index 873e315..efd887d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c @@ -11,6 +11,8 @@ DEF_VF_MULOP_ACC_CASE_0 (float, +, +, acc) DEF_VF_MULOP_ACC_CASE_0 (float, -, +, sac) DEF_VF_MULOP_ACC_CASE_0 (float, +, -, nacc) DEF_VF_MULOP_ACC_CASE_0 (float, -, -, nsac) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -20,3 +22,5 @@ DEF_VF_MULOP_ACC_CASE_0 (float, -, -, nsac) /* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c index 78127b6..84987a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c @@ -11,3 +11,7 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.s.h} 2 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c index 30d57e0..dbd3d02 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c @@ -11,3 +11,7 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.d.s} 2 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c index 8295ffb..5f0d758 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c @@ -11,6 +11,8 @@ DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, +, acc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, +, sac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, -, nacc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, -, nsac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -20,3 +22,5 @@ DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, -, nsac, VF_MULOP_ACC_BODY_X128) /* { dg-final { scan-assembler {vfmsac.vf} } } */ /* { dg-final { scan-assembler {vfnmacc.vf} } } */ /* { dg-final { scan-assembler {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c index f237f84..951b0ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c @@ -11,6 +11,8 @@ DEF_VF_MULOP_ACC_CASE_1 (float, +, +, acc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, -, +, sac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, +, -, nacc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, -, -, nsac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -20,3 +22,5 @@ DEF_VF_MULOP_ACC_CASE_1 (float, -, -, nsac, VF_MULOP_ACC_BODY_X128) /* { dg-final { scan-assembler {vfmsac.vf} } } */ /* { dg-final { scan-assembler {vfnmacc.vf} } } */ /* { dg-final { scan-assembler {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c index 7a50f67..a4edd92 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c @@ -11,3 +11,6 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {fcvt.s.h} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c index fb0493e..4eb28e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c @@ -11,3 +11,6 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {fcvt.d.s} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h index 1659f78..b1a324f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h @@ -34,6 +34,21 @@ #define RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, out, in, x, n) \ RUN_VF_MULOP_ACC_CASE_0 (T, NAME, out, in, x, n) +#define DEF_VF_MULOP_WIDEN_CASE_0(T1, T2, OP, NEG, NAME) \ + void test_vf_mulop_widen_##NAME##_##T1##_case_0 (T2 *restrict out, \ + T1 *restrict in, \ + T1 *restrict f, unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = NEG ((T2) * f * (T2) in[i] OP out[i]); \ + } +#define DEF_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, OP, NEG, NAME) \ + DEF_VF_MULOP_WIDEN_CASE_0 (T1, T2, OP, NEG, NAME) +#define RUN_VF_MULOP_WIDEN_CASE_0(T1, T2, NAME, out, in, x, n) \ + test_vf_mulop_widen_##NAME##_##T1##_case_0 (out, in, x, n) +#define RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, x, n) \ + RUN_VF_MULOP_WIDEN_CASE_0 (T1, T2, NAME, out, in, x, n) + #define VF_MULOP_BODY(op, neg) \ out[k + 0] = neg (tmp * out[k + 0] op in[k + 0]); \ out[k + 1] = neg (tmp * out[k + 1] op in[k + 1]); \ @@ -129,4 +144,19 @@ #define DEF_VF_MULOP_ACC_CASE_1_WRAP(T, OP, NEG, NAME, BODY) \ DEF_VF_MULOP_ACC_CASE_1 (T, OP, NEG, NAME, BODY) +#define DEF_VF_MULOP_WIDEN_CASE_1(TYPE1, TYPE2, OP, NEG, NAME) \ + void test_vf_mulop_widen_##NAME##_##TYPE1##_##TYPE2##_case_1 ( \ + TYPE2 *__restrict dst, TYPE2 *__restrict dst2, TYPE2 *__restrict dst3, \ + TYPE2 *__restrict dst4, TYPE1 *__restrict a, TYPE1 *__restrict b, \ + TYPE1 *__restrict a2, TYPE1 *__restrict b2, int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + dst[i] = NEG ((TYPE2) * a * (TYPE2) b[i] OP dst[i]); \ + dst2[i] = NEG ((TYPE2) * a2 * (TYPE2) b[i] OP dst2[i]); \ + dst3[i] = NEG ((TYPE2) * a2 * (TYPE2) a[i] OP dst3[i]); \ + dst4[i] = NEG ((TYPE2) * a * (TYPE2) b2[i] OP dst4[i]); \ + } \ + } + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h new file mode 100644 index 0000000..9f95fbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h @@ -0,0 +1,32 @@ +#ifndef HAVE_DEFINED_VF_MULOP_WIDEN_RUN_H +#define HAVE_DEFINED_VF_MULOP_WIDEN_RUN_H + +#include <assert.h> + +#define N 512 + +int main () +{ + T1 f[N]; + T1 in[N]; + T2 out[N]; + T2 out2[N]; + + for (int i = 0; i < N; i++) + { + f[i] = LIMIT + i % 8723; + in[i] = LIMIT + i & 1964; + out[i] = LIMIT + i & 628; + out2[i] = LIMIT + i & 628; + asm volatile ("" ::: "memory"); + } + + TEST_RUN (T1, T2, NAME, out, in, f, N); + + for (int i = 0; i < N; i++) + assert (out[i] == NEG(((T2) *f * (T2) in[i]) OP out2[i])); + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c new file mode 100644 index 0000000..d78cf73 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME acc +#define OP + +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c new file mode 100644 index 0000000..1af5240 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME acc +#define OP + +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c new file mode 100644 index 0000000..6422bba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME sac +#define OP - +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c new file mode 100644 index 0000000..13617a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME sac +#define OP - +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c new file mode 100644 index 0000000..43ab563 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c new file mode 100644 index 0000000..8d5449b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c new file mode 100644 index 0000000..ee41593 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c new file mode 100644 index 0000000..065afb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c new file mode 100644 index 0000000..062bbc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c new file mode 100644 index 0000000..e6f632b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/s390/vector/reduc-binops-1.c b/gcc/testsuite/gcc.target/s390/vector/reduc-binops-1.c new file mode 100644 index 0000000..efd3294 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/reduc-binops-1.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z13 -ftree-vectorize -fdump-tree-optimized" } */ + +#define T(X,N) \ + unsigned X \ + reduce_and_##X (unsigned X *in) \ + { \ + unsigned X acc = (unsigned X)-1; \ + for (int i = 0; i < N; i++) \ + acc &= in[i]; \ + return acc; \ + } \ + unsigned X \ + reduce_ior_##X (unsigned X *in) \ + { \ + unsigned X acc = 0; \ + for (int i = 0; i < N; i++) \ + acc |= in[i]; \ + return acc; \ + } \ + unsigned X \ + redue_xor_##X (unsigned X *in) \ + { \ + unsigned X acc = 0; \ + for (int i = 0; i < N; i++) \ + acc ^= in[i]; \ + return acc; \ + } + +T(char,16) + +T(short, 8) + +T(int,4) + +T(long,4) + +/* { dg-final { scan-tree-dump-times "\.REDUC_AND" 4 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_IOR" 4 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_XOR" 4 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/reduc-minmax-1.c b/gcc/testsuite/gcc.target/s390/vector/reduc-minmax-1.c new file mode 100644 index 0000000..5295250 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/reduc-minmax-1.c @@ -0,0 +1,234 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z14 -ftree-vectorize -fdump-tree-optimized" } */ + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + +/* unsigned integers */ + +unsigned char +reduce_umax_char (unsigned char *p) +{ + unsigned char res = p[0]; + for (int i = 0; i < 16; i++) + res = MAX (res, p[i]); + return res; +} + +unsigned char +reduce_umin_char (unsigned char *p) +{ + unsigned char res = p[0]; + for (int i = 0; i < 16; i++) + res = MIN (res, p[i]); + return res; +} + +unsigned short +reduce_umax_short (unsigned short *p) +{ + unsigned short res = p[0]; + for (int i = 0; i < 8; i++) + res = MAX (res, p[i]); + return res; +} + +unsigned short +reduce_umin_short (unsigned short *p) +{ + unsigned short res = p[0]; + for (int i = 0; i < 8; i++) + res = MIN (res, p[i]); + return res; +} + +unsigned int +reduce_umax_int (unsigned int* p) +{ + unsigned int res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +unsigned int +reduce_umin_int (unsigned int* p) +{ + unsigned int res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN(res, p[i]); + return res; +} + +unsigned long +reduce_umax_long (unsigned long* p) +{ + unsigned long res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +unsigned long +reduce_umin_long (unsigned long* p) +{ + unsigned long res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN(res, p[i]); + return res; +} + +/* signed integers */ + +signed char +reduce_smax_char (signed char *p) +{ + signed char res = p[0]; + for (int i = 0; i < 16; i++) + res = MAX (res, p[i]); + return res; +} + +signed char +reduce_smin_char (signed char *p) +{ + signed char res = p[0]; + for (int i = 0; i < 16; i++) + res = MIN (res, p[i]); + return res; +} + +signed short +reduce_smax_short (signed short *p) +{ + signed short res = p[0]; + for (int i = 0; i < 8; i++) + res = MAX (res, p[i]); + return res; +} + +signed short +reduce_smin_short (signed short *p) +{ + signed short res = p[0]; + for (int i = 0; i < 8; i++) + res = MIN (res, p[i]); + return res; +} + +signed int +reduce_smax_int (signed int* p) +{ + signed int res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +signed int +reduce_smin_int (signed int* p) +{ + signed int res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN(res, p[i]); + return res; +} + +signed long +reduce_smax_long (signed long* p) +{ + signed long res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +signed long +reduce_smin_long (signed long* p) +{ + signed long res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN(res, p[i]); + return res; +} + +float +__attribute__((optimize("Ofast"))) +reduce_smax_float (float* p) +{ + float res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +float +__attribute__((optimize("Ofast"))) +reduce_smin_float (float* p) +{ + float res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN (res, p[i]); + return res; +} + +double +__attribute__((optimize("Ofast"))) +reduce_smax_double (double* p) +{ + double res = p[0]; + for (int i = 0; i != 4; i++) + res = MAX (res, p[i]); + return res; +} + +double +__attribute__((optimize("Ofast"))) +reduce_smin_double (double* p) +{ + double res = p[0]; + for (int i = 0; i != 4; i++) + res = MIN (res, p[i]); + return res; +} + +float +reduce_fmax_float (float* p) +{ + float res = p[0]; + for (int i = 0; i != 4; i++) + res = __builtin_fmaxf (res, p[i]); + return res; +} + +float +reduce_fmin_float (float* p) +{ + float res = p[0]; + for (int i = 0; i != 4; i++) + res = __builtin_fminf (res, p[i]); + return res; +} + +double +reduce_fmax_double (double* p) +{ + double res = p[0]; + for (int i = 0; i != 4; i++) + res = __builtin_fmax (res, p[i]); + return res; +} + +double +reduce_fmin_double (double* p) +{ + double res = p[0]; + for (int i = 0; i != 4; i++) + res = __builtin_fmin (res, p[i]); + return res; +} + +/* { dg-final { scan-tree-dump-times "\.REDUC_MAX" 10 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_MIN" 10 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_FMAX" 2 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_FMIN" 2 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/reduc-plus-1.c b/gcc/testsuite/gcc.target/s390/vector/reduc-plus-1.c new file mode 100644 index 0000000..12cdd5f --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/reduc-plus-1.c @@ -0,0 +1,152 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=z14 -ftree-vectorize -fdump-tree-optimized" } */ +/* { dg-do run { target { s390_z14_hw } } } */ + +/* signed integers */ + +signed char +__attribute__((noipa, optimize("Ofast"))) +reduce_add_char (signed char* p) +{ + signed char sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +short +__attribute__((noipa, optimize("Ofast"))) +reduce_add_short (short* p) +{ + short sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +int +__attribute__((noipa, optimize("Ofast"))) +reduce_add_int (int* p) +{ + int sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +long +__attribute__((noipa, optimize("Ofast"))) +reduce_add_long (long* p) +{ + long sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +/* unsigned integers */ + +unsigned char +__attribute__((noipa, optimize("Ofast"))) +reduce_add_uchar (unsigned char* p) +{ + unsigned char sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +unsigned short +__attribute__((noipa, optimize("Ofast"))) +reduce_add_ushort (unsigned short* p) +{ + unsigned short sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +unsigned int +__attribute__((noipa, optimize("Ofast"))) +reduce_add_uint (unsigned int* p) +{ + unsigned int sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +unsigned long +__attribute__((noipa, optimize("Ofast"))) +reduce_add_ulong (unsigned long* p) +{ + unsigned long sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +/* floating point */ + +float +__attribute__((noipa, optimize("Ofast"))) +reduce_add_float (float* p) +{ + float sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +double +__attribute__((noipa, optimize("Ofast"))) +reduce_add_double (double* p) +{ + double sum = 0; + for (int i = 0; i != 16; i++) + sum += p[i]; + return sum; +} + +int +main() +{ + signed char chararr[] = {-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16}; + signed short shortarr[] = {-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16}; + signed int intarr[] = {-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16}; + signed long longarr[] = {-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16}; + + unsigned char uchararr[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + unsigned short ushortarr[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + unsigned int uintarr[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + unsigned long ulongarr[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + + float floatarr[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + double doublearr[] = {-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16}; + + if (reduce_add_char (chararr) != (-136 & 0xff)) + __builtin_abort(); + if (reduce_add_short (shortarr) != -136) + __builtin_abort(); + if (reduce_add_int (intarr) != -136) + __builtin_abort(); + if (reduce_add_long (longarr) != -136) + __builtin_abort(); + + if (reduce_add_uchar (uchararr) != 136) + __builtin_abort(); + if (reduce_add_ushort (ushortarr) != 136) + __builtin_abort(); + if (reduce_add_uint (uintarr) != 136) + __builtin_abort(); + if (reduce_add_ulong (ulongarr) != 136) + __builtin_abort(); + + if (reduce_add_float (floatarr) != 136) + __builtin_abort(); + if (reduce_add_double (doublearr) != -136) + __builtin_abort(); + return 0; +} + +/* { dg-final { scan-tree-dump-times "\.REDUC_PLUS" 10 "optimized" } } */ diff --git a/gcc/testsuite/gnat.dg/deref4.adb b/gcc/testsuite/gnat.dg/deref4.adb new file mode 100644 index 0000000..586a6186 --- /dev/null +++ b/gcc/testsuite/gnat.dg/deref4.adb @@ -0,0 +1,9 @@ +-- { dg-do compile } +-- { dg-options "-gnatX" } + +with Deref4_Pkg; use Deref4_Pkg; + +procedure Deref4 is +begin + Obj.Proc (null); +end; diff --git a/gcc/testsuite/gnat.dg/deref4_pkg.ads b/gcc/testsuite/gnat.dg/deref4_pkg.ads new file mode 100644 index 0000000..9410d0d --- /dev/null +++ b/gcc/testsuite/gnat.dg/deref4_pkg.ads @@ -0,0 +1,8 @@ +package Deref4_Pkg is + + type A is tagged null record; + type A_Ptr is access A; + procedure Proc (This : in out A'Class; Some_Parameter : A_Ptr) is null; + Obj : A_Ptr; + +end Deref4_Pkg; diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 9ab46a0..4486a6a 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -9961,7 +9961,8 @@ proc check_effective_target_vect_logical_reduc { } { || [istarget amdgcn-*-*] || [check_effective_target_riscv_v] || [check_effective_target_loongarch_sx] - || [check_effective_target_x86]}] + || [check_effective_target_x86] + || [check_effective_target_s390_vx]}] } # Return 1 if the target supports the fold_extract_last optab. @@ -14528,3 +14529,51 @@ proc check_effective_target_foldable_pi_based_trigonometry { } { } }] } +# +# Return 1 if the x86-64 target enables -mfentry by default, 0 +# otherwise. Cache the result. + +proc check_effective_target_fentry { } { + global tool + global GCC_UNDER_TEST + + if { ![check_effective_target_x86] } { + return 0 + } + + # Need auto-host.h to check linker support. + if { ![file exists ../../auto-host.h ] } { + return 0 + } + + return [check_cached_effective_target fentry { + # Set up and compile to see if ENABLE_X86_64_MFENTRY is + # non-zero. Include the current process ID in the file + # names to prevent conflicts with invocations for multiple + # testsuites. + + set src pie[pid].c + set obj pie[pid].o + + set f [open $src "w"] + puts $f "#include \"../../auto-host.h\"" + puts $f "#if ENABLE_X86_64_MFENTRY == 0 || !defined __x86_64__" + puts $f "# error -mfentry is not enabled by default." + puts $f "#endif" + close $f + + verbose "check_effective_target_fentry compiling testfile $src" 2 + set lines [${tool}_target_compile $src $obj object ""] + + file delete $src + file delete $obj + + if [string match "" $lines] then { + verbose "check_effective_target_fentry testfile compilation passed" 2 + return 1 + } else { + verbose "check_effective_target_fentry testfile compilation failed" 2 + return 0 + } + }] +} diff --git a/gcc/tree.cc b/gcc/tree.cc index 6a055c8..9d3d0ec 100644 --- a/gcc/tree.cc +++ b/gcc/tree.cc @@ -32,6 +32,7 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "backend.h" #include "target.h" +#include "tm_p.h" #include "tree.h" #include "gimple.h" #include "tree-pass.h" |