diff options
132 files changed, 2363 insertions, 159 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 711d040..5d5acc6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2025-07-13 Andrew Pinski <quic_apinski@quicinc.com> + + PR middle-end/120866 + * tree.cc: Add include to tm_p.h. + +2025-07-13 Benjamin Wu <bwu25@cs.washington.edu> + + * gimple.h (GTMA_DOES_GO_IRREVOCABLE): Fix typo. + 2025-07-12 Jan Hubicka <hubicka@ucw.cz> * auto-profile.cc (function_instance::~function_instance): diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 7bcb4c4..eaad352 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250713 +20250714 diff --git a/gcc/ada/sem_ch4.adb b/gcc/ada/sem_ch4.adb index dc81467..56dc7c6 100644 --- a/gcc/ada/sem_ch4.adb +++ b/gcc/ada/sem_ch4.adb @@ -10692,6 +10692,7 @@ package body Sem_Ch4 is or else (Has_Unknown_Discriminants (Typ) + and then Is_Record_Type (Base_Type (Obj_Type)) and then Typ = Underlying_Record_View (Base_Type (Obj_Type))) -- Prefix can be dereferenced diff --git a/gcc/cobol/ChangeLog b/gcc/cobol/ChangeLog index 5555b8e..9ab294d 100644 --- a/gcc/cobol/ChangeLog +++ b/gcc/cobol/ChangeLog @@ -1,3 +1,73 @@ +2025-07-13 Robert Dubner <rdubner@symas.com> + + * Make-lang.in: Eliminate the .cc.o override. + * genapi.cc (level_88_helper): Eliminate cppcheck warning. + (get_level_88_domain): Likewise. + (get_class_condition_string): Likewise. + (parser_call_targets_dump): Likewise. + (parser_compile_ecs): Likewise. + (initialize_variable_internal): Likewise. + (move_tree): Likewise. + (combined_name): Likewise. + (assembler_label): Likewise. + (find_procedure): Likewise. + (parser_perform): Likewise. + (parser_perform_times): Likewise. + (internal_perform_through): Likewise. + (internal_perform_through_times): Likewise. + (psa_FldLiteralN): Likewise. + (psa_FldBlob): Likewise. + (parser_accept): Likewise. + (parser_accept_exception): Likewise. + (parser_accept_exception_end): Likewise. + (parser_accept_command_line): Likewise. + (parser_accept_envar): Likewise. + (parser_display_internal): Likewise. + (parser_display): Likewise. + (parser_assign): Likewise. + (parser_initialize_table): Likewise. + (parser_arith_error): Likewise. + (parser_arith_error_end): Likewise. + (parser_division): Likewise. + (label_fetch): Likewise. + (parser_label_label): Likewise. + (parser_label_goto): Likewise. + (parser_perform_start): Likewise. + (parser_perform_conditional): Likewise. + (parser_perform_conditional_end): Likewise. + (parser_perform_until): Likewise. + (parser_file_delete): Likewise. + (parser_intrinsic_subst): Likewise. + (create_lsearch_address_pairs): Likewise. + (parser_bsearch_start): Likewise. + (is_ascending_key): Likewise. + (parser_sort): Likewise. + (parser_file_sort): Likewise. + (parser_return_start): Likewise. + (parser_file_merge): Likewise. + (parser_string_overflow): Likewise. + (parser_unstring): Likewise. + (parser_string): Likewise. + (parser_call_exception): Likewise. + (create_and_call): Likewise. + (mh_identical): Likewise. + (move_helper): Likewise. + (binary_initial_from_float128): Likewise. + (initial_from_initial): Likewise. + (psa_FldLiteralA): Likewise. + (parser_local_add): Likewise. + (parser_symbol_add): Likewise. + * genapi.h (parser_display): Likewise. + * gengen.cc (gg_call_expr): Explict check for NULL_TREE. + (gg_call): Likewise. + * show_parse.h (SHOW_PARSE_LABEL_OK): Likewise. + (TRACE1_FIELD_VALUE): Likewise. + (CHECK_FIELD): Likewise. + (CHECK_FIELD2): Likewise. + (CHECK_LABEL): Likewise. + * util.cc (cbl_internal_error): Apply [[noreturn]] attribute. + * util.h (cbl_internal_error): Likewise. + 2025-07-11 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> PR cobol/120621 diff --git a/gcc/config.in b/gcc/config.in index ab62c15..353d1bc 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -318,6 +318,12 @@ #endif +/* Define to enable -mfentry by default on x86-64. */ +#ifndef USED_FOR_TARGET +#undef ENABLE_X86_64_MFENTRY +#endif + + /* Define to the name of a file containing a list of extra machine modes for this architecture. */ #ifndef USED_FOR_TARGET diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md index b8bb4cc..bfe368e 100644 --- a/gcc/config/aarch64/aarch64-sme.md +++ b/gcc/config/aarch64/aarch64-sme.md @@ -38,6 +38,7 @@ ;; ---- Binary arithmetic on ZA tile ;; ---- Binary arithmetic on ZA slice ;; ---- Binary arithmetic, writing to ZA slice +;; ---- Absolute minimum/maximum ;; ;; == Ternary arithmetic ;; ---- [INT] Dot product @@ -1264,6 +1265,23 @@ "<sme_int_op>\tza.<Vetype>[%w0, %1, vgx<vector_count>], %2, %3.<Vetype>" ) +;; ------------------------------------------------------------------------- +;; ---- Absolute minimum/maximum +;; ------------------------------------------------------------------------- +;; Includes: +;; - svamin (SME2+faminmax) +;; - svamin (SME2+faminmax) +;; ------------------------------------------------------------------------- + +(define_insn "@aarch64_sme_<faminmax_uns_op><mode>" + [(set (match_operand:SVE_Fx24 0 "register_operand" "=Uw<vector_count>") + (unspec:SVE_Fx24 [(match_operand:SVE_Fx24 1 "register_operand" "%0") + (match_operand:SVE_Fx24 2 "register_operand" "Uw<vector_count>")] + FAMINMAX_UNS))] + "TARGET_SME2 && TARGET_FAMINMAX" + "<faminmax_uns_op>\t%0, %1, %2" +) + ;; ========================================================================= ;; == Ternary arithmetic ;; ========================================================================= diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def b/gcc/config/aarch64/aarch64-sve-builtins-sme.def index f75c0a5..8e6aadc 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def @@ -92,6 +92,11 @@ DEF_SME_FUNCTION (svstr_zt, str_zt, none, none) DEF_SME_FUNCTION (svzero_zt, inherent_zt, none, none) #undef REQUIRED_EXTENSIONS +#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2 && AARCH64_FL_FAMINMAX) +DEF_SME_FUNCTION_GS (svamin, binary_opt_single_n, all_float, x24, none) +DEF_SME_FUNCTION_GS (svamax, binary_opt_single_n, all_float, x24, none) +#undef REQUIRED_EXTENSIONS + /* The d_za entries in this section just declare C _za64 overloads, which will then be resolved to either an integer function or a floating-point function. They are needed because the integer and diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc index abe21a8..73004a8 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc @@ -930,6 +930,44 @@ public: unsigned int m_bits; }; +/* The same as cond_or_uncond_unspec_function but the intrinsics with vector + modes are SME2 extensions instead of SVE. */ +class faminmaximpl : public function_base +{ +public: + CONSTEXPR faminmaximpl (int cond_unspec, int uncond_unspec) + : m_cond_unspec (cond_unspec), m_uncond_unspec (uncond_unspec) + {} + + rtx + expand (function_expander &e) const override + { + if (e.group_suffix ().vectors_per_tuple > 1) + { + /* SME2+faminmax intrinsics. */ + gcc_assert (e.pred == PRED_none); + auto mode = e.tuple_mode (0); + auto icode = (code_for_aarch64_sme (m_uncond_unspec, mode)); + return e.use_exact_insn (icode); + } + /* SVE+faminmax intrinsics. */ + else if (e.pred == PRED_none) + { + auto mode = e.tuple_mode (0); + auto icode = (e.mode_suffix_id == MODE_single + ? code_for_aarch64_sve_single (m_uncond_unspec, mode) + : code_for_aarch64_sve (m_uncond_unspec, mode)); + return e.use_exact_insn (icode); + } + return e.map_to_unspecs (m_cond_unspec, m_cond_unspec, m_cond_unspec); + } + + /* The unspecs for the conditional and unconditional instructions, + respectively. */ + int m_cond_unspec; + int m_uncond_unspec; +}; + } /* end anonymous namespace */ namespace aarch64_sve { @@ -958,10 +996,8 @@ FUNCTION (svaesd, fixed_insn_function, (CODE_FOR_aarch64_sve2_aesd)) FUNCTION (svaese, fixed_insn_function, (CODE_FOR_aarch64_sve2_aese)) FUNCTION (svaesimc, fixed_insn_function, (CODE_FOR_aarch64_sve2_aesimc)) FUNCTION (svaesmc, fixed_insn_function, (CODE_FOR_aarch64_sve2_aesmc)) -FUNCTION (svamax, cond_or_uncond_unspec_function, - (UNSPEC_COND_FAMAX, UNSPEC_FAMAX)) -FUNCTION (svamin, cond_or_uncond_unspec_function, - (UNSPEC_COND_FAMIN, UNSPEC_FAMIN)) +FUNCTION (svamax, faminmaximpl, (UNSPEC_COND_FAMAX, UNSPEC_FAMAX)) +FUNCTION (svamin, faminmaximpl, (UNSPEC_COND_FAMIN, UNSPEC_FAMIN)) FUNCTION (svandqv, reduction, (UNSPEC_ANDQV, UNSPEC_ANDQV, -1)) FUNCTION (svbcax, CODE_FOR_MODE0 (aarch64_sve2_bcax),) FUNCTION (svbdep, unspec_based_function, (UNSPEC_BDEP, UNSPEC_BDEP, -1)) diff --git a/gcc/config/darwin-driver.cc b/gcc/config/darwin-driver.cc index 224e0a0..e83b7cd 100644 --- a/gcc/config/darwin-driver.cc +++ b/gcc/config/darwin-driver.cc @@ -64,7 +64,8 @@ validate_macosx_version_min (const char *version_str) major = strtoul (version_str, &end, 10); - /* macOS 10, 11, and 12 are known. clang accepts up to 99. */ + /* macOS 10, 11, 12, 13, 14, 15 and 26 are known. + clang accepts up to 99. */ if (major < 10 || major > 99) return NULL; @@ -159,15 +160,16 @@ darwin_find_version_from_kernel (void) if (*version_p++ != '.') goto parse_failed; - /* Darwin20 sees a transition to macOS 11. In this, it seems that the - mapping to macOS minor version and patch level is now always 0, 0 - (at least for macOS 11 and 12). */ - if (major_vers >= 20) - { - /* Apple clang doesn't include the minor version or the patch level - in the object file, nor does it pass it to ld */ - asprintf (&new_flag, "%d.00.00", major_vers - 9); - } + /* Darwin25 saw a transition to macOS 26. */ + if (major_vers >= 25) + /* Apple clang doesn't include the minor version or the patch level + in the object file, nor does it pass it to ld */ + asprintf (&new_flag, "%d.00.00", major_vers + 1); + /* Darwin20 saw a transition to macOS 11. */ + else if (major_vers >= 20) + /* Apple clang doesn't include the minor version or the patch level + in the object file, nor does it pass it to ld */ + asprintf (&new_flag, "%d.00.00", major_vers - 9); else if (major_vers - 4 <= 4) /* On 10.4 and earlier, the old linker is used which does not support three-component system versions. diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 09cb133..5365849 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -2839,7 +2839,9 @@ ix86_option_override_internal (bool main_args_p, /* Set the default value for -mfentry. */ if (!opts_set->x_flag_fentry) - opts->x_flag_fentry = TARGET_SEH; + opts->x_flag_fentry = (TARGET_SEH + || (TARGET_64BIT_P (opts->x_ix86_isa_flags) + && ENABLE_X86_64_MFENTRY)); else { if (!TARGET_64BIT_P (opts->x_ix86_isa_flags) && opts->x_flag_pic @@ -2850,6 +2852,13 @@ ix86_option_override_internal (bool main_args_p, sorry ("%<-mno-fentry%> isn%'t compatible with SEH"); } + if (!opts->x_flag_fentry + && (TARGET_64BIT_P (opts->x_ix86_isa_flags) || !opts->x_flag_pic) + && opts->x_flag_shrink_wrap + && opts->x_profile_flag) + warning (0, "%<-pg%> without %<-mfentry%> may be unreliable with " + "shrink wrapping"); + if (TARGET_SEH && TARGET_CALL_MS2SYSV_XLOGUES) sorry ("%<-mcall-ms2sysv-xlogues%> isn%'t currently supported with SEH"); diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 3f7ad68..bfc6c6f 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2465,10 +2465,11 @@ constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_ALDERLAKE | PTA_AVXIFMA | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_UINTR; constexpr wide_int_bitmask PTA_ARROWLAKE_S = PTA_ARROWLAKE | PTA_AVXVNNIINT16 | PTA_SHA512 | PTA_SM3 | PTA_SM4; -constexpr wide_int_bitmask PTA_CLEARWATERFOREST = PTA_SIERRAFOREST - | PTA_AVXVNNIINT16 | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_USER_MSR - | PTA_PREFETCHI; -constexpr wide_int_bitmask PTA_PANTHERLAKE = PTA_ARROWLAKE_S | PTA_PREFETCHI; +constexpr wide_int_bitmask PTA_CLEARWATERFOREST = + (PTA_SIERRAFOREST & (~(PTA_KL | PTA_WIDEKL))) | PTA_AVXVNNIINT16 | PTA_SHA512 + | PTA_SM3 | PTA_SM4 | PTA_USER_MSR | PTA_PREFETCHI; +constexpr wide_int_bitmask PTA_PANTHERLAKE = + (PTA_ARROWLAKE_S & (~(PTA_KL | PTA_WIDEKL))) | PTA_PREFETCHI; constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_GRANITERAPIDS_D | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 | PTA_AVXVNNIINT8 | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2 diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 8df7f64..f372f0e 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1725,6 +1725,8 @@ ;; - vfmsac.vf ;; - vfnmacc.vf ;; - vfnmsac.vf +;; - vfwmacc.vf +;; - vfwmsac.vf ;; ============================================================================= ;; vfmadd.vf, vfmsub.vf, vfmacc.vf, vfmsac.vf @@ -1796,3 +1798,49 @@ } [(set_attr "type" "vfmuladd")] ) + +;; vfwmacc.vf, vfwmsac.vf +(define_insn_and_split "*vfwmacc_vf_<mode>" + [(set (match_operand:VWEXTF 0 "register_operand") + (plus_minus:VWEXTF + (mult:VWEXTF + (float_extend:VWEXTF + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand")) + (vec_duplicate:VWEXTF + (float_extend:<VEL> + (match_operand:<VSUBEL> 2 "register_operand")))) + (match_operand:VWEXTF 1 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + rtx ops[] = {operands[0], operands[1], operands[2], operands[3]}; + riscv_vector::emit_vlmax_insn (code_for_pred_widen_mul_scalar (<CODE>, <MODE>mode), + riscv_vector::WIDEN_TERNARY_OP_FRM_DYN, ops); + DONE; + } + [(set_attr "type" "vfwmuladd")] +) + +;; Intermediate pattern for vfwmacc.vf and vfwmsac.vf used by combine +(define_insn_and_split "*extend_vf_<mode>" + [(set (match_operand:VWEXTF 0 "register_operand") + (vec_duplicate:VWEXTF + (float_extend:<VEL> + (match_operand:<VSUBEL> 1 "register_operand"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + rtx tmp = gen_reg_rtx (<VEL>mode); + emit_insn (gen_extend<vsubel><vel>2(tmp, operands[1])); + + rtx ops[] = {operands[0], tmp}; + riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode), + riscv_vector::UNARY_OP, ops); + DONE; + } + [(set_attr "type" "vfwmuladd")] +) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index e60e3a8..5f6cc42 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -2418,6 +2418,47 @@ (RVVM1x2DF "rvvm1df") ]) +(define_mode_attr vsubel [ + (RVVM8HI "qi") (RVVM4HI "qi") (RVVM2HI "qi") (RVVM1HI "qi") (RVVMF2HI "qi") (RVVMF4HI "qi") + + (RVVM8SI "hi") (RVVM4SI "hi") (RVVM2SI "hi") (RVVM1SI "hi") (RVVMF2SI "hi") + + (RVVM8SF "hf") (RVVM4SF "hf") (RVVM2SF "hf") (RVVM1SF "hf") (RVVMF2SF "hf") + + (RVVM8DI "si") (RVVM4DI "si") (RVVM2DI "si") (RVVM1DI "si") + + (RVVM8DF "sf") (RVVM4DF "sf") (RVVM2DF "sf") (RVVM1DF "sf") + + ;; VLS modes. + (V1HI "qi") (V2HI "qi") (V4HI "qi") (V8HI "qi") (V16HI "qi") (V32HI "qi") (V64HI "qi") (V128HI "qi") (V256HI "qi") + (V512HI "qi") (V1024HI "qi") (V2048HI "qi") + (V1SI "hi") (V2SI "hi") (V4SI "hi") (V8SI "hi") (V16SI "hi") (V32SI "hi") (V64SI "hi") (V128SI "hi") (V256SI "hi") + (V512SI "hi") (V1024SI "hi") + (V1DI "si") (V2DI "si") (V4DI "si") (V8DI "si") (V16DI "si") (V32DI "si") (V64DI "si") (V128DI "si") (V256DI "si") (V512DI "si") + + (V1SF "hf") + (V2SF "hf") + (V4SF "hf") + (V8SF "hf") + (V16SF "hf") + (V32SF "hf") + (V64SF "hf") + (V128SF "hf") + (V256SF "hf") + (V512SF "hf") + (V1024SF "hf") + (V1DF "sf") + (V2DF "sf") + (V4DF "sf") + (V8DF "sf") + (V16DF "sf") + (V32DF "sf") + (V64DF "sf") + (V128DF "sf") + (V256DF "sf") + (V512DF "sf") +]) + (define_mode_attr VSUBEL [ (RVVM8HI "QI") (RVVM4HI "QI") (RVVM2HI "QI") (RVVM1HI "QI") (RVVMF2HI "QI") (RVVMF4HI "QI") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index c5b23b3..baf215b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7299,10 +7299,10 @@ (plus_minus:VWEXTF (mult:VWEXTF (float_extend:VWEXTF - (vec_duplicate:<V_DOUBLE_TRUNC> - (match_operand:<VSUBEL> 3 "register_operand" " f"))) - (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))) + (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")) + (vec_duplicate:VWEXTF + (float_extend:<VEL> + (match_operand:<VSUBEL> 3 "register_operand" " f")))) (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" diff --git a/gcc/configure b/gcc/configure index f056cfe..7537da2 100755 --- a/gcc/configure +++ b/gcc/configure @@ -1064,6 +1064,7 @@ enable_versioned_jit enable_default_pie enable_cet enable_s390_excess_float_precision +enable_x86_64_mfentry ' ac_precious_vars='build_alias host_alias @@ -1842,6 +1843,7 @@ Optional Features: --enable-s390-excess-float-precision on s390 targets, evaluate float with double precision when in standards-conforming mode + --enable-x86-64-mfentry enable -mfentry by default on x86-64 targets Optional Packages: --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] @@ -21520,7 +21522,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 21523 "configure" +#line 21525 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -21626,7 +21628,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 21629 "configure" +#line 21631 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -35022,6 +35024,46 @@ $as_echo "#define ENABLE_S390_EXCESS_FLOAT_PRECISION 1" >>confdefs.h ;; esac +# On x86-64, when profiling is enabled with shrink wrapping, the mcount +# call may not be placed at the function entry after +# pushq %rbp +# movq %rsp,%rbp +# As the result, the profile data may be skewed which makes PGO less +# effective: +# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120881 +# Enable -mfentry by default on x86-64 to put the profiling counter call +# before the prologue. +# Check whether --enable-x86-64-mfentry was given. +if test "${enable_x86_64_mfentry+set}" = set; then : + enableval=$enable_x86_64_mfentry; case "${enableval}" in + yes | no | auto) + enable_x86_64_mfentry=$enableval + ;; + *) + as_fn_error $? "'$enable_x86_64_mfentry' is an invalid value for --enable-x86-64-mfentry. Valid choices are 'yes', 'no' and 'auto'." "$LINENO" 5 + ;; + esac +else + enable_x86_64_mfentry=auto +fi + + +if test x"$enable_x86_64_mfentry" = xauto; then + case "${target}" in + i?86-*-*gnu* | x86_64-*-*gnu*) + # Enable -mfentry by default with glibc on x86. + enable_x86_64_mfentry=yes + ;; + esac +fi + +gif=`if test x$enable_x86_64_mfentry = xyes; then echo 1; else echo 0; fi` + +cat >>confdefs.h <<_ACEOF +#define ENABLE_X86_64_MFENTRY $gif +_ACEOF + + # Check if the linker supports '-z now' ld_now_support=no { $as_echo "$as_me:${as_lineno-$LINENO}: checking linker -z now option" >&5 diff --git a/gcc/configure.ac b/gcc/configure.ac index 58bf63f..24e0aa6 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -7972,6 +7972,41 @@ standards-compatible mode on s390 targets.]) ;; esac +# On x86-64, when profiling is enabled with shrink wrapping, the mcount +# call may not be placed at the function entry after +# pushq %rbp +# movq %rsp,%rbp +# As the result, the profile data may be skewed which makes PGO less +# effective: +# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120881 +# Enable -mfentry by default on x86-64 to put the profiling counter call +# before the prologue. +AC_ARG_ENABLE(x86-64-mfentry, + [AS_HELP_STRING([--enable-x86-64-mfentry], + [enable -mfentry by default on x86-64 targets])], + [case "${enableval}" in + yes | no | auto) + enable_x86_64_mfentry=$enableval + ;; + *) + AC_MSG_ERROR(['$enable_x86_64_mfentry' is an invalid value for --enable-x86-64-mfentry. Valid choices are 'yes', 'no' and 'auto'.]) + ;; + esac], + [enable_x86_64_mfentry=auto]) + +if test x"$enable_x86_64_mfentry" = xauto; then + case "${target}" in + i?86-*-*gnu* | x86_64-*-*gnu*) + # Enable -mfentry by default with glibc on x86. + enable_x86_64_mfentry=yes + ;; + esac +fi + +gif=`if test x$enable_x86_64_mfentry = xyes; then echo 1; else echo 0; fi` +AC_DEFINE_UNQUOTED(ENABLE_X86_64_MFENTRY, $gif, +[Define to enable -mfentry by default on x86-64.]) + # Check if the linker supports '-z now' ld_now_support=no AC_MSG_CHECKING(linker -z now option) diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 80ee2cd..09ea87a 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -2667,6 +2667,17 @@ target binutils supports @code{Intel CET} instructions and disabled otherwise. In this case, the target libraries are configured to get additional @option{-fcf-protection} option. +@item --enable-x86-64-mfentry +@itemx --disable-x86-64-mfentry +Enable @option {-mfentry} by default on x86-64 to put the profiling +counter call, @code{__fentry__}, before the prologue so that @option{-pg} +can be used with @option{-fshrink-wrap} which is enabled at @option{-O1}. +This configure option is 64-bit only because @code{__fentry__} doesn't +support PIC in 32-bit mode. + +@option{--enable-x86-64-mfentry=auto} is default. @option{-mfentry} is +enabled on Linux/x86-64 by default. + @item --with-riscv-attribute=@samp{yes}, @samp{no} or @samp{default} Generate RISC-V attribute by default, in order to record extra build information in object. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9a1aa37..f60865b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -34892,9 +34892,9 @@ Intel Panther Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, -VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR, AVXIFMA, -AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and -PREFETCHI instruction set support. +VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, UINTR, AVXIFMA, AVXVNNIINT8, +AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and PREFETCHI +instruction set support. @item sapphirerapids @itemx emeraldrapids @@ -34997,9 +34997,9 @@ Intel Clearwater Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, -LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -ENQCMD, UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, -SHA512, SM3, SM4, USER_MSR and PREFETCHI instruction set support. +LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, ENQCMD, +UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, +SM3, SM4, USER_MSR and PREFETCHI instruction set support. @item k6 AMD K6 CPU with MMX instruction set support. diff --git a/gcc/testsuite/gcc.dg/20021014-1.c b/gcc/testsuite/gcc.dg/20021014-1.c index e43f7b2..f5f6fcf 100644 --- a/gcc/testsuite/gcc.dg/20021014-1.c +++ b/gcc/testsuite/gcc.dg/20021014-1.c @@ -2,6 +2,7 @@ /* { dg-require-profiling "-p" } */ /* { dg-options "-O2 -p" } */ /* { dg-options "-O2 -p -static" { target hppa*-*-hpux* } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ /* { dg-error "profiler" "No profiler support" { target xstormy16-*-* } 0 } */ /* { dg-message "" "consider using `-pg' instead of `-p' with gprof(1)" { target *-*-freebsd* } 0 } */ diff --git a/gcc/testsuite/gcc.dg/aru-2.c b/gcc/testsuite/gcc.dg/aru-2.c index 054223c..102ece1 100644 --- a/gcc/testsuite/gcc.dg/aru-2.c +++ b/gcc/testsuite/gcc.dg/aru-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ static int __attribute__((noinline)) bar (int x) diff --git a/gcc/testsuite/gcc.dg/darwin-minversion-link.c b/gcc/testsuite/gcc.dg/darwin-minversion-link.c index af712a1b..55f7c7e 100644 --- a/gcc/testsuite/gcc.dg/darwin-minversion-link.c +++ b/gcc/testsuite/gcc.dg/darwin-minversion-link.c @@ -20,6 +20,7 @@ /* { dg-additional-options "-mmacosx-version-min=013.000.00 -DCHECK=130000" { target *-*-darwin22* } } */ /* { dg-additional-options "-mmacosx-version-min=014.000.00 -DCHECK=140000" { target *-*-darwin23* } } */ /* { dg-additional-options "-mmacosx-version-min=015.000.00 -DCHECK=150000" { target *-*-darwin24* } } */ +/* { dg-additional-options "-mmacosx-version-min=026.000.00 -DCHECK=260000" { target *-*-darwin25* } } */ int main () diff --git a/gcc/testsuite/gcc.dg/nest.c b/gcc/testsuite/gcc.dg/nest.c index 5734c11..9221ed1 100644 --- a/gcc/testsuite/gcc.dg/nest.c +++ b/gcc/testsuite/gcc.dg/nest.c @@ -3,6 +3,7 @@ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ /* { dg-options "-O2 -pg -static" { target hppa*-*-hpux* } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ /* { dg-error "profiler" "No profiler support" { target xstormy16-*-* } 0 } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/pr32450.c b/gcc/testsuite/gcc.dg/pr32450.c index 9606e30..4aaeb7d 100644 --- a/gcc/testsuite/gcc.dg/pr32450.c +++ b/gcc/testsuite/gcc.dg/pr32450.c @@ -3,7 +3,7 @@ /* { dg-do run } */ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ -/* { dg-options "-O2 -pg -mtune=core2" { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-O2 -pg -mtune=core2 -mfentry -fno-pic" { target { i?86-*-* x86_64-*-* } } } */ /* { dg-options "-O2 -pg -static" { target hppa*-*-hpux* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/pr43643.c b/gcc/testsuite/gcc.dg/pr43643.c index 43896ab..a62586d 100644 --- a/gcc/testsuite/gcc.dg/pr43643.c +++ b/gcc/testsuite/gcc.dg/pr43643.c @@ -4,6 +4,7 @@ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ /* { dg-options "-O2 -pg -static" { target hppa*-*-hpux* } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ extern char *strdup (const char *); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c new file mode 100644 index 0000000..90b5438 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c @@ -0,0 +1,97 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat16x2_t, z0, + svamax_f16_x2 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat16x2_t, z0, + svamax_f16_x2 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.h - z29\.h} +** | +** famax [^\n]+, {z28\.h - z29\.h} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat16x2_t, z0, + svamax_f16_x2 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** famax {z18\.h - z19\.h}, {z18\.h - z19\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat16x2_t, z18, + svamax_f16_x2 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z18\.h - z19\.h} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z18, svfloat16x2_t, z23, + svamax_f16_x2 (z23, z18), + svamax (z23, z18)) + +/* +** amax_z28_z28_z0: +** famax {z28\.h - z29\.h}, {z28\.h - z29\.h}, {z0\.h - z1\.h} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat16x2_t, z28, + svamax_f16_x2 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** famax {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z18\.h - z19\.h} +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat16x2_t, z0, + svamax_f16_x2 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** | +** famax {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat16x2_t, z4, + svamax_f16_x2 (z4, z23), + svamax (z4, z23)) + diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c new file mode 100644 index 0000000..d168ad7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat16x4_t, z0, + svamax_f16_x4 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat16x4_t, z0, + svamax_f16_x4 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.h - z31\.h} +** | +** famax [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat16x4_t, z0, + svamax_f16_x4 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z4\.h - z7\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat16x4_t, z18, + svamax_f16_x4 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z28, svfloat16x4_t, z23, + svamax_f16_x4 (z23, z28), + svamax (z23, z28)) + +/* +** amax_z28_z28_z0: +** famax {z28\.h - z31\.h}, {z28\.h - z31\.h}, {z0\.h - z3\.h} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat16x4_t, z28, + svamax_f16_x4 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** | +** famax {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat16x4_t, z0, + svamax_f16_x4 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** | +** famax {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat16x4_t, z4, + svamax_f16_x4 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c new file mode 100644 index 0000000..618d50b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat32x2_t, z0, + svamax_f32_x2 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat32x2_t, z0, + svamax_f32_x2 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.s - z29\.s} +** | +** famax [^\n]+, {z28\.s - z29\.s} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat32x2_t, z0, + svamax_f32_x2 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** famax {z18\.s - z19\.s}, {z18\.s - z19\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat32x2_t, z18, + svamax_f32_x2 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z18\.s - z19\.s} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z18, svfloat32x2_t, z23, + svamax_f32_x2 (z23, z18), + svamax (z23, z18)) + +/* +** amax_z28_z28_z0: +** famax {z28\.s - z29\.s}, {z28\.s - z29\.s}, {z0\.s - z1\.s} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat32x2_t, z28, + svamax_f32_x2 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** famax {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z18\.s - z19\.s} +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat32x2_t, z0, + svamax_f32_x2 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** | +** famax {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat32x2_t, z4, + svamax_f32_x2 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c new file mode 100644 index 0000000..981e78c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c @@ -0,0 +1,129 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat32x4_t, z0, + svamax_f32_x4 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat32x4_t, z0, + svamax_f32_x4 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.s - z31\.s} +** | +** famax [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat32x4_t, z0, + svamax_f32_x4 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z4\.s - z7\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat32x4_t, z18, + svamax_f32_x4 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z28, svfloat32x4_t, z23, + svamax_f32_x4 (z23, z28), + svamax (z23, z28)) + +/* +** amax_z28_z28_z0: +** famax {z28\.s - z31\.s}, {z28\.s - z31\.s}, {z0\.s - z3\.s} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat32x4_t, z28, + svamax_f32_x4 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** | +** famax {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat32x4_t, z0, + svamax_f32_x4 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** | +** famax {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat32x4_t, z4, + svamax_f32_x4 (z4, z23), + svamax (z4, z23)) + diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c new file mode 100644 index 0000000..e93a409 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat64x2_t, z0, + svamax_f64_x2 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat64x2_t, z0, + svamax_f64_x2 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.d - z29\.d} +** | +** famax [^\n]+, {z28\.d - z29\.d} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat64x2_t, z0, + svamax_f64_x2 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** famax {z18\.d - z19\.d}, {z18\.d - z19\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat64x2_t, z18, + svamax_f64_x2 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z18\.d - z19\.d} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z18, svfloat64x2_t, z23, + svamax_f64_x2 (z23, z18), + svamax (z23, z18)) + +/* +** amax_z28_z28_z0: +** famax {z28\.d - z29\.d}, {z28\.d - z29\.d}, {z0\.d - z1\.d} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat64x2_t, z28, + svamax_f64_x2 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** famax {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z18\.d - z19\.d} +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat64x2_t, z0, + svamax_f64_x2 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** | +** famax {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat64x2_t, z4, + svamax_f64_x2 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c new file mode 100644 index 0000000..2db629e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amax_z0_z0_z4: +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amax_z0_z0_z4, svfloat64x4_t, z0, + svamax_f64_x4 (z0, z4), + svamax (z0, z4)) + +/* +** amax_z0_z4_z0: +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amax_z0_z4_z0, svfloat64x4_t, z0, + svamax_f64_x4 (z4, z0), + svamax (z4, z0)) + +/* +** amax_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.d - z31\.d} +** | +** famax [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z4_z28, svfloat64x4_t, z0, + svamax_f64_x4 (z4, z28), + svamax (z4, z28)) + +/* +** amax_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z4\.d - z7\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z18_z18_z4, svfloat64x4_t, z18, + svamax_f64_x4 (z18, z4), + svamax (z18, z4)) + +/* +** amax_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amax_z23_z23_z28, svfloat64x4_t, z23, + svamax_f64_x4 (z23, z28), + svamax (z23, z28)) + +/* +** amax_z28_z28_z0: +** famax {z28\.d - z31\.d}, {z28\.d - z31\.d}, {z0\.d - z3\.d} +** ret +*/ +TEST_XN (amax_z28_z28_z0, svfloat64x4_t, z28, + svamax_f64_x4 (z28, z0), + svamax (z28, z0)) + +/* +** amax_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** | +** famax {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z0_z0_z18, svfloat64x4_t, z0, + svamax_f64_x4 (z0, z18), + svamax (z0, z18)) + +/* +** amax_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famax {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** | +** famax {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amax_z4_z4_z23, svfloat64x4_t, z4, + svamax_f64_x4 (z4, z23), + svamax (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c new file mode 100644 index 0000000..74604e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat16x2_t, z0, + svamin_f16_x2 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat16x2_t, z0, + svamin_f16_x2 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.h - z29\.h} +** | +** famin [^\n]+, {z28\.h - z29\.h} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat16x2_t, z0, + svamin_f16_x2 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** famin {z18\.h - z19\.h}, {z18\.h - z19\.h}, {z4\.h - z5\.h} +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat16x2_t, z18, + svamin_f16_x2 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z18\.h - z19\.h} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z18, svfloat16x2_t, z23, + svamin_f16_x2 (z23, z18), + svamin (z23, z18)) + +/* +** amin_z28_z28_z0: +** famin {z28\.h - z29\.h}, {z28\.h - z29\.h}, {z0\.h - z1\.h} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat16x2_t, z28, + svamin_f16_x2 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** famin {z0\.h - z1\.h}, {z0\.h - z1\.h}, {z18\.h - z19\.h} +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat16x2_t, z0, + svamin_f16_x2 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** | +** famin {z4\.h - z5\.h}, {z4\.h - z5\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat16x2_t, z4, + svamin_f16_x2 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c new file mode 100644 index 0000000..bc3779b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat16x4_t, z0, + svamin_f16_x4 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, {z4\.h - z7\.h} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat16x4_t, z0, + svamin_f16_x4 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.h - z31\.h} +** | +** famin [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat16x4_t, z0, + svamin_f16_x4 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z4\.h - z7\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat16x4_t, z18, + svamin_f16_x4 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.h - z31\.h} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z28, svfloat16x4_t, z23, + svamin_f16_x4 (z23, z28), + svamin (z23, z28)) + +/* +** amin_z28_z28_z0: +** famin {z28\.h - z31\.h}, {z28\.h - z31\.h}, {z0\.h - z3\.h} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat16x4_t, z28, + svamin_f16_x4 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** | +** famin {z0\.h - z3\.h}, {z0\.h - z3\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat16x4_t, z0, + svamin_f16_x4 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** | +** famin {z4\.h - z7\.h}, {z4\.h - z7\.h}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat16x4_t, z4, + svamin_f16_x4 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c new file mode 100644 index 0000000..43e3075 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat32x2_t, z0, + svamin_f32_x2 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat32x2_t, z0, + svamin_f32_x2 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.s - z29\.s} +** | +** famin [^\n]+, {z28\.s - z29\.s} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat32x2_t, z0, + svamin_f32_x2 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** famin {z18\.s - z19\.s}, {z18\.s - z19\.s}, {z4\.s - z5\.s} +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat32x2_t, z18, + svamin_f32_x2 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z18\.s - z19\.s} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z18, svfloat32x2_t, z23, + svamin_f32_x2 (z23, z18), + svamin (z23, z18)) + +/* +** amin_z28_z28_z0: +** famin {z28\.s - z29\.s}, {z28\.s - z29\.s}, {z0\.s - z1\.s} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat32x2_t, z28, + svamin_f32_x2 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** famin {z0\.s - z1\.s}, {z0\.s - z1\.s}, {z18\.s - z19\.s} +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat32x2_t, z0, + svamin_f32_x2 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** | +** famin {z4\.s - z5\.s}, {z4\.s - z5\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat32x2_t, z4, + svamin_f32_x2 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c new file mode 100644 index 0000000..6bd20f8f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat32x4_t, z0, + svamin_f32_x4 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, {z4\.s - z7\.s} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat32x4_t, z0, + svamin_f32_x4 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.s - z31\.s} +** | +** famin [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat32x4_t, z0, + svamin_f32_x4 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z4\.s - z7\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat32x4_t, z18, + svamin_f32_x4 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.s - z31\.s} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z28, svfloat32x4_t, z23, + svamin_f32_x4 (z23, z28), + svamin (z23, z28)) + +/* +** amin_z28_z28_z0: +** famin {z28\.s - z31\.s}, {z28\.s - z31\.s}, {z0\.s - z3\.s} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat32x4_t, z28, + svamin_f32_x4 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** | +** famin {z0\.s - z3\.s}, {z0\.s - z3\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat32x4_t, z0, + svamin_f32_x4 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** | +** famin {z4\.s - z7\.s}, {z4\.s - z7\.s}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat32x4_t, z4, + svamin_f32_x4 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c new file mode 100644 index 0000000..3bbef3f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat64x2_t, z0, + svamin_f64_x2 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat64x2_t, z0, + svamin_f64_x2 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.d - z29\.d} +** | +** famin [^\n]+, {z28\.d - z29\.d} +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat64x2_t, z0, + svamin_f64_x2 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** famin {z18\.d - z19\.d}, {z18\.d - z19\.d}, {z4\.d - z5\.d} +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat64x2_t, z18, + svamin_f64_x2 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z18: +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z18\.d - z19\.d} +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z18, svfloat64x2_t, z23, + svamin_f64_x2 (z23, z18), + svamin (z23, z18)) + +/* +** amin_z28_z28_z0: +** famin {z28\.d - z29\.d}, {z28\.d - z29\.d}, {z0\.d - z1\.d} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat64x2_t, z28, + svamin_f64_x2 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** famin {z0\.d - z1\.d}, {z0\.d - z1\.d}, {z18\.d - z19\.d} +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat64x2_t, z0, + svamin_f64_x2 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** | +** famin {z4\.d - z5\.d}, {z4\.d - z5\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat64x2_t, z4, + svamin_f64_x2 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c new file mode 100644 index 0000000..6f4c9b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+faminmax" + +/* +** amin_z0_z0_z4: +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amin_z0_z0_z4, svfloat64x4_t, z0, + svamin_f64_x4 (z0, z4), + svamin (z0, z4)) + +/* +** amin_z0_z4_z0: +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, {z4\.d - z7\.d} +** ret +*/ +TEST_XN (amin_z0_z4_z0, svfloat64x4_t, z0, + svamin_f64_x4 (z4, z0), + svamin (z4, z0)) + +/* +** amin_z0_z4_z28: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.d - z31\.d} +** | +** famin [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z4_z28, svfloat64x4_t, z0, + svamin_f64_x4 (z4, z28), + svamin (z4, z28)) + +/* +** amin_z18_z18_z4: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z4\.d - z7\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z18_z18_z4, svfloat64x4_t, z18, + svamin_f64_x4 (z18, z4), + svamin (z18, z4)) + +/* +** amin_z23_z23_z28: +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin [^\n]+, {z28\.d - z31\.d} +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ret +*/ +TEST_XN (amin_z23_z23_z28, svfloat64x4_t, z23, + svamin_f64_x4 (z23, z28), + svamin (z23, z28)) + +/* +** amin_z28_z28_z0: +** famin {z28\.d - z31\.d}, {z28\.d - z31\.d}, {z0\.d - z3\.d} +** ret +*/ +TEST_XN (amin_z28_z28_z0, svfloat64x4_t, z28, + svamin_f64_x4 (z28, z0), + svamin (z28, z0)) + +/* +** amin_z0_z0_z18: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** | +** famin {z0\.d - z3\.d}, {z0\.d - z3\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z0_z0_z18, svfloat64x4_t, z0, + svamin_f64_x4 (z0, z18), + svamin (z0, z18)) + +/* +** amin_z4_z4_z23: +** ( +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** famin {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** | +** famin {z4\.d - z7\.d}, {z4\.d - z7\.d}, [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** mov [^\n]+ +** ) +** ret +*/ +TEST_XN (amin_z4_z4_z23, svfloat64x4_t, z4, + svamin_f64_x4 (z4, z23), + svamin (z4, z23)) diff --git a/gcc/testsuite/gcc.target/i386/pr104447.c b/gcc/testsuite/gcc.target/i386/pr104447.c index cb618c7..f58170d 100644 --- a/gcc/testsuite/gcc.target/i386/pr104447.c +++ b/gcc/testsuite/gcc.target/i386/pr104447.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-profiling "-pg" } */ -/* { dg-options "-O2 -pg" } */ +/* { dg-options "-O2 -pg -mfentry -fno-pic" } */ int bar (int x) diff --git a/gcc/testsuite/gcc.target/i386/pr113122-3.c b/gcc/testsuite/gcc.target/i386/pr113122-3.c index 71aa240..c46805d 100644 --- a/gcc/testsuite/gcc.target/i386/pr113122-3.c +++ b/gcc/testsuite/gcc.target/i386/pr113122-3.c @@ -1,7 +1,7 @@ /* PR target/113122 */ /* { dg-do assemble { target *-*-linux* } } */ /* { dg-require-effective-target masm_intel } */ -/* { dg-options "-fprofile -O2 -masm=intel" } */ +/* { dg-options "-fprofile -mfentry -fno-pic -O2 -masm=intel" } */ void func (void) diff --git a/gcc/testsuite/gcc.target/i386/pr119386-1.c b/gcc/testsuite/gcc.target/i386/pr119386-1.c index 9a0dc64..39a3e1d 100644 --- a/gcc/testsuite/gcc.target/i386/pr119386-1.c +++ b/gcc/testsuite/gcc.target/i386/pr119386-1.c @@ -1,7 +1,9 @@ /* PR target/119386 */ /* { dg-do compile { target *-*-linux* } } */ /* { dg-options "-O2 -fpic -pg" } */ -/* { dg-final { scan-assembler "call\[ \t\]+mcount@PLT" } } */ +/* { dg-additional-options "-mfentry" { target { ! ia32 } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+mcount@PLT" { target ia32 } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+__fentry__@PLT" { target { ! ia32 } } } } */ int main () diff --git a/gcc/testsuite/gcc.target/i386/pr119386-2.c b/gcc/testsuite/gcc.target/i386/pr119386-2.c index 3ea978e..d516aa9 100644 --- a/gcc/testsuite/gcc.target/i386/pr119386-2.c +++ b/gcc/testsuite/gcc.target/i386/pr119386-2.c @@ -1,7 +1,8 @@ /* PR target/119386 */ /* { dg-do compile { target *-*-linux* } } */ /* { dg-options "-O2 -fpic -fno-plt -pg" } */ -/* { dg-final { scan-assembler "call\[ \t\]+\\*mcount@GOTPCREL\\(" { target { ! ia32 } } } } */ +/* { dg-additional-options "-mfentry" { target { ! ia32 } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*__fentry__@GOTPCREL" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler "call\[ \t\]+\\*mcount@GOT\\(" { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1a.c b/gcc/testsuite/gcc.target/i386/pr120881-1a.c new file mode 100644 index 0000000..3d9ac0e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1a.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fno-pic" } */ +/* { dg-message "'-pg' without '-mfentry' may be unreliable with shrink wrapping" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1b.c b/gcc/testsuite/gcc.target/i386/pr120881-1b.c new file mode 100644 index 0000000..0826407 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1b.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target { fpic && { ! ia32 } } } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fpic" } */ +/* { dg-message "'-pg' without '-mfentry' may be unreliable with shrink wrapping" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1c.c b/gcc/testsuite/gcc.target/i386/pr120881-1c.c new file mode 100644 index 0000000..c21979f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1c.c @@ -0,0 +1,3 @@ +/* { dg-do compile { target { fpic && ia32 } } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fpic" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-1d.c b/gcc/testsuite/gcc.target/i386/pr120881-1d.c new file mode 100644 index 0000000..f74af23 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-1d.c @@ -0,0 +1,3 @@ +/* { dg-do compile { target { fpic && ia32 } } } */ +/* { dg-require-profiling "-pg" } */ +/* { dg-options "-O2 -pg -mno-fentry -fno-shrink-wrap -fno-pic" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120881-2a.c b/gcc/testsuite/gcc.target/i386/pr120881-2a.c new file mode 100644 index 0000000..52e3e52 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-2a.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target fentry } } */ +/* { dg-options "-O2 -pg" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**f2: +**.LFB[0-9]+: +** .cfi_startproc +** call __fentry__ +**... +*/ + +extern void f1 (void); + +void +f2 (int count) +{ + for (int i = 0; i < count; ++i) + f1 (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr120881-2b.c b/gcc/testsuite/gcc.target/i386/pr120881-2b.c new file mode 100644 index 0000000..43a12f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120881-2b.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue -march=x86-64" } */ +/* { dg-final { scan-rtl-dump "Now spread 1 times" "pro_and_epilogue" } } */ + +#include "pr120881-2a.c" + diff --git a/gcc/testsuite/gcc.target/i386/pr82699-1.c b/gcc/testsuite/gcc.target/i386/pr82699-1.c index 272d079..96e3ccb 100644 --- a/gcc/testsuite/gcc.target/i386/pr82699-1.c +++ b/gcc/testsuite/gcc.target/i386/pr82699-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fno-pic -fcf-protection -pg -fasynchronous-unwind-tables" } */ +/* { dg-options "-O2 -mfentry -fno-pic -fcf-protection -pg -fasynchronous-unwind-tables" } */ /* { dg-final { scan-assembler-times {\t\.cfi_startproc\n\tendbr} 1 } } */ extern int bar (int); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h index 9e4b4f4..93c29f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h @@ -531,6 +531,40 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ #define DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) \ DEF_VEC_SAT_U_SUB_FMT_10(T) +#define DEF_VEC_SAT_U_SUB_FMT_11(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_11 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = overflow ? 0 : ret; \ + } \ +} +#define DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_11(T) + +#define DEF_VEC_SAT_U_SUB_FMT_12(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_12 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = !overflow ? ret : 0; \ + } \ +} +#define DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_12(T) + #define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \ @@ -737,6 +771,16 @@ vec_sat_s_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_11(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_11(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_SUB_FMT_12(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_12(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12(T, out, op_1, op_2, N) + #define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N) #define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h index 4469f0e..7647439 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h @@ -744,7 +744,7 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] = }, }; -uint8_t TEST_UNARY_DATA(uint8_t, usub)[][3][N] = { +uint8_t TEST_UNARY_DATA(uint8_t, ussub)[][3][N] = { { { 0, 0, 0, 0, @@ -807,7 +807,7 @@ uint8_t TEST_UNARY_DATA(uint8_t, usub)[][3][N] = { }, }; -uint16_t TEST_UNARY_DATA(uint16_t, usub)[][3][N] = { +uint16_t TEST_UNARY_DATA(uint16_t, ussub)[][3][N] = { { { 0, 0, 0, 0, @@ -870,7 +870,7 @@ uint16_t TEST_UNARY_DATA(uint16_t, usub)[][3][N] = { }, }; -uint32_t TEST_UNARY_DATA(uint32_t, usub)[][3][N] = { +uint32_t TEST_UNARY_DATA(uint32_t, ussub)[][3][N] = { { { 0, 0, 4, 0, @@ -933,7 +933,7 @@ uint32_t TEST_UNARY_DATA(uint32_t, usub)[][3][N] = { }, }; -uint64_t TEST_UNARY_DATA(uint64_t, usub)[][3][N] = { +uint64_t TEST_UNARY_DATA(uint64_t, ussub)[][3][N] = { { { 0, 9, 0, 0, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c new file mode 100644 index 0000000..57da9e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c new file mode 100644 index 0000000..b5264a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c new file mode 100644 index 0000000..1a68b5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c new file mode 100644 index 0000000..a1c5c19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c new file mode 100644 index 0000000..fd987e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c new file mode 100644 index 0000000..bc380fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c new file mode 100644 index 0000000..c03163f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c new file mode 100644 index 0000000..91e1909 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c index 5fc747b..5878c5b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c index c9976d0..f74979f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c index 10a0b0c..1250e5b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c index 7b22863..a2a77dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c index a6b2dc4..19c8fa0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c index 91e749e..ada136f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c index b7a6314..488c158 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c index 1d55798..127c27a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c new file mode 100644 index 0000000..4b49467 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c new file mode 100644 index 0000000..80b55ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c new file mode 100644 index 0000000..6a89d0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c new file mode 100644 index 0000000..974493e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c new file mode 100644 index 0000000..28778b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c new file mode 100644 index 0000000..936a39a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c new file mode 100644 index 0000000..b8fa65b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c new file mode 100644 index 0000000..6bff1e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c index dcd6d17..45bef88 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c index 98a1fff..6d8a653 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c index 5445b01..0132d46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c index 3aaec4d..425f86f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c index 99e58cd..97a8e08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c index bd7bcd0..9124899 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c index 96ee0c8..1e54ede 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c index b9fa957..d8d53b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c index 6d4f377..b293823 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c index 1425017..f0f1c4f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c index 149d481..27c28e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c index 12195cd..7911825 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c index 9cd2577..6ae7b36 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c index 638e054..4e6b9e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c index db86baf..6b26913 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c index b277e1c..2bd28cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c index e79e2fc..69b0be9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c index cd9cbfc..2450586 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c index 7c0f753..0b97910 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c index d97a834..afb23f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c index 3b8c870..0466d4c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c index 065d898..14b8701 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c index f6783a8..7e0afd8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c index 6b9ae2d..40b1a6a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c index 27c4563..bd33048 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c index 2dba875..36f78f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c index 149a522..3bc5d5d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c index 739850e..3964d1b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c index 3eb91ef..4c0809a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c index 3e8d6fb..3e700bd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c index bb09035..81b8dc8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c index 1dc3191..8bc52ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c @@ -8,7 +8,7 @@ DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -#define test_data TEST_UNARY_DATA_WRAP(T, usub) +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) #define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c index 05cf57c..b17fd8e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c @@ -11,6 +11,8 @@ DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, +, acc) DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, +, sac) DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, -, nacc) DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, -, nsac) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -20,3 +22,5 @@ DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, -, nsac) /* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c index 873e315..efd887d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c @@ -11,6 +11,8 @@ DEF_VF_MULOP_ACC_CASE_0 (float, +, +, acc) DEF_VF_MULOP_ACC_CASE_0 (float, -, +, sac) DEF_VF_MULOP_ACC_CASE_0 (float, +, -, nacc) DEF_VF_MULOP_ACC_CASE_0 (float, -, -, nsac) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -20,3 +22,5 @@ DEF_VF_MULOP_ACC_CASE_0 (float, -, -, nsac) /* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c index 78127b6..84987a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c @@ -11,3 +11,7 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.s.h} 2 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c index 30d57e0..dbd3d02 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c @@ -11,3 +11,7 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.d.s} 2 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c index 8295ffb..5f0d758 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c @@ -11,6 +11,8 @@ DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, +, acc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, +, sac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, -, nacc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, -, nsac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -20,3 +22,5 @@ DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, -, nsac, VF_MULOP_ACC_BODY_X128) /* { dg-final { scan-assembler {vfmsac.vf} } } */ /* { dg-final { scan-assembler {vfnmacc.vf} } } */ /* { dg-final { scan-assembler {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c index f237f84..951b0ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c @@ -11,6 +11,8 @@ DEF_VF_MULOP_ACC_CASE_1 (float, +, +, acc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, -, +, sac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, +, -, nacc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, -, -, nsac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -20,3 +22,5 @@ DEF_VF_MULOP_ACC_CASE_1 (float, -, -, nsac, VF_MULOP_ACC_BODY_X128) /* { dg-final { scan-assembler {vfmsac.vf} } } */ /* { dg-final { scan-assembler {vfnmacc.vf} } } */ /* { dg-final { scan-assembler {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c index 7a50f67..a4edd92 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c @@ -11,3 +11,6 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {fcvt.s.h} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c index fb0493e..4eb28e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c @@ -11,3 +11,6 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {fcvt.d.s} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h index 1659f78..b1a324f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h @@ -34,6 +34,21 @@ #define RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, out, in, x, n) \ RUN_VF_MULOP_ACC_CASE_0 (T, NAME, out, in, x, n) +#define DEF_VF_MULOP_WIDEN_CASE_0(T1, T2, OP, NEG, NAME) \ + void test_vf_mulop_widen_##NAME##_##T1##_case_0 (T2 *restrict out, \ + T1 *restrict in, \ + T1 *restrict f, unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = NEG ((T2) * f * (T2) in[i] OP out[i]); \ + } +#define DEF_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, OP, NEG, NAME) \ + DEF_VF_MULOP_WIDEN_CASE_0 (T1, T2, OP, NEG, NAME) +#define RUN_VF_MULOP_WIDEN_CASE_0(T1, T2, NAME, out, in, x, n) \ + test_vf_mulop_widen_##NAME##_##T1##_case_0 (out, in, x, n) +#define RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, x, n) \ + RUN_VF_MULOP_WIDEN_CASE_0 (T1, T2, NAME, out, in, x, n) + #define VF_MULOP_BODY(op, neg) \ out[k + 0] = neg (tmp * out[k + 0] op in[k + 0]); \ out[k + 1] = neg (tmp * out[k + 1] op in[k + 1]); \ @@ -129,4 +144,19 @@ #define DEF_VF_MULOP_ACC_CASE_1_WRAP(T, OP, NEG, NAME, BODY) \ DEF_VF_MULOP_ACC_CASE_1 (T, OP, NEG, NAME, BODY) +#define DEF_VF_MULOP_WIDEN_CASE_1(TYPE1, TYPE2, OP, NEG, NAME) \ + void test_vf_mulop_widen_##NAME##_##TYPE1##_##TYPE2##_case_1 ( \ + TYPE2 *__restrict dst, TYPE2 *__restrict dst2, TYPE2 *__restrict dst3, \ + TYPE2 *__restrict dst4, TYPE1 *__restrict a, TYPE1 *__restrict b, \ + TYPE1 *__restrict a2, TYPE1 *__restrict b2, int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + dst[i] = NEG ((TYPE2) * a * (TYPE2) b[i] OP dst[i]); \ + dst2[i] = NEG ((TYPE2) * a2 * (TYPE2) b[i] OP dst2[i]); \ + dst3[i] = NEG ((TYPE2) * a2 * (TYPE2) a[i] OP dst3[i]); \ + dst4[i] = NEG ((TYPE2) * a * (TYPE2) b2[i] OP dst4[i]); \ + } \ + } + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h new file mode 100644 index 0000000..9f95fbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h @@ -0,0 +1,32 @@ +#ifndef HAVE_DEFINED_VF_MULOP_WIDEN_RUN_H +#define HAVE_DEFINED_VF_MULOP_WIDEN_RUN_H + +#include <assert.h> + +#define N 512 + +int main () +{ + T1 f[N]; + T1 in[N]; + T2 out[N]; + T2 out2[N]; + + for (int i = 0; i < N; i++) + { + f[i] = LIMIT + i % 8723; + in[i] = LIMIT + i & 1964; + out[i] = LIMIT + i & 628; + out2[i] = LIMIT + i & 628; + asm volatile ("" ::: "memory"); + } + + TEST_RUN (T1, T2, NAME, out, in, f, N); + + for (int i = 0; i < N; i++) + assert (out[i] == NEG(((T2) *f * (T2) in[i]) OP out2[i])); + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c new file mode 100644 index 0000000..d78cf73 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME acc +#define OP + +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c new file mode 100644 index 0000000..1af5240 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME acc +#define OP + +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c new file mode 100644 index 0000000..6422bba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME sac +#define OP - +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c new file mode 100644 index 0000000..13617a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME sac +#define OP - +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gnat.dg/deref4.adb b/gcc/testsuite/gnat.dg/deref4.adb new file mode 100644 index 0000000..586a6186 --- /dev/null +++ b/gcc/testsuite/gnat.dg/deref4.adb @@ -0,0 +1,9 @@ +-- { dg-do compile } +-- { dg-options "-gnatX" } + +with Deref4_Pkg; use Deref4_Pkg; + +procedure Deref4 is +begin + Obj.Proc (null); +end; diff --git a/gcc/testsuite/gnat.dg/deref4_pkg.ads b/gcc/testsuite/gnat.dg/deref4_pkg.ads new file mode 100644 index 0000000..9410d0d --- /dev/null +++ b/gcc/testsuite/gnat.dg/deref4_pkg.ads @@ -0,0 +1,8 @@ +package Deref4_Pkg is + + type A is tagged null record; + type A_Ptr is access A; + procedure Proc (This : in out A'Class; Some_Parameter : A_Ptr) is null; + Obj : A_Ptr; + +end Deref4_Pkg; diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 9ab46a0..c37a30a 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -14528,3 +14528,51 @@ proc check_effective_target_foldable_pi_based_trigonometry { } { } }] } +# +# Return 1 if the x86-64 target enables -mfentry by default, 0 +# otherwise. Cache the result. + +proc check_effective_target_fentry { } { + global tool + global GCC_UNDER_TEST + + if { ![check_effective_target_x86] } { + return 0 + } + + # Need auto-host.h to check linker support. + if { ![file exists ../../auto-host.h ] } { + return 0 + } + + return [check_cached_effective_target fentry { + # Set up and compile to see if ENABLE_X86_64_MFENTRY is + # non-zero. Include the current process ID in the file + # names to prevent conflicts with invocations for multiple + # testsuites. + + set src pie[pid].c + set obj pie[pid].o + + set f [open $src "w"] + puts $f "#include \"../../auto-host.h\"" + puts $f "#if ENABLE_X86_64_MFENTRY == 0 || !defined __x86_64__" + puts $f "# error -mfentry is not enabled by default." + puts $f "#endif" + close $f + + verbose "check_effective_target_fentry compiling testfile $src" 2 + set lines [${tool}_target_compile $src $obj object ""] + + file delete $src + file delete $obj + + if [string match "" $lines] then { + verbose "check_effective_target_fentry testfile compilation passed" 2 + return 1 + } else { + verbose "check_effective_target_fentry testfile compilation failed" 2 + return 0 + } + }] +} diff --git a/gcc/tree.cc b/gcc/tree.cc index 6a055c8..9d3d0ec 100644 --- a/gcc/tree.cc +++ b/gcc/tree.cc @@ -32,6 +32,7 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "backend.h" #include "target.h" +#include "tm_p.h" #include "tree.h" #include "gimple.h" #include "tree-pass.h" diff --git a/libgcobol/ChangeLog b/libgcobol/ChangeLog index 221b3009..91a3b86 100644 --- a/libgcobol/ChangeLog +++ b/libgcobol/ChangeLog @@ -1,3 +1,8 @@ +2025-07-13 Robert Dubner <rdubner@symas.com> + + * common-defs.h (PTRCAST): Moved here from libgcobol.h. + * libgcobol.h (PTRCAST): Deleted. + 2025-07-10 James K. Lowden <jklowden@cobolworx.com> * common-defs.h (cdf_enabled_exceptions): Use new CDF state. diff --git a/libstdc++-v3/include/bits/version.def b/libstdc++-v3/include/bits/version.def index df58e70..cf0672b 100644 --- a/libstdc++-v3/include/bits/version.def +++ b/libstdc++-v3/include/bits/version.def @@ -2053,7 +2053,7 @@ ftms = { ftms = { name = constexpr_exceptions; values = { - v = 202502; + v = 202411; cxxmin = 26; extra_cond = "__cpp_constexpr_exceptions >= 202411L"; }; diff --git a/libstdc++-v3/include/bits/version.h b/libstdc++-v3/include/bits/version.h index 1414dd7..c01ddf1 100644 --- a/libstdc++-v3/include/bits/version.h +++ b/libstdc++-v3/include/bits/version.h @@ -2301,9 +2301,9 @@ #if !defined(__cpp_lib_constexpr_exceptions) # if (__cplusplus > 202302L) && (__cpp_constexpr_exceptions >= 202411L) -# define __glibcxx_constexpr_exceptions 202502L +# define __glibcxx_constexpr_exceptions 202411L # if defined(__glibcxx_want_all) || defined(__glibcxx_want_constexpr_exceptions) -# define __cpp_lib_constexpr_exceptions 202502L +# define __cpp_lib_constexpr_exceptions 202411L # endif # endif #endif /* !defined(__cpp_lib_constexpr_exceptions) && defined(__glibcxx_want_constexpr_exceptions) */ diff --git a/libstdc++-v3/include/pstl/algorithm_impl.h b/libstdc++-v3/include/pstl/algorithm_impl.h index 5b1cd20..2080e82 100644 --- a/libstdc++-v3/include/pstl/algorithm_impl.h +++ b/libstdc++-v3/include/pstl/algorithm_impl.h @@ -79,7 +79,7 @@ template <class _ForwardIterator, class _Size, class _Function> _ForwardIterator __for_each_n_it_serial(_ForwardIterator __first, _Size __n, _Function __f) { - for (; __n > 0; ++__first, --__n) + for (; __n > 0; ++__first, (void) --__n) __f(__first); return __first; } @@ -221,7 +221,7 @@ _ForwardIterator2 __brick_walk2(_ForwardIterator1 __first1, _ForwardIterator1 __last1, _ForwardIterator2 __first2, _Function __f, /*vector=*/std::false_type) noexcept { - for (; __first1 != __last1; ++__first1, ++__first2) + for (; __first1 != __last1; ++__first1, (void) ++__first2) __f(*__first1, *__first2); return __first2; } @@ -240,7 +240,7 @@ _ForwardIterator2 __brick_walk2_n(_ForwardIterator1 __first1, _Size __n, _ForwardIterator2 __first2, _Function __f, /*vector=*/std::false_type) noexcept { - for (; __n > 0; --__n, ++__first1, ++__first2) + for (; __n > 0; --__n, (void) ++__first1, ++__first2) __f(*__first1, *__first2); return __first2; } @@ -364,7 +364,7 @@ _ForwardIterator3 __brick_walk3(_ForwardIterator1 __first1, _ForwardIterator1 __last1, _ForwardIterator2 __first2, _ForwardIterator3 __first3, _Function __f, /*vector=*/std::false_type) noexcept { - for (; __first1 != __last1; ++__first1, ++__first2, ++__first3) + for (; __first1 != __last1; ++__first1, (void) ++__first2, ++__first3) __f(*__first1, *__first2, *__first3); return __first3; } @@ -961,7 +961,7 @@ struct __brick_move_destroy { using _IteratorValueType = typename std::iterator_traits<_RandomAccessIterator1>::value_type; - for (; __first != __last; ++__first, ++__result) + for (; __first != __last; ++__first, (void) ++__result) { *__result = std::move(*__first); (*__first).~_IteratorValueType(); @@ -1027,7 +1027,7 @@ __brick_calc_mask_1(_ForwardIterator __first, _ForwardIterator __last, bool* __r static_assert(__are_random_access_iterators<_ForwardIterator>::value, "Pattern-brick error. Should be a random access iterator."); - for (; __first != __last; ++__first, ++__mask) + for (; __first != __last; ++__first, (void) ++__mask) { *__mask = __pred(*__first); if (*__mask) @@ -1052,7 +1052,7 @@ void __brick_copy_by_mask(_ForwardIterator __first, _ForwardIterator __last, _OutputIterator __result, bool* __mask, _Assigner __assigner, /*vector=*/std::false_type) noexcept { - for (; __first != __last; ++__first, ++__mask) + for (; __first != __last; ++__first, (void) ++__mask) { if (*__mask) { @@ -1079,7 +1079,7 @@ void __brick_partition_by_mask(_ForwardIterator __first, _ForwardIterator __last, _OutputIterator1 __out_true, _OutputIterator2 __out_false, bool* __mask, /*vector=*/std::false_type) noexcept { - for (; __first != __last; ++__first, ++__mask) + for (; __first != __last; ++__first, (void) ++__mask) { if (*__mask) { @@ -1383,7 +1383,7 @@ __brick_calc_mask_2(_RandomAccessIterator __first, _RandomAccessIterator __last, _BinaryPredicate __pred, /*vector=*/std::false_type) noexcept { _DifferenceType __count = 0; - for (; __first != __last; ++__first, ++__mask) + for (; __first != __last; ++__first, (void) ++__mask) { *__mask = !__pred(*__first, *(__first - 1)); __count += *__mask; @@ -1483,7 +1483,7 @@ void __brick_reverse(_BidirectionalIterator __first, _BidirectionalIterator __last, _BidirectionalIterator __d_last, /*is_vector=*/std::false_type) noexcept { - for (--__d_last; __first != __last; ++__first, --__d_last) + for (--__d_last; __first != __last; ++__first, (void) --__d_last) { using std::iter_swap; iter_swap(__first, __d_last); @@ -2333,7 +2333,7 @@ __pattern_partial_sort_copy(__parallel_tag<_IsVector> __tag, _ExecutionPolicy&& _RandomAccessIterator1 __it = __first + (__i - __r); // 1. Copy elements from input to raw memory - for (_T1* __k = __i; __k != __j; ++__k, ++__it) + for (_T1* __k = __i; __k != __j; ++__k, (void) ++__it) { ::new (__k) _T2(*__it); } @@ -3648,7 +3648,7 @@ __mismatch_serial(_ForwardIterator1 __first1, _ForwardIterator1 __last1, _Forwar #if defined(_PSTL_CPP14_2RANGE_MISMATCH_EQUAL_PRESENT) return std::mismatch(__first1, __last1, __first2, __last2, __pred); #else - for (; __first1 != __last1 && __first2 != __last2 && __pred(*__first1, *__first2); ++__first1, ++__first2) + for (; __first1 != __last1 && __first2 != __last2 && __pred(*__first1, *__first2); ++__first1, (void) ++__first2) { } return std::make_pair(__first1, __first2); diff --git a/libstdc++-v3/include/pstl/memory_impl.h b/libstdc++-v3/include/pstl/memory_impl.h index 8cb32d0..080b6ca 100644 --- a/libstdc++-v3/include/pstl/memory_impl.h +++ b/libstdc++-v3/include/pstl/memory_impl.h @@ -29,7 +29,7 @@ __brick_uninitialized_move(_ForwardIterator __first, _ForwardIterator __last, _O /*vector=*/std::false_type) noexcept { using _ValueType = typename std::iterator_traits<_OutputIterator>::value_type; - for (; __first != __last; ++__first, ++__result) + for (; __first != __last; ++__first, (void) ++__result) { ::new (std::addressof(*__result)) _ValueType(std::move(*__first)); } @@ -80,7 +80,7 @@ __brick_uninitialized_copy(_ForwardIterator __first, _ForwardIterator __last, _O /*vector=*/std::false_type) noexcept { using _ValueType = typename std::iterator_traits<_OutputIterator>::value_type; - for (; __first != __last; ++__first, ++__result) + for (; __first != __last; ++__first, (void) ++__result) { ::new (std::addressof(*__result)) _ValueType(*__first); } diff --git a/libstdc++-v3/include/pstl/numeric_impl.h b/libstdc++-v3/include/pstl/numeric_impl.h index b285a66..af6f6a2 100644 --- a/libstdc++-v3/include/pstl/numeric_impl.h +++ b/libstdc++-v3/include/pstl/numeric_impl.h @@ -158,7 +158,7 @@ __brick_transform_scan(_ForwardIterator __first, _ForwardIterator __last, _Outpu _UnaryOperation __unary_op, _Tp __init, _BinaryOperation __binary_op, /*Inclusive*/ std::false_type, /*is_vector=*/std::false_type) noexcept { - for (; __first != __last; ++__first, ++__result) + for (; __first != __last; ++__first, (void) ++__result) { _Tp __v = std::move(__init); _PSTL_PRAGMA_FORCEINLINE @@ -175,7 +175,7 @@ __brick_transform_scan(_RandomAccessIterator __first, _RandomAccessIterator __la _UnaryOperation __unary_op, _Tp __init, _BinaryOperation __binary_op, /*Inclusive*/ std::true_type, /*is_vector=*/std::false_type) noexcept { - for (; __first != __last; ++__first, ++__result) + for (; __first != __last; ++__first, (void) ++__result) { _PSTL_PRAGMA_FORCEINLINE __init = __binary_op(__init, __unary_op(*__first)); diff --git a/libstdc++-v3/libsupc++/exception b/libstdc++-v3/libsupc++/exception index 25ce8d9..fc6f8d9 100644 --- a/libstdc++-v3/libsupc++/exception +++ b/libstdc++-v3/libsupc++/exception @@ -38,6 +38,7 @@ #include <bits/exception.h> #define __glibcxx_want_uncaught_exceptions +#define __glibcxx_want_constexpr_exceptions #define __glibcxx_want_exception_ptr_cast #include <bits/version.h> diff --git a/libstdc++-v3/libsupc++/exception_ptr.h b/libstdc++-v3/libsupc++/exception_ptr.h index ee00915..f673a33 100644 --- a/libstdc++-v3/libsupc++/exception_ptr.h +++ b/libstdc++-v3/libsupc++/exception_ptr.h @@ -83,9 +83,9 @@ namespace std _GLIBCXX_VISIBILITY(default) #if __cpp_lib_exception_ptr_cast >= 202506L template<typename _Ex> - constexpr const _Ex* exception_ptr_cast(const exception_ptr&) noexcept; + constexpr const _Ex* exception_ptr_cast(const exception_ptr&) noexcept; template<typename _Ex> - void exception_ptr_cast(const exception_ptr&&) = delete; + void exception_ptr_cast(const exception_ptr&&) = delete; #endif namespace __exception_ptr @@ -138,8 +138,8 @@ namespace std _GLIBCXX_VISIBILITY(default) _GLIBCXX_USE_NOEXCEPT; #if __cpp_lib_exception_ptr_cast >= 202506L template<typename _Ex> - friend constexpr const _Ex* std::exception_ptr_cast(const exception_ptr&) - noexcept; + friend constexpr const _Ex* + std::exception_ptr_cast(const exception_ptr&) noexcept; #endif const void* _M_exception_ptr_cast(const type_info&) const @@ -296,40 +296,41 @@ namespace std _GLIBCXX_VISIBILITY(default) using __exception_ptr::swap; // So that std::swap(exp1, exp2) finds it. /// Obtain an exception_ptr pointing to a copy of the supplied object. -#if (__cplusplus >= 201103L && __cpp_rtti) || __cpp_exceptions template<typename _Ex> +#if !(__cplusplus >= 201103L && __cpp_rtti) && !__cpp_exceptions + // This is always_inline so the linker will never use a useless definition + // instead of a working one compiled with RTTI and/or exceptions enabled. + __attribute__ ((__always_inline__)) inline +#endif _GLIBCXX26_CONSTEXPR exception_ptr make_exception_ptr(_Ex __ex) _GLIBCXX_USE_NOEXCEPT { -#if __cplusplus >= 202400L - if consteval { - try - { - throw __ex; - } - catch(...) - { - return current_exception(); - } - } -#endif #if __cplusplus >= 201103L && __cpp_rtti - using _Ex2 = typename decay<_Ex>::type; - void* __e = __cxxabiv1::__cxa_allocate_exception(sizeof(_Ex)); - (void) __cxxabiv1::__cxa_init_primary_exception( - __e, const_cast<std::type_info*>(&typeid(_Ex)), - __exception_ptr::__dest_thunk<_Ex2>); - __try - { - ::new (__e) _Ex2(__ex); - return exception_ptr(__e); - } - __catch(...) + // For runtime calls with -frtti enabled we can avoid try-catch overhead. + // We can't use this for C++98 because it relies on std::decay. +#ifdef __glibcxx_constexpr_exceptions + if ! consteval +#endif { - __cxxabiv1::__cxa_free_exception(__e); - return current_exception(); + using _Ex2 = typename decay<_Ex>::type; + void* __e = __cxxabiv1::__cxa_allocate_exception(sizeof(_Ex)); + (void) __cxxabiv1::__cxa_init_primary_exception( + __e, const_cast<std::type_info*>(&typeid(_Ex)), + __exception_ptr::__dest_thunk<_Ex2>); + __try + { + ::new (__e) _Ex2(__ex); + return exception_ptr(__e); + } + __catch(...) + { + __cxxabiv1::__cxa_free_exception(__e); + return current_exception(); + } } -#else +#endif + +#ifdef __cpp_exceptions try { throw __ex; @@ -339,21 +340,14 @@ namespace std _GLIBCXX_VISIBILITY(default) return current_exception(); } #endif + return exception_ptr(); } -#else // no RTTI and no exceptions - // This is always_inline so the linker will never use this useless definition - // instead of a working one compiled with RTTI and/or exceptions enabled. - template<typename _Ex> - __attribute__ ((__always_inline__)) - _GLIBCXX26_CONSTEXPR inline exception_ptr - make_exception_ptr(_Ex) _GLIBCXX_USE_NOEXCEPT - { return exception_ptr(); } -#endif #if __cpp_lib_exception_ptr_cast >= 202506L template<typename _Ex> [[__gnu__::__always_inline__]] - constexpr const _Ex* exception_ptr_cast(const exception_ptr& __p) noexcept + constexpr const _Ex* + exception_ptr_cast(const exception_ptr& __p) noexcept { static_assert(!std::is_const_v<_Ex>); static_assert(!std::is_reference_v<_Ex>); @@ -361,28 +355,31 @@ namespace std _GLIBCXX_VISIBILITY(default) static_assert(!std::is_array_v<_Ex>); static_assert(!std::is_pointer_v<_Ex>); static_assert(!std::is_member_pointer_v<_Ex>); + #ifdef __cpp_rtti - if consteval { - if (__p._M_exception_object) - try - { - std::rethrow_exception(__p); - } - catch (const _Ex& __exc) - { - return &__exc; - } - catch (...) - { - } - return nullptr; - } else { + // For runtime calls with -frtti enabled we can avoid try-catch overhead. + if ! consteval { const type_info &__id = typeid(const _Ex&); return static_cast<const _Ex*>(__p._M_exception_ptr_cast(__id)); } -#else - return nullptr; #endif + +#ifdef __cpp_exceptions + if (__p._M_exception_object) + try + { + std::rethrow_exception(__p); + } + catch (const _Ex& __exc) + { + return &__exc; + } + catch (...) + { + } +#endif + + return nullptr; } #endif diff --git a/libstdc++-v3/testsuite/18_support/exception/version.cc b/libstdc++-v3/testsuite/18_support/exception/version.cc new file mode 100644 index 0000000..09a2d10 --- /dev/null +++ b/libstdc++-v3/testsuite/18_support/exception/version.cc @@ -0,0 +1,10 @@ +// { dg-do preprocess { target c++26 } } +// { dg-add-options no_pch } + +#include <exception> + +#ifndef __cpp_lib_constexpr_exceptions +# error "Feature test macro for constexpr_exceptions is missing in <exception>" +#elif __cpp_lib_constexpr_exceptions < 202411L +# error "Feature test macro for constexpr_exceptions has wrong value in <exception>" +#endif |