diff options
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 116 |
1 files changed, 83 insertions, 33 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9a1aa37..c1e708b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -433,7 +433,8 @@ Objective-C and Objective-C++ Dialects}. -Wunsuffixed-float-constants -Wunterminated-string-initialization -Wunused --Wunused-but-set-parameter -Wunused-but-set-variable +-Wunused-but-set-parameter -Wunused-but-set-parameter=@var{n} +-Wunused-but-set-variable -Wunused-but-set-variable=@var{n} -Wunused-const-variable -Wunused-const-variable=@var{n} -Wunused-function -Wunused-label -Wunused-local-typedefs -Wunused-macros @@ -914,7 +915,7 @@ Objective-C and Objective-C++ Dialects}. @emph{AVR Options} (@ref{AVR Options}) @gccoptlist{-mmcu=@var{mcu} -mabsdata -maccumulate-args -mcvt -mbranch-cost=@var{cost} -mfuse-add=@var{level} -mfuse-move=@var{level} --mcall-prologues -mgas-isr-prologues -mint8 -mflmap +-mfuse-move2 -mcall-prologues -mgas-isr-prologues -mint8 -mflmap -mdouble=@var{bits} -mlong-double=@var{bits} -mno-call-main -mn_flash=@var{size} -mfract-convert-truncate -mno-interrupts -mmain-is-OS_task -mrelax -mrmw -mstrict-X -mtiny-stack @@ -7921,27 +7922,89 @@ statement. @opindex Wunused-but-set-parameter @opindex Wno-unused-but-set-parameter @item -Wunused-but-set-parameter +@option{-Wunused-but-set-parameter} is the same as +@option{-Wunused-but-set-parameter=3} and +@option{-Wno-unused-but-set-parameter} is the same as +@option{-Wunused-but-set-parameter=0}. + +@opindex Wunused-but-set-parameter= +@item -Wunused-but-set-parameter=@var{n} Warn whenever a function parameter is assigned to, but otherwise unused (aside from its declaration). To suppress this warning use the @code{unused} attribute (@pxref{Variable Attributes}). -This warning is also enabled by @option{-Wunused} together with -@option{-Wextra}. +@option{-Wunused-but-set-parameter=0} disables the warning. +With @option{-Wunused-but-set-parameter=1} all uses except initialization +and left hand side of assignment which is not further used disable the +warning. +With @option{-Wunused-but-set-parameter=2} additionally uses of parameter +in @code{++} and @code{--} operators don't count as uses. +And finally with @option{-Wunused-but-set-parameter=3} additionally +uses in @var{parm} @code{@var{@@}=} @var{rhs} outside of @var{rhs} don't +count as uses. See @option{-Wunused-but-set-variable=@var{n}} option for +examples. + +This @option{-Wunused-but-set-parameter=3} warning is also enabled by +@option{-Wunused} together with @option{-Wextra}. @opindex Wunused-but-set-variable @opindex Wno-unused-but-set-variable @item -Wunused-but-set-variable +@option{-Wunused-but-set-variable} is the same as +@option{-Wunused-but-set-variable=3} and +@option{-Wno-unused-but-set-variable} is the same as +@option{-Wunused-but-set-variable=0}. + +@opindex Wunused-but-set-variable= +@item -Wunused-but-set-variable=@var{n} Warn whenever a local variable is assigned to, but otherwise unused (aside from its declaration). -This warning is enabled by @option{-Wall}. +This @option{-Wunused-but-set-variable=3} warning is enabled by @option{-Wall}. To suppress this warning use the @code{unused} attribute (@pxref{Variable Attributes}). -This warning is also enabled by @option{-Wunused}, which is enabled -by @option{-Wall}. +@option{-Wunused-but-set-variable=0} disables the warning. +With @option{-Wunused-but-set-variable=1} all uses except initialization +and left hand side of assignment which is not further used disable the +warning. +With @option{-Wunused-but-set-variable=2} additionally uses of variable +in @code{++} and @code{--} operators don't count as uses. +And finally with @option{-Wunused-but-set-variable=3} additionally +uses in @var{parm} @code{@var{@@}=} @var{rhs} outside of @var{rhs} don't +count as uses. + +This @option{-Wunused-but-set-variable=3} warning is also enabled by +@option{-Wunused}, which is enabled by @option{-Wall}. + +@smallexample +void foo (void) +@{ + int a = 1; // @option{-Wunused-variable} warning + int b = 0; // Warning for @var{n} >= 1 + b = 1; b = 2; + int c = 0; // Warning for @var{n} >= 2 + ++c; c--; --c; c++; + int d = 0; // Warning for @var{n} >= 3 + d += 4; + int e = 0; // No warning, cast to void + (void) e; + int f = 0; // No warning, f used + int g = f = 5; + (void) g; + int h = 0; // No warning, preincrement used + int i = ++h; + (void) i; + int j = 0; // No warning, postdecrement used + int k = j--; + (void) k; + int l = 0; // No warning, l used + int m = l |= 2; + (void) m; +@} +@end smallexample @opindex Wunused-function @opindex Wno-unused-function @@ -25047,6 +25110,10 @@ Valid values for @var{level} are in the range @code{0} @dots{} @code{23} which is a 3:2:2:2 mixed radix value. Each digit controls some aspect of the optimization. +@opindex mfuse-move2 +@item -mfuse-move2 +Run a post combine optimization pass that tries to fuse move instructions. + @opindex mstrict-X @item -mstrict-X Use address register @code{X} in a way proposed by the hardware. This means @@ -31307,31 +31374,14 @@ When the RISC-V specifications define an extension as depending on other extensions, GCC will implicitly add the dependent extensions to the enabled extension set if they weren't added explicitly. -@opindex mcpu -@item -mcpu=@var{processor-string} -Use architecture of and optimize the output for the given processor, specified -by particular CPU name. -Permissible values for this option are: @samp{mips-p8700}, @samp{sifive-e20}, -@samp{sifive-e21}, @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, -@samp{sifive-e76}, @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, -@samp{sifive-s76}, @samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, -@samp{sifive-xp450}, @samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8}, -@samp{xiangshan-nanhu}, @samp{xiangshan-kunminghu}, @samp{xt-c908}, @samp{xt-c908v}, -@samp{xt-c910}, @samp{xt-c910v2}, @samp{xt-c920}, @samp{xt-c920v2}. +@include riscv-mcpu.texi Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}. -@opindex mtune -@item -mtune=@var{processor-string} -Optimize the output for the given processor, specified by microarchitecture or -particular CPU name. Permissible values for this option are: -@samp{generic-ooo}, @samp{mips-p8700}, @samp{rocket}, @samp{sifive-3-series}, -@samp{sifive-5-series}, @samp{sifive-7-series}, @samp{size}, -@samp{sifive-p400-series}, @samp{sifive-p600-series}, and all valid options for -@option{-mcpu=}. +@include riscv-mtune.texi When @option{-mtune=} is not specified, use the setting from @option{-mcpu}, -the default is @samp{rocket} if both are not specified. +the default is @samp{generic} if both are not specified. The @samp{size} choice is not intended for use by end-users. This is used when @option{-Os} is specified. It overrides the instruction cost info @@ -34892,9 +34942,9 @@ Intel Panther Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, -VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR, AVXIFMA, -AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and -PREFETCHI instruction set support. +VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, UINTR, AVXIFMA, AVXVNNIINT8, +AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and PREFETCHI +instruction set support. @item sapphirerapids @itemx emeraldrapids @@ -34997,9 +35047,9 @@ Intel Clearwater Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, -LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -ENQCMD, UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, -SHA512, SM3, SM4, USER_MSR and PREFETCHI instruction set support. +LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, ENQCMD, +UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, +SM3, SM4, USER_MSR and PREFETCHI instruction set support. @item k6 AMD K6 CPU with MMX instruction set support. |