diff options
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/aarch64.h | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 826bd7d..4425dd4 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -304,6 +304,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_V9_4A, /* Armv9.5-A processors. */ AARCH64_FEATURE_V9_5A, + /* Armv9.6-A processors. */ + AARCH64_FEATURE_V9_6A, /* FPRCVT instructions. */ AARCH64_FEATURE_FPRCVT, /* Point of Physical Storage. */ @@ -473,6 +475,12 @@ static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL, | AARCH64_FEATBIT (X, SPMU2) \ | AARCH64_FEATBIT (X, STEP2) \ ) +#define AARCH64_ARCH_V9_6A_FEATURES(X) (AARCH64_FEATBIT (X, V9_6A) \ + | AARCH64_FEATBIT (X, CMPBR) \ + | AARCH64_FEATBIT (X, FPRCVT) \ + | AARCH64_FEATBIT (X, LSUI) \ + | AARCH64_FEATBIT (X, OCCMO) \ + | AARCH64_FEATBIT (X, SVE2p2)) /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \ @@ -512,6 +520,8 @@ static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL, | AARCH64_ARCH_V9_4A_FEATURES (X)) #define AARCH64_ARCH_V9_5A(X) (AARCH64_ARCH_V9_4A (X) \ | AARCH64_ARCH_V9_5A_FEATURES (X)) +#define AARCH64_ARCH_V9_6A(X) (AARCH64_ARCH_V9_5A (X) \ + | AARCH64_ARCH_V9_6A_FEATURES (X)) #define AARCH64_ARCH_NONE(X) 0 @@ -1541,7 +1551,24 @@ extern const aarch64_opcode aarch64_opcode_table[]; /* For LSFE instructions with size[30:31] field. */ #define F_LSFE_SZ (1ULL << 41) -/* Next bit is 42. */ + +/* When parsing immediate values, register names should not be misinterpreted + as symbols. However, for backwards compatibility we need to permit some + newer register names within older instructions. These flags specify which + register names are invalid immediate value, and are required for all + instructions with immediate operands (and are otherwise ignored). */ +#define F_INVALID_IMM_SYMS (3ULL << 42) + +/* Any GP or SIMD register except WSP/SP. */ +#define F_INVALID_IMM_SYMS_1 (1ULL << 42) + +/* As above, plus WSP/SP, and Z and P registers. */ +#define F_INVALID_IMM_SYMS_2 (2ULL << 42) + +/* As above, plus PN registers. */ +#define F_INVALID_IMM_SYMS_3 (3ULL << 42) + +/* Next bit is 44. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ |