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-rw-r--r--include/elf/aarch64.h2
-rw-r--r--include/elf/common.h1
-rw-r--r--include/opcode/aarch64.h29
-rw-r--r--include/sframe-api.h8
4 files changed, 31 insertions, 9 deletions
diff --git a/include/elf/aarch64.h b/include/elf/aarch64.h
index e218e07..74bd7b4 100644
--- a/include/elf/aarch64.h
+++ b/include/elf/aarch64.h
@@ -52,6 +52,8 @@
#define DT_AARCH64_BTI_PLT (DT_LOPROC + 1)
#define DT_AARCH64_PAC_PLT (DT_LOPROC + 3)
#define DT_AARCH64_VARIANT_PCS (DT_LOPROC + 5)
+#define DT_AARCH64_MEMTAG_MODE (DT_LOPROC + 9)
+#define DT_AARCH64_MEMTAG_STACK (DT_LOPROC + 12)
/* AArch64-specific values for st_other. */
#define STO_AARCH64_VARIANT_PCS 0x80 /* Symbol may follow different call
diff --git a/include/elf/common.h b/include/elf/common.h
index f395278..0d9a7b7 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -568,6 +568,7 @@
#define SHT_ANDROID_RELR 0x6fffff00
+#define SHT_GNU_SFRAME 0x6ffffff4 /* SFrame stack trace information. */
#define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes */
#define SHT_GNU_HASH 0x6ffffff6 /* GNU style symbol hash table */
#define SHT_GNU_LIBLIST 0x6ffffff7 /* List of prelink dependencies */
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 826bd7d..4425dd4 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -304,6 +304,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_V9_4A,
/* Armv9.5-A processors. */
AARCH64_FEATURE_V9_5A,
+ /* Armv9.6-A processors. */
+ AARCH64_FEATURE_V9_6A,
/* FPRCVT instructions. */
AARCH64_FEATURE_FPRCVT,
/* Point of Physical Storage. */
@@ -473,6 +475,12 @@ static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL,
| AARCH64_FEATBIT (X, SPMU2) \
| AARCH64_FEATBIT (X, STEP2) \
)
+#define AARCH64_ARCH_V9_6A_FEATURES(X) (AARCH64_FEATBIT (X, V9_6A) \
+ | AARCH64_FEATBIT (X, CMPBR) \
+ | AARCH64_FEATBIT (X, FPRCVT) \
+ | AARCH64_FEATBIT (X, LSUI) \
+ | AARCH64_FEATBIT (X, OCCMO) \
+ | AARCH64_FEATBIT (X, SVE2p2))
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \
@@ -512,6 +520,8 @@ static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL,
| AARCH64_ARCH_V9_4A_FEATURES (X))
#define AARCH64_ARCH_V9_5A(X) (AARCH64_ARCH_V9_4A (X) \
| AARCH64_ARCH_V9_5A_FEATURES (X))
+#define AARCH64_ARCH_V9_6A(X) (AARCH64_ARCH_V9_5A (X) \
+ | AARCH64_ARCH_V9_6A_FEATURES (X))
#define AARCH64_ARCH_NONE(X) 0
@@ -1541,7 +1551,24 @@ extern const aarch64_opcode aarch64_opcode_table[];
/* For LSFE instructions with size[30:31] field. */
#define F_LSFE_SZ (1ULL << 41)
-/* Next bit is 42. */
+
+/* When parsing immediate values, register names should not be misinterpreted
+ as symbols. However, for backwards compatibility we need to permit some
+ newer register names within older instructions. These flags specify which
+ register names are invalid immediate value, and are required for all
+ instructions with immediate operands (and are otherwise ignored). */
+#define F_INVALID_IMM_SYMS (3ULL << 42)
+
+/* Any GP or SIMD register except WSP/SP. */
+#define F_INVALID_IMM_SYMS_1 (1ULL << 42)
+
+/* As above, plus WSP/SP, and Z and P registers. */
+#define F_INVALID_IMM_SYMS_2 (2ULL << 42)
+
+/* As above, plus PN registers. */
+#define F_INVALID_IMM_SYMS_3 (3ULL << 42)
+
+/* Next bit is 44. */
/* Instruction constraints. */
/* This instruction has a predication constraint on the instruction at PC+4. */
diff --git a/include/sframe-api.h b/include/sframe-api.h
index ac4f19a..8c26257 100644
--- a/include/sframe-api.h
+++ b/include/sframe-api.h
@@ -153,14 +153,6 @@ sframe_decoder_get_fixed_fp_offset (sframe_decoder_ctx *dctx);
extern int8_t
sframe_decoder_get_fixed_ra_offset (sframe_decoder_ctx *dctx);
-/* Find the function descriptor entry which contains the specified address.
-
- Note: This function is deprecated and will be removed from future release
- X+2 of the library. */
-extern void *
-sframe_get_funcdesc_with_addr (sframe_decoder_ctx *dctx, int32_t addr,
- int *errp);
-
/* Find the SFrame Frame Row Entry which contains the PC. Returns
SFRAME_ERR if failure. */