diff options
121 files changed, 1266 insertions, 237 deletions
diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c index 0250a8f..dc0d2e0 100644 --- a/bfd/elf-eh-frame.c +++ b/bfd/elf-eh-frame.c @@ -802,6 +802,9 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info, switch (*aug++) { case 'B': + case 'G': + if (abfd->arch_info->arch != bfd_arch_aarch64) + goto unrecognized; break; case 'L': REQUIRE (read_byte (&buf, end, &cie->lsda_encoding)); @@ -843,6 +846,7 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info, REQUIRE (skip_bytes (&buf, end, per_width)); } break; + unrecognized: default: /* Unrecognized augmentation. Better bail out. */ goto free_no_table; diff --git a/bfd/elf-sframe.c b/bfd/elf-sframe.c index d74235b..b709e59 100644 --- a/bfd/elf-sframe.c +++ b/bfd/elf-sframe.c @@ -191,6 +191,18 @@ _bfd_elf_parse_sframe (bfd *abfd, bfd_size_type sf_size; int decerr = 0; + /* Prior versions of assembler and ld were generating SFrame sections with + section type SHT_PROGBITS. Issue an error for lack of support for such + objects now. Even if section size is zero, a valid section type is + expected. */ + if (elf_section_type (sec) != SHT_GNU_SFRAME) + { + _bfd_error_handler + (_("error in %pB(%pA); unexpected SFrame section type"), + abfd, sec); + return false; + } + if (sec->size == 0 || (sec->flags & SEC_HAS_CONTENTS) == 0 || sec->sec_info_type != SEC_INFO_TYPE_NONE) @@ -298,8 +310,7 @@ _bfd_elf_discard_section_sframe BFD ABFD. Returns true if no error. */ bool -_bfd_elf_set_section_sframe (bfd *abfd, - struct bfd_link_info *info) +_bfd_elf_set_section_sframe (bfd *abfd, struct bfd_link_info *info) { asection *cfsec; @@ -307,6 +318,7 @@ _bfd_elf_set_section_sframe (bfd *abfd, if (!cfsec) return false; + elf_section_type (cfsec) = SHT_GNU_SFRAME; elf_sframe (abfd) = cfsec; return true; @@ -2476,6 +2476,7 @@ bfd_section_from_shdr (bfd *abfd, unsigned int shindex) case SHT_PREINIT_ARRAY: /* .preinit_array section. */ case SHT_GNU_LIBLIST: /* .gnu.liblist section. */ case SHT_GNU_HASH: /* .gnu.hash section. */ + case SHT_GNU_SFRAME: /* .sframe section. */ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); goto success; diff --git a/bfd/elflink.c b/bfd/elflink.c index 666399b..c4f57cf 100644 --- a/bfd/elflink.c +++ b/bfd/elflink.c @@ -11293,7 +11293,7 @@ _bfd_elf_default_action_discarded (asection *sec) && strncmp (sec->name, ".eh_frame.", 10) == 0) return 0; - if (strcmp (".sframe", sec->name) == 0) + if (elf_section_type (sec) == SHT_GNU_SFRAME) return 0; if (strcmp (".gcc_except_table", sec->name) == 0) diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index 8f39920..9e98215d 100644 --- a/bfd/elfnn-aarch64.c +++ b/bfd/elfnn-aarch64.c @@ -2622,6 +2622,9 @@ struct elf_aarch64_link_hash_table /* Don't apply link-time values for dynamic relocations. */ int no_apply_dynamic_relocs; + /* Memtag Extension mode of operation. */ + aarch64_memtag_opts memtag_opts; + /* The number of bytes in the initial entry in the PLT. */ bfd_size_type plt_header_size; @@ -5009,13 +5012,15 @@ bfd_elfNN_aarch64_set_options (struct bfd *output_bfd, int fix_erratum_835769, erratum_84319_opts fix_erratum_843419, int no_apply_dynamic_relocs, - const aarch64_protection_opts *sw_protections) + const aarch64_protection_opts *sw_protections, + const aarch64_memtag_opts *memtag_opts) { struct elf_aarch64_link_hash_table *globals; globals = elf_aarch64_hash_table (link_info); globals->pic_veneer = pic_veneer; globals->fix_erratum_835769 = fix_erratum_835769; + globals->memtag_opts = *memtag_opts; /* If the default options are used, then ERRAT_ADR will be set by default which will enable the ADRP->ADR workaround for the erratum 843419 workaround. */ @@ -9775,7 +9780,20 @@ elfNN_aarch64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED, && !add_dynamic_entry (DT_AARCH64_PAC_PLT, 0)) return false; } + + if (is_aarch64_elf (output_bfd) + && htab->memtag_opts.memtag_mode != AARCH64_MEMTAG_MODE_NONE + && !add_dynamic_entry (DT_AARCH64_MEMTAG_MODE, + htab->memtag_opts.memtag_mode == AARCH64_MEMTAG_MODE_ASYNC)) + return false; + + if (is_aarch64_elf (output_bfd) + && htab->memtag_opts.memtag_stack == 1 + && !add_dynamic_entry (DT_AARCH64_MEMTAG_STACK, + htab->memtag_opts.memtag_stack == 1)) + return false; } + #undef add_dynamic_entry return true; diff --git a/bfd/elfxx-aarch64.h b/bfd/elfxx-aarch64.h index 506f4a9..bd3642c 100644 --- a/bfd/elfxx-aarch64.h +++ b/bfd/elfxx-aarch64.h @@ -129,13 +129,38 @@ typedef enum ERRAT_ADRP = (1 << 2), /* Erratum workarounds using ADRP are allowed. */ } erratum_84319_opts; +/* An enum to define the various modes of MTE operation. + At this time, except AARCH64_MEMTAG_MODE_NONE, the enumerator constants are + the same as specified in the Memtag ABI Extension to ELF for the Arm 64-bit + Architecture (AArch64) document (the intent being that this keeps the + emission of the associated dynamic tag simple).*/ +typedef enum +{ + AARCH64_MEMTAG_MODE_SYNC = 0, + AARCH64_MEMTAG_MODE_ASYNC = 1, + AARCH64_MEMTAG_MODE_NONE = 2, +} aarch64_memtag_mode_type; + +/* A structure to encompass all information about memtag feature related + command line options. */ +struct aarch64_memtag_opts +{ + /* Mode of MTE operation. */ + aarch64_memtag_mode_type memtag_mode; + + /* Whether stack accesses use MTE insns. */ + unsigned int memtag_stack; +}; + +typedef struct aarch64_memtag_opts aarch64_memtag_opts; + extern void bfd_elf64_aarch64_set_options (bfd *, struct bfd_link_info *, int, int, int, int, erratum_84319_opts, int, - const aarch64_protection_opts *); + const aarch64_protection_opts *, const aarch64_memtag_opts *); extern void bfd_elf32_aarch64_set_options (bfd *, struct bfd_link_info *, int, int, int, int, erratum_84319_opts, int, - const aarch64_protection_opts *); + const aarch64_protection_opts *, const aarch64_memtag_opts *); /* AArch64 stub generation support for ELF64. Called from the linker. */ extern int elf64_aarch64_setup_section_lists diff --git a/bfd/elfxx-x86.c b/bfd/elfxx-x86.c index 663f40a..3dc0095 100644 --- a/bfd/elfxx-x86.c +++ b/bfd/elfxx-x86.c @@ -4785,11 +4785,10 @@ _bfd_x86_elf_link_setup_gnu_properties | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED); - sec = bfd_make_section_anyway_with_flags (dynobj, - ".sframe", - flags); + sec = bfd_make_section_anyway_with_flags (dynobj, ".sframe", flags); if (sec == NULL) info->callbacks->fatal (_("%P: failed to create PLT .sframe section\n")); + elf_section_type (sec) = SHT_GNU_SFRAME; // FIXME check this // if (!bfd_set_section_alignment (sec, class_align)) @@ -4805,6 +4804,7 @@ _bfd_x86_elf_link_setup_gnu_properties flags); if (sec == NULL) info->callbacks->fatal (_("%P: failed to create second PLT .sframe section\n")); + elf_section_type (sec) = SHT_GNU_SFRAME; htab->plt_second_sframe = sec; } @@ -4817,6 +4817,7 @@ _bfd_x86_elf_link_setup_gnu_properties flags); if (sec == NULL) info->callbacks->fatal (_("%P: failed to create PLT GOT .sframe section\n")); + elf_section_type (sec) = SHT_GNU_SFRAME; htab->plt_got_sframe = sec; } diff --git a/binutils/NEWS b/binutils/NEWS index 0635687..89351d7 100644 --- a/binutils/NEWS +++ b/binutils/NEWS @@ -1,5 +1,17 @@ -*- text -*- +* New versioned release of libsframe: libsframe.so.2. This release introduces + versioned symbols with version node name LIBSFRAME_2.0. Some new symbols + have been added to support the new flag SFRAME_F_FDE_FUNC_START_PCREL and + retrieving flags from SFrame decoder and encoder objects: + - Addition of sframe_decoder_get_flags, + sframe_decoder_get_offsetof_fde_start_addr, sframe_encoder_get_flags, + sframe_encoder_get_offsetof_fde_start_addr. + This release also includes backward-incompatible ABI changes: + - Removal of sframe_get_funcdesc_with_addr. + - Change in the behavior of sframe_decoder_get_funcdesc_v2, + sframe_encoder_add_funcdesc_v2 and sframe_encoder_write. + * On s390 64-bit (s390x), gas, ld, objdump, and readelf now support generating and processing SFrame V2 stack trace information (.sframe). The assembler generates SFrame info from CFI directives with option "--gsframe". The @@ -24,6 +36,10 @@ * For RISC-V dis-assembler, the definition of mapping symbol $x is changed, so the file needs to be rebuilt since 2.45 once used .option arch directives. +* The LoongArch disassembler now properly accepts multiple disassembly + options given by -M, such as "-M no-aliases,numeric". (Previously only the + first option took effect.) + Changes in 2.44: * Support for Nios II targets has been removed except in the readelf utility, diff --git a/binutils/dwarf.c b/binutils/dwarf.c index e0e202f..f4bcb67 100644 --- a/binutils/dwarf.c +++ b/binutils/dwarf.c @@ -8582,6 +8582,8 @@ typedef struct Frame_Chunk } Frame_Chunk; +typedef bool (*is_mach_augmentation_ftype) (char c); +static is_mach_augmentation_ftype is_mach_augmentation; typedef const char *(*dwarf_regname_lookup_ftype) (unsigned int); static dwarf_regname_lookup_ftype dwarf_regnames_lookup_func; static const char *const *dwarf_regnames; @@ -8894,9 +8896,22 @@ init_dwarf_regnames_loongarch (void) dwarf_regnames_lookup_func = regname_internal_by_table_only; } +static bool +is_nomach_augmentation (char c ATTRIBUTE_UNUSED) +{ + return false; +} + +static bool +is_aarch64_augmentation (char c) +{ + return (c == 'B' || c == 'G'); +} + void -init_dwarf_regnames_by_elf_machine_code (unsigned int e_machine) +init_dwarf_by_elf_machine_code (unsigned int e_machine) { + is_mach_augmentation = is_nomach_augmentation; dwarf_regnames_lookup_func = NULL; is_aarch64 = false; @@ -8918,6 +8933,7 @@ init_dwarf_regnames_by_elf_machine_code (unsigned int e_machine) case EM_AARCH64: init_dwarf_regnames_aarch64 (); + is_mach_augmentation = is_aarch64_augmentation; break; case EM_S390: @@ -8941,9 +8957,10 @@ init_dwarf_regnames_by_elf_machine_code (unsigned int e_machine) architecture and specific machine type of a BFD. */ void -init_dwarf_regnames_by_bfd_arch_and_mach (enum bfd_architecture arch, - unsigned long mach) +init_dwarf_by_bfd_arch_and_mach (enum bfd_architecture arch, + unsigned long mach) { + is_mach_augmentation = is_nomach_augmentation; dwarf_regnames_lookup_func = NULL; is_aarch64 = false; @@ -8971,6 +8988,7 @@ init_dwarf_regnames_by_bfd_arch_and_mach (enum bfd_architecture arch, case bfd_arch_aarch64: init_dwarf_regnames_aarch64(); + is_mach_augmentation = is_aarch64_augmentation; break; case bfd_arch_s390: @@ -9216,7 +9234,7 @@ read_cie (unsigned char *start, unsigned char *end, fc->fde_encoding = *q++; else if (*p == 'S') ; - else if (*p == 'B') + else if (is_mach_augmentation (*p)) ; else break; diff --git a/binutils/dwarf.h b/binutils/dwarf.h index 6f693b1..13afb4a 100644 --- a/binutils/dwarf.h +++ b/binutils/dwarf.h @@ -241,9 +241,9 @@ extern unsigned long dwarf_start_die; extern int dwarf_check; -extern void init_dwarf_regnames_by_elf_machine_code (unsigned int); -extern void init_dwarf_regnames_by_bfd_arch_and_mach (enum bfd_architecture arch, - unsigned long mach); +extern void init_dwarf_by_elf_machine_code (unsigned int); +extern void init_dwarf_by_bfd_arch_and_mach (enum bfd_architecture arch, + unsigned long mach); extern bool load_debug_section (enum dwarf_section_display_enum, void *); extern void free_debug_section (enum dwarf_section_display_enum); diff --git a/binutils/objdump.c b/binutils/objdump.c index 7bb6d76..98d3049 100644 --- a/binutils/objdump.c +++ b/binutils/objdump.c @@ -4551,8 +4551,8 @@ dump_dwarf (bfd *abfd, bool is_mainfile) break; } - init_dwarf_regnames_by_bfd_arch_and_mach (bfd_get_arch (abfd), - bfd_get_mach (abfd)); + init_dwarf_by_bfd_arch_and_mach (bfd_get_arch (abfd), + bfd_get_mach (abfd)); bfd_map_over_sections (abfd, dump_dwarf_section, (void *) &is_mainfile); } diff --git a/binutils/readelf.c b/binutils/readelf.c index 5730247..cfccdd2 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -2584,9 +2584,12 @@ get_aarch64_dynamic_type (unsigned long type) { switch (type) { - case DT_AARCH64_BTI_PLT: return "AARCH64_BTI_PLT"; - case DT_AARCH64_PAC_PLT: return "AARCH64_PAC_PLT"; + case DT_AARCH64_BTI_PLT: return "AARCH64_BTI_PLT"; + case DT_AARCH64_PAC_PLT: return "AARCH64_PAC_PLT"; case DT_AARCH64_VARIANT_PCS: return "AARCH64_VARIANT_PCS"; + case DT_AARCH64_MEMTAG_MODE: return "AARCH64_MEMTAG_MODE"; + case DT_AARCH64_MEMTAG_STACK: return "AARCH64_MEMTAG_STACK"; + default: return NULL; } @@ -5964,6 +5967,7 @@ get_os_specific_section_type_name (Filedata * filedata, unsigned int sh_type) case SHT_GNU_HASH: return "GNU_HASH"; case SHT_GNU_LIBLIST: return "GNU_LIBLIST"; case SHT_GNU_OBJECT_ONLY: return "GNU_OBJECT_ONLY"; + case SHT_GNU_SFRAME: return "GNU_SFRAME"; case SHT_SUNW_move: return "SUNW_MOVE"; case SHT_SUNW_COMDAT: return "SUNW_COMDAT"; @@ -6827,7 +6831,7 @@ process_file_header (Filedata * filedata) return false; if (! filedata->is_separate) - init_dwarf_regnames_by_elf_machine_code (header->e_machine); + init_dwarf_by_elf_machine_code (header->e_machine); if (do_header) { @@ -8367,6 +8371,7 @@ process_section_headers (Filedata * filedata) case SHT_NOTE: case SHT_PROGBITS: + case SHT_GNU_SFRAME: /* Having a zero sized section is not illegal according to the ELF standard, but it might be an indication that something is wrong. So issue a warning if we are running in lint mode. */ @@ -8,6 +8,8 @@ with the applicable encoding. Setting the flag ensures compliance with the updated SFrame V2 specification. + ELF SFrame sections now have section type set to SHT_GNU_SFRAME. + * Add .errif and .warnif directives, permitting user-controlled diagnostics with conditionals that are evaluated only at the end of assembly. @@ -39,6 +41,15 @@ * Add support for the x86 Zhaoxin PadLock XMODX instructions. +* Add support for several instruction aliases defined for the LoongArch 32-bit + reduced subset (LA32R): rdcntvl.w, rdcntvh.w, rdcntid.w. + +* For LoongArch, warn about out-of-range 3rd arguments (maximum number of + bytes to skip) of .align directives. + +* For LoongArch, warn about negative right-shift amounts and + division/modulus-by-zero when evaluating expressions. + Changes in 2.44: * Add support for the x86 Intel Diamond Rapids AMX instructions, including diff --git a/gas/config/obj-elf.c b/gas/config/obj-elf.c index 03b6c24..315d08e 100644 --- a/gas/config/obj-elf.c +++ b/gas/config/obj-elf.c @@ -1163,6 +1163,15 @@ obj_elf_attach_to_group (int dummy ATTRIBUTE_UNUSED) elf_set_group_name (now_seg, gname); } +/* Handle section related directives. + + Note on support for SFrame sections: These are generally expected to be + generated by the assembler. However, this function permits their direct + creation by the user. At the moment though, we go no extra mile by adding + an explicit @sframe for SHT_GNU_SFRAME (using the numeric value of section + type should suffice); Nor do we implement any outright refusal for + non-supported targets via ELFOSABI-specific checks. */ + void obj_elf_section (int push) { diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 29d9cdb..cd9ae58 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -2351,6 +2351,14 @@ s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED) fde->pauth_key = AARCH64_PAUTH_KEY_B; } +static void +s_aarch64_mte_tagged_frame (int ignored ATTRIBUTE_UNUSED) +{ + demand_empty_rest_of_line (); + struct fde_entry *fde = frchain_now->frch_cfi_data->cur_fde_data; + fde->memtag_frame_p = true; +} + #ifdef OBJ_ELF /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */ @@ -2476,6 +2484,7 @@ const pseudo_typeS md_pseudo_table[] = { {"arch_extension", s_aarch64_arch_extension, 0}, {"inst", s_aarch64_inst, 0}, {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame, 0}, + {"cfi_mte_tagged_frame", s_aarch64_mte_tagged_frame, 0}, #ifdef OBJ_ELF {"tlsdescadd", s_tlsdescadd, 0}, {"tlsdesccall", s_tlsdesccall, 0}, @@ -4956,6 +4965,10 @@ parse_sme_sm_za (char **str) return TOLOWER (p[0]); } +/* By default, system register accesses are unguarded (apart from the + requirement of +d128 for mrrs/msrr). */ +static int sysreg_checking_p = 0; + /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. Returns the encoding for the option, or PARSE_FAIL. @@ -5010,10 +5023,11 @@ parse_sys_reg (char **str, htab_t sys_regs, } else { - if (pstatefield_p && !aarch64_pstatefield_supported_p (cpu_variant, o)) + if (pstatefield_p && sysreg_checking_p + && !aarch64_pstatefield_supported_p (cpu_variant, o)) as_bad (_("selected processor does not support PSTATE field " "name '%s'"), buf); - if (!pstatefield_p + if (!pstatefield_p && sysreg_checking_p && !aarch64_sys_ins_reg_supported_p (cpu_variant, o->name, o->flags, &o->features)) as_bad (_("selected processor does not support system register " @@ -5094,12 +5108,14 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs, bool sysreg128_p) } while (0) #define po_imm_nc_or_fail() do { \ - if (! parse_constant_immediate (&str, &val, imm_reg_type)) \ + aarch64_reg_type invalid_types = imm_invalid_reg_types (opcode->flags); \ + if (! parse_constant_immediate (&str, &val, invalid_types)) \ goto failure; \ } while (0) #define po_imm_or_fail(min, max) do { \ - if (! parse_constant_immediate (&str, &val, imm_reg_type)) \ + aarch64_reg_type invalid_types = imm_invalid_reg_types (opcode->flags); \ + if (! parse_constant_immediate (&str, &val, invalid_types)) \ goto failure; \ if (val < min || val > max) \ { \ @@ -5110,8 +5126,9 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs, bool sysreg128_p) } while (0) #define po_enum_or_fail(array) do { \ + aarch64_reg_type invalid_types = imm_invalid_reg_types (opcode->flags); \ if (!parse_enum_string (&str, &val, array, \ - ARRAY_SIZE (array), imm_reg_type)) \ + ARRAY_SIZE (array), invalid_types)) \ goto failure; \ } while (0) @@ -6657,6 +6674,28 @@ reg_list_valid_p (uint32_t reginfo, struct aarch64_reglist *list, return true; } +static aarch64_reg_type +imm_invalid_reg_types (uint64_t flags) +{ + switch (flags & F_INVALID_IMM_SYMS) + { + case F_INVALID_IMM_SYMS_1: + return REG_TYPE_R_ZR_BHSDQ_V; + + case F_INVALID_IMM_SYMS_2: + return REG_TYPE_R_ZR_SP_BHSDQ_VZP; + + case F_INVALID_IMM_SYMS_3: + return REG_TYPE_R_ZR_SP_BHSDQ_VZP_PN; + + default: + /* All instructions with immediate operands require an explicit flag - + this ensures that the flags will not be forgotten when adding new + instructions. */ + gas_assert (0); + } +} + /* Generic instruction operand parser. This does no encoding and no semantic validation; it merely squirrels values away in the inst structure. Returns TRUE or FALSE depending on whether the @@ -6669,19 +6708,10 @@ parse_operands (char *str, const aarch64_opcode *opcode) char *backtrack_pos = 0; const enum aarch64_opnd *operands = opcode->operands; const uint64_t flags = opcode->flags; - aarch64_reg_type imm_reg_type; clear_error (); skip_whitespace (str); - if (AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SME2)) - imm_reg_type = REG_TYPE_R_ZR_SP_BHSDQ_VZP_PN; - else if (AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE) - || AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2)) - imm_reg_type = REG_TYPE_R_ZR_SP_BHSDQ_VZP; - else - imm_reg_type = REG_TYPE_R_ZR_BHSDQ_V; - for (i = 0; operands[i] != AARCH64_OPND_NIL; i++) { int64_t val; @@ -7237,13 +7267,15 @@ parse_operands (char *str, const aarch64_opcode *opcode) { int qfloat; bool res1 = false, res2 = false; + aarch64_reg_type invalid_types + = imm_invalid_reg_types (opcode->flags); /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected, it is probably not worth the effort to support it. */ if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, false, - imm_reg_type)) + invalid_types)) && (error_p () || !(res2 = parse_constant_immediate (&str, &val, - imm_reg_type)))) + invalid_types)))) goto failure; if ((res1 && qfloat == 0) || (res2 && val == 0)) { @@ -7277,7 +7309,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SIMD_IMM: case AARCH64_OPND_SIMD_IMM_SFT: - if (! parse_big_immediate (&str, &val, imm_reg_type)) + if (! parse_big_immediate (&str, &val, + imm_invalid_reg_types (opcode->flags))) goto failure; assign_imm_if_const_or_fixup_later (&inst.reloc, info, /* addr_off_p */ 0, @@ -7305,11 +7338,13 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SIMD_FPIMM: case AARCH64_OPND_SVE_FPIMM8: { + aarch64_reg_type invalid_types + = imm_invalid_reg_types (opcode->flags); int qfloat; bool dp_p; dp_p = double_precision_operand_p (&inst.base.operands[0]); - if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type) + if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, invalid_types) || !aarch64_imm_float_p (qfloat)) { if (!error_p ()) @@ -7326,11 +7361,13 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_I1_HALF_TWO: case AARCH64_OPND_SVE_I1_ZERO_ONE: { + aarch64_reg_type invalid_types + = imm_invalid_reg_types (opcode->flags); int qfloat; bool dp_p; dp_p = double_precision_operand_p (&inst.base.operands[0]); - if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type)) + if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, invalid_types)) { if (!error_p ()) set_fatal_syntax_error (_("invalid floating-point" @@ -7419,13 +7456,17 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_EXCEPTION: case AARCH64_OPND_UNDEFINED: - po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp, - imm_reg_type)); - assign_imm_if_const_or_fixup_later (&inst.reloc, info, - /* addr_off_p */ 0, - /* need_libopcodes_p */ 0, - /* skip_p */ 1); - break; + { + aarch64_reg_type invalid_types + = imm_invalid_reg_types (opcode->flags); + po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp, + invalid_types)); + assign_imm_if_const_or_fixup_later (&inst.reloc, info, + /* addr_off_p */ 0, + /* need_libopcodes_p */ 0, + /* skip_p */ 1); + break; + } case AARCH64_OPND_NZCV: { @@ -8094,7 +8135,9 @@ parse_operands (char *str, const aarch64_opcode *opcode) { /* DSB nXS barrier variant accept 5-bit unsigned immediate, with possible values 16, 20, 24 or 28 , encoded as val<3:2>. */ - if (! parse_constant_immediate (&str, &val, imm_reg_type)) + aarch64_reg_type invalid_types + = imm_invalid_reg_types (opcode->flags); + if (! parse_constant_immediate (&str, &val, invalid_types)) goto failure; if (!(val == 16 || val == 20 || val == 24 || val == 28)) { @@ -10574,6 +10617,9 @@ static struct aarch64_option_table aarch64_opts[] = { NULL}, {"mno-verbose-error", N_("do not output verbose error messages"), &verbose_error_p, 0, NULL}, + {"menable-sysreg-checking", + N_("enable feature flag gating for system registers"), + &sysreg_checking_p, 1, NULL}, {NULL, NULL, NULL, 0, NULL} }; @@ -10696,6 +10742,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = { {"armv9.3-a", AARCH64_ARCH_FEATURES (V9_3A)}, {"armv9.4-a", AARCH64_ARCH_FEATURES (V9_4A)}, {"armv9.5-a", AARCH64_ARCH_FEATURES (V9_5A)}, + {"armv9.6-a", AARCH64_ARCH_FEATURES (V9_6A)}, {NULL, AARCH64_NO_FEATURES} }; diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h index 0d8066c..fce34ed 100644 --- a/gas/config/tc-aarch64.h +++ b/gas/config/tc-aarch64.h @@ -90,13 +90,21 @@ enum pointer_auth_key { /* The extra fields required by AArch64 in fde_entry and cie_entry. Currently only used to store the key used to sign the frame's return address. */ -#define tc_fde_entry_extras enum pointer_auth_key pauth_key; -#define tc_cie_entry_extras enum pointer_auth_key pauth_key; +#define tc_fde_entry_extras enum pointer_auth_key pauth_key; \ + bool memtag_frame_p; +#define tc_cie_entry_extras enum pointer_auth_key pauth_key; \ + bool memtag_frame_p; /* The extra initialisation steps needed by AArch64 in alloc_fde_entry. Currently only used to initialise the key used to sign the return address. */ -#define tc_fde_entry_init_extra(fde) fde->pauth_key = AARCH64_PAUTH_KEY_A; +#define tc_fde_entry_init_extra(fde) \ + do \ + { \ + fde->pauth_key = AARCH64_PAUTH_KEY_A; \ + fde->memtag_frame_p = false; \ + } \ + while (0) /* Extra checks required by AArch64 when outputting the current cie_entry. Currently only used to output a 'B' if the return address is signed with the @@ -106,18 +114,29 @@ enum pointer_auth_key { { \ if (cie->pauth_key == AARCH64_PAUTH_KEY_B) \ out_one ('B'); \ + if (cie->memtag_frame_p) \ + out_one ('G'); \ } \ while (0) /* Extra equivalence checks required by AArch64 when selecting the correct cie - for some fde. Currently only used to check for quivalence between keys used - to sign ther return address. */ -#define tc_cie_fde_equivalent_extra(cie, fde) (cie->pauth_key == fde->pauth_key) + for some fde. Currently used to check for equivalence between - keys used + to sign the return address, and if stack locations have MTE tagging + enabled. */ +#define tc_cie_fde_equivalent_extra(cie, fde) \ + ((cie->pauth_key == fde->pauth_key) \ + && (cie->memtag_frame_p == fde->memtag_frame_p)) /* The extra initialisation steps needed by AArch64 in select_cie_for_fde. Currently only used to initialise the key used to sign the return address. */ -#define tc_cie_entry_init_extra(cie, fde) cie->pauth_key = fde->pauth_key; +#define tc_cie_entry_init_extra(cie, fde) \ + do \ + { \ + cie->pauth_key = fde->pauth_key; \ + cie->memtag_frame_p = fde->memtag_frame_p; \ + } \ + while (0) #define TC_FIX_TYPE struct aarch64_fix #define TC_INIT_FIX_DATA(FIX) { (FIX)->tc_fix_data.inst = NULL; \ diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index d300ab2..dc64e09 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -136,6 +136,12 @@ is enabled by default. @item -mno-verbose-error This option disables verbose error messages in AArch64 gas. +@cindex @code{-menable-sysreg-checking} command-line option, AArch64 +@item -menable-sysreg-checking +This option enables error messages that are issued if an attempt is made to +assemble a system register access which will not execute on the target +architecture. + @end table @c man end @@ -369,6 +375,7 @@ automatically cause those extensions to be disabled. @item @code{armv9.3-a} @tab @code{armv9.2-a}, @code{armv8.8-a} @item @code{armv9.4-a} @tab @code{armv9.3-a}, @code{armv8.9-a} @item @code{armv9.5-a} @tab @code{armv9.4-a}, @code{cpa}, @code{lut}, @code{faminmax} +@item @code{armv9.6-a} @tab @code{armv9.5-a}, @code{cmpbr}, @code{fprcvt}, @code{lsui}, @code{occmo}, @code{sve2p2} @item @code{armv8-r} @tab @code{armv8.4-a+nolor} @end multitable @@ -492,6 +499,14 @@ incrementally to the architecture being compiled for. @c BBBBBBBBBBBBBBBBBBBBBBBBBB @c CCCCCCCCCCCCCCCCCCCCCCCCCC +@cindex @code{.cfi_mte_tagged_frame} directive, AArch64 +@item @code{.cfi_mte_tagged_frame} +The @code{.cfi_mte_tagged_frame} directive inserts a 'G' character into the +CIE corresponding to the current frame's FDE, meaning that the associated +frames may modify MTE tags on the stack space they use. This information is +intended to be used by the stack unwinder in order to properly untag stack +frames. + @cindex @code{.cpu} directive, AArch64 @item .cpu @var{name} Set the target processor. Valid values for @var{name} are the same as diff --git a/gas/dw2gencfi.c b/gas/dw2gencfi.c index 5eb8a5d..57fffab 100644 --- a/gas/dw2gencfi.c +++ b/gas/dw2gencfi.c @@ -91,11 +91,6 @@ #define tc_cfi_reloc_for_encoding(e) BFD_RELOC_NONE #endif -/* Targets which support SFrame format will define this and return true. */ -#ifndef support_sframe_p -# define support_sframe_p() false -#endif - /* Private segment collection list. */ struct dwcfi_seg_list { @@ -414,7 +409,7 @@ alloc_fde_entry (void) fde->lsda_encoding = DW_EH_PE_omit; fde->eh_header_type = EH_COMPACT_UNKNOWN; #ifdef tc_fde_entry_init_extra - tc_fde_entry_init_extra (fde) + tc_fde_entry_init_extra (fde); #endif return fde; @@ -2277,7 +2272,7 @@ select_cie_for_fde (struct fde_entry *fde, bool eh_frame, cie->personality = fde->personality; cie->first = fde->data; #ifdef tc_cie_entry_init_extra - tc_cie_entry_init_extra (cie, fde) + tc_cie_entry_init_extra (cie, fde); #endif for (i = cie->first; i ; i = i->next) @@ -2606,6 +2601,7 @@ cfi_finish (void) - .sframe in the .cfi_sections directive. */ if (flag_gen_sframe || (all_cfi_sections & CFI_EMIT_sframe) != 0) { +#ifdef support_sframe_p if (support_sframe_p () && !SUPPORT_FRAME_LINKONCE) { segT sframe_seg; @@ -2615,9 +2611,11 @@ cfi_finish (void) (SEC_ALLOC | SEC_LOAD | SEC_DATA | DWARF2_EH_FRAME_READ_ONLY), alignment); + elf_section_type (sframe_seg) = SHT_GNU_SFRAME; output_sframe (sframe_seg); } else +#endif as_bad (_(".sframe not supported for target")); } diff --git a/gas/testsuite/gas/aarch64/armv8-ras-1.d b/gas/testsuite/gas/aarch64/armv8-ras-1.d index b10495f..21596c0 100644 --- a/gas/testsuite/gas/aarch64/armv8-ras-1.d +++ b/gas/testsuite/gas/aarch64/armv8-ras-1.d @@ -1,4 +1,4 @@ -#as: -march=armv8-a+ras +#as: -menable-sysreg-checking -march=armv8-a+ras #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.d b/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.d index 2c00b65..a429d2d 100644 --- a/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.d +++ b/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.d @@ -1,3 +1,3 @@ -#as: -march=armv8.4-a+crypto+sm4+sha3 +#as: -menable-sysreg-checking -march=armv8.4-a+crypto+sm4+sha3 #source: armv8_4-a-registers-illegal.s #error_output: armv8_4-a-registers-illegal.l diff --git a/gas/testsuite/gas/aarch64/armv8_4-a-registers.d b/gas/testsuite/gas/aarch64/armv8_4-a-registers.d index f643c89..f8768c3 100644 --- a/gas/testsuite/gas/aarch64/armv8_4-a-registers.d +++ b/gas/testsuite/gas/aarch64/armv8_4-a-registers.d @@ -1,4 +1,4 @@ -#as: -march=armv8.4-a +#as: -menable-sysreg-checking -march=armv8.4-a #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/cmpbr.d b/gas/testsuite/gas/aarch64/cmpbr.d index 457fdd7..9096350 100644 --- a/gas/testsuite/gas/aarch64/cmpbr.d +++ b/gas/testsuite/gas/aarch64/cmpbr.d @@ -1,5 +1,6 @@ #name: Test for FEAT_CMPBR #as: -march=armv8-a+cmpbr +#as: -march=armv9.6-a #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/fprcvt.d b/gas/testsuite/gas/aarch64/fprcvt.d index 9129858..f44690b 100644 --- a/gas/testsuite/gas/aarch64/fprcvt.d +++ b/gas/testsuite/gas/aarch64/fprcvt.d @@ -1,5 +1,6 @@ #name: FPRCVT instructions #as: -march=armv8-a+fprcvt +#as: -march=armv9.6-a #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/gpc3.d b/gas/testsuite/gas/aarch64/gpc3.d index 2535aef..749a0ae 100644 --- a/gas/testsuite/gas/aarch64/gpc3.d +++ b/gas/testsuite/gas/aarch64/gpc3.d @@ -1,5 +1,5 @@ #name: RME_GPC3 System register -#as: -march=armv9.5-a +#as: -menable-sysreg-checking -march=armv9.5-a #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/illegal-ite1-1.d b/gas/testsuite/gas/aarch64/illegal-ite1-1.d index 99ef4d4..d655d2d 100644 --- a/gas/testsuite/gas/aarch64/illegal-ite1-1.d +++ b/gas/testsuite/gas/aarch64/illegal-ite1-1.d @@ -1,3 +1,3 @@ -#as: -march=armv8-a +#as: -menable-sysreg-checking -march=armv8-a #source: ite1.s -#error_output: illegal-ite1-1.l
\ No newline at end of file +#error_output: illegal-ite1-1.l diff --git a/gas/testsuite/gas/aarch64/illegal-predres2-1.d b/gas/testsuite/gas/aarch64/illegal-predres2-1.d index f858afd..ff73ac8 100644 --- a/gas/testsuite/gas/aarch64/illegal-predres2-1.d +++ b/gas/testsuite/gas/aarch64/illegal-predres2-1.d @@ -1,3 +1,3 @@ -#as: -march=armv8-a +#as: -menable-sysreg-checking -march=armv8-a #source: predres2.s -#error_output: illegal-predres2-1.l
\ No newline at end of file +#error_output: illegal-predres2-1.l diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l index 62f063a..4b97425 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -50,27 +50,27 @@ [^ :]+:[0-9]+: Error: expected a register at operand 1 -- `addp z32\.s,p0/m,z32\.s,z0\.s' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `addp z0\.s,p0/m,z0\.s,z32\.s' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `addp z0\.s,p8/m,z0\.s,z0\.s' -[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesd z0\.b,z0\.b,z0\.b' +[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesd z0\.b,z0\.b,z0\.b' [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesd z0\.b,z1\.b,z0\.b' [^ :]+:[0-9]+: Error: operand mismatch -- `aesd z0\.b,z0\.s,z0\.b' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: aesd z0\.b, z0\.b, z0\.b [^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `aesd z32\.b,z0\.b,z0\.b' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aesd z0\.b,z0\.b,z32\.b' -[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aese z0\.b,z0\.b,z0\.b' +[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aese z0\.b,z0\.b,z0\.b' [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aese z0\.b,z1\.b,z0\.b' [^ :]+:[0-9]+: Error: operand mismatch -- `aese z0\.b,z0\.s,z0\.b' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: aese z0\.b, z0\.b, z0\.b [^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `aese z32\.b,z0\.b,z0\.b' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aese z0\.b,z0\.b,z32\.b' -[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesimc z0\.b,z0\.b' +[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesimc z0\.b,z0\.b' [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesimc z0\.b,z1\.b' [^ :]+:[0-9]+: Error: operand mismatch -- `aesimc z0\.b,z0\.s' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: aesimc z0\.b, z0\.b [^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesimc z32\.b,z0\.b' -[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesmc z0\.b,z0\.b' +[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesmc z0\.b,z0\.b' [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesmc z0\.b,z1\.b' [^ :]+:[0-9]+: Error: operand mismatch -- `aesmc z0\.b,z0\.s' [^ :]+:[0-9]+: Info: did you mean this\? diff --git a/gas/testsuite/gas/aarch64/illegal.d b/gas/testsuite/gas/aarch64/illegal.d index 33bbb0c..7367f9b 100644 --- a/gas/testsuite/gas/aarch64/illegal.d +++ b/gas/testsuite/gas/aarch64/illegal.d @@ -1,4 +1,4 @@ #name: Illegal Instructions -#as: -mno-verbose-error +#as: -menable-sysreg-checking -mno-verbose-error #source: illegal.s #error_output: illegal.l diff --git a/gas/testsuite/gas/aarch64/ite1.d b/gas/testsuite/gas/aarch64/ite1.d index 10ccbda..a0d2b62 100644 --- a/gas/testsuite/gas/aarch64/ite1.d +++ b/gas/testsuite/gas/aarch64/ite1.d @@ -1,4 +1,4 @@ -#as: -march=armv9.4-a+ite +#as: -menable-sysreg-checking -march=armv9.4-a+ite #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/lsui.d b/gas/testsuite/gas/aarch64/lsui.d index 0a052c3..7a1d922 100644 --- a/gas/testsuite/gas/aarch64/lsui.d +++ b/gas/testsuite/gas/aarch64/lsui.d @@ -1,6 +1,7 @@ #name: FEAT_LSUI Test #objdump: -dr #as:-march=armv9-a+lsui+fp +#as:-march=armv9.6-a .*: file format .* diff --git a/gas/testsuite/gas/aarch64/mec-arch-bad.d b/gas/testsuite/gas/aarch64/mec-arch-bad.d index d2e6416..8538b7d 100644 --- a/gas/testsuite/gas/aarch64/mec-arch-bad.d +++ b/gas/testsuite/gas/aarch64/mec-arch-bad.d @@ -1,4 +1,4 @@ #name: MEC unavailable for architecture below armv9.2-a -#as: -march=armv9.1-a +#as: -menable-sysreg-checking -march=armv9.1-a #source: mec.s #error_output: mec-arch-bad.l diff --git a/gas/testsuite/gas/aarch64/mec.d b/gas/testsuite/gas/aarch64/mec.d index 070f831..7a16791 100644 --- a/gas/testsuite/gas/aarch64/mec.d +++ b/gas/testsuite/gas/aarch64/mec.d @@ -1,5 +1,5 @@ #name: MEC System registers -#as: -march=armv9.2-a +#as: -menable-sysreg-checking -march=armv9.2-a #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/msr.d b/gas/testsuite/gas/aarch64/msr.d index fedf2ee..815c778 100644 --- a/gas/testsuite/gas/aarch64/msr.d +++ b/gas/testsuite/gas/aarch64/msr.d @@ -1,4 +1,4 @@ -#as: -march=armv8.2-a+profile +#as: -menable-sysreg-checking -march=armv8.2-a+profile #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/mte_tagged_stack.d b/gas/testsuite/gas/aarch64/mte_tagged_stack.d new file mode 100644 index 0000000..5e8afb8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/mte_tagged_stack.d @@ -0,0 +1,47 @@ +#objdump: --dwarf=frames +# This test is only valid on ELF based ports. +#notarget: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +# Test assembling a file with functions using MTE tagged stack or not +# It must interpret .cfi_mte_tagged_frame properly and emit a +# 'G' character into the correct CIE's augmentation string. + +.+: file .+ + +Contents of the .eh_frame section: + +0+ 0+14 0+ CIE + Version: 1 + Augmentation: "zRG" + Code alignment factor: 4 + Data alignment factor: -8 + Return address column: 30 + Augmentation data: 1b + DW_CFA_def_cfa: r31 \(sp\) ofs 0 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +0+18 0+14 0+1c FDE cie=0+ pc=0+\.\.0+4 + DW_CFA_advance_loc: 4 to 0+4 + DW_CFA_def_cfa_offset: 16 + DW_CFA_offset: r29 \(x29\) at cfa-16 + DW_CFA_offset: r30 \(x30\) at cfa-8 + +0+30 0+10 0+0 CIE + Version: 1 + Augmentation: "zR" + Code alignment factor: 4 + Data alignment factor: -8 + Return address column: 30 + Augmentation data: 1b + DW_CFA_def_cfa: r31 \(sp\) ofs 0 + +0+44 0+1(4|8) 0+18 FDE cie=0+30 pc=0+4\.\.0+8 + DW_CFA_advance_loc: 4 to 0+8 + DW_CFA_def_cfa_offset: 16 + DW_CFA_offset: r29 \(x29\) at cfa-16 + DW_CFA_offset: r30 \(x30\) at cfa-8 +#? DW_CFA_nop +#? DW_CFA_nop +#? DW_CFA_nop +#? DW_CFA_nop diff --git a/gas/testsuite/gas/aarch64/mte_tagged_stack.s b/gas/testsuite/gas/aarch64/mte_tagged_stack.s new file mode 100644 index 0000000..64a92b4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/mte_tagged_stack.s @@ -0,0 +1,24 @@ + .arch armv8-a+memtag + .text + .align 2 + .global foo + .type foo, %function +foo: + .cfi_startproc + .cfi_mte_tagged_frame + stp x29, x30, [sp, -16]! + .cfi_def_cfa_offset 16 + .cfi_offset 29, -16 + .cfi_offset 30, -8 + .cfi_endproc + .size foo, .-foo + .align 2 + .global bar + .type bar, %function +bar: + .cfi_startproc + stp x29, x30, [sp, -16]! + .cfi_def_cfa_offset 16 + .cfi_offset 29, -16 + .cfi_offset 30, -8 + .cfi_endproc diff --git a/gas/testsuite/gas/aarch64/occmo-memtag.d b/gas/testsuite/gas/aarch64/occmo-memtag.d index 0dbbab0..5a20fd4 100644 --- a/gas/testsuite/gas/aarch64/occmo-memtag.d +++ b/gas/testsuite/gas/aarch64/occmo-memtag.d @@ -1,5 +1,6 @@ #name: FEAT_OCCMO + MEMTAG Test #as: -march=armv8-a+occmo+memtag +#as: -march=armv9.6-a+memtag #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/occmo.d b/gas/testsuite/gas/aarch64/occmo.d index 0ec68e8..4267413 100644 --- a/gas/testsuite/gas/aarch64/occmo.d +++ b/gas/testsuite/gas/aarch64/occmo.d @@ -1,5 +1,6 @@ #name: FEAT_OCCMO Test #as: -march=armv8-a+occmo +#as: -march=armv9.6-a #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/pan-directive.d b/gas/testsuite/gas/aarch64/pan-directive.d index b7e4378..51fac24 100644 --- a/gas/testsuite/gas/aarch64/pan-directive.d +++ b/gas/testsuite/gas/aarch64/pan-directive.d @@ -1,5 +1,5 @@ #objdump: -dr -#as: --defsym DIRECTIVE=1 +#as: -menable-sysreg-checking --defsym DIRECTIVE=1 #source: pan.s .*: file format .* diff --git a/gas/testsuite/gas/aarch64/pan.d b/gas/testsuite/gas/aarch64/pan.d index 46c3631..e79602b 100644 --- a/gas/testsuite/gas/aarch64/pan.d +++ b/gas/testsuite/gas/aarch64/pan.d @@ -1,5 +1,5 @@ #objdump: -dr -#as: -march=armv8-a+pan +#as: -menable-sysreg-checking -march=armv8-a+pan .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sme-8.d b/gas/testsuite/gas/aarch64/sme-8.d index c956baa..e550d0a 100644 --- a/gas/testsuite/gas/aarch64/sme-8.d +++ b/gas/testsuite/gas/aarch64/sme-8.d @@ -1,5 +1,5 @@ #name: SME mode selection and state access instructions -#as: -march=armv8-a+sme +#as: -menable-sysreg-checking -march=armv8-a+sme #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/ssbs-illegal2.d b/gas/testsuite/gas/aarch64/ssbs-illegal2.d index d35757c..aeef026 100644 --- a/gas/testsuite/gas/aarch64/ssbs-illegal2.d +++ b/gas/testsuite/gas/aarch64/ssbs-illegal2.d @@ -1,3 +1,3 @@ -#as: -march=armv8-a --defsym ERROR2=1 +#as: -menable-sysreg-checking -march=armv8-a --defsym ERROR2=1 #source: ssbs.s #error_output: ssbs-illegal2.l diff --git a/gas/testsuite/gas/aarch64/ssbs1.d b/gas/testsuite/gas/aarch64/ssbs1.d index daeda76..6dfa178 100644 --- a/gas/testsuite/gas/aarch64/ssbs1.d +++ b/gas/testsuite/gas/aarch64/ssbs1.d @@ -1,6 +1,6 @@ #source: ssbs.s #objdump: -dr -#as: -march=armv8-a+ssbs --defsym SUCCESS=1 +#as: -menable-sysreg-checking -march=armv8-a+ssbs --defsym SUCCESS=1 .*: file format .* diff --git a/gas/testsuite/gas/aarch64/ssbs2.d b/gas/testsuite/gas/aarch64/ssbs2.d index 0027026..68eef6b 100644 --- a/gas/testsuite/gas/aarch64/ssbs2.d +++ b/gas/testsuite/gas/aarch64/ssbs2.d @@ -1,6 +1,6 @@ #source: ssbs.s #objdump: -dr -#as: -march=armv8.5-a --defsym SUCCESS=1 +#as: -menable-sysreg-checking -march=armv8.5-a --defsym SUCCESS=1 .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sve-missing-qualifiers.d b/gas/testsuite/gas/aarch64/sve-missing-qualifiers.d new file mode 100644 index 0000000..5f00db8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-missing-qualifiers.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+sve2+sme2p1+sve-f16f32mm+f8f32mm+f8f16mm+sve-bfscale+i8mm+f64mm+f32mm+lut+sme-lutv2 +#error_output: sve-missing-qualifiers.l diff --git a/gas/testsuite/gas/aarch64/sve-missing-qualifiers.l b/gas/testsuite/gas/aarch64/sve-missing-qualifiers.l new file mode 100644 index 0000000..a258ef5 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-missing-qualifiers.l @@ -0,0 +1,36 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: operand mismatch -- `fmmla z0\.s,z0\.h,z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmmla z0\.s, z0\.h, z0\.h +[^ :]+:[0-9]+: Error: operand mismatch -- `fmmla z0\.s,z0\.b,z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmmla z0\.s, z0\.b, z0\.b +[^ :]+:[0-9]+: Error: operand mismatch -- `fmmla z0\.h,z0\.b,z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmmla z0\.h, z0\.b, z0\.b +[^ :]+:[0-9]+: Error: operand mismatch -- `fmmla z0,z0,z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmmla z0\.d, z0\.d, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `bfscale z0\.h,p0/m,z0,z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfscale z0\.h, p0/m, z0\.h, z0\.h +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmul {z0\.h-z3\.h},{z0\.h-z3\.h},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmul {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Error: operand mismatch -- `smmla z0\.s,z0\.b,z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: smmla z0\.s, z0\.b, z0\.b +[^ :]+:[0-9]+: Error: operand mismatch -- `ld1rob {z0\.b},p0,\[x0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: ld1rob {z0\.b}, p0/z, \[x0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `fmmla z0\.d,z0\.d,z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmmla z0\.d, z0\.d, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `fmmla z0\.s,z0,z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmmla z0\.s, z0\.s, z0\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0,{z0\.b},z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z0\.b, {z0\.b}, z0\[0\] +[^ :]+:[0-9]+: Error: missing type suffix at operand 1 -- `luti4 {z0-z3},zt0,{z0-z1}' +[^ :]+:[0-9]+: Error: missing type suffix at operand 1 -- `luti4 {z0,z4,z8,z12},zt0,{z0-z1}' diff --git a/gas/testsuite/gas/aarch64/sve-missing-qualifiers.s b/gas/testsuite/gas/aarch64/sve-missing-qualifiers.s new file mode 100644 index 0000000..64ee8db --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-missing-qualifiers.s @@ -0,0 +1,13 @@ + fmmla z0.s, z0.h, z0 + fmmla z0.s, z0.b, z0 + fmmla z0.h, z0.b, z0 + fmmla z0, z0, z0 + bfscale z0.h, p0/m, z0, z0.h + bfmul {z0.h-z3.h}, {z0.h-z3.h}, z0 + smmla z0.s, z0.b, z0 + ld1rob {z0.b}, p0, [x0] + fmmla z0.d, z0.d, z0 + fmmla z0.s, z0, z0.s + luti2 z0, {z0.b}, z0[0] + luti4 {z0-z3}, zt0, {z0-z1} + luti4 {z0, z4, z8, z12}, zt0, {z0-z1} diff --git a/gas/testsuite/gas/aarch64/sve2p2.d b/gas/testsuite/gas/aarch64/sve2p2.d index f401cb4..128e350 100644 --- a/gas/testsuite/gas/aarch64/sve2p2.d +++ b/gas/testsuite/gas/aarch64/sve2p2.d @@ -1,5 +1,6 @@ #as: -march=armv8-a+sve2p2 #as: -march=armv8-a+sme2p2 +#as: -march=armv9.6-a #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_8-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv8_8-a-sysregs.d index 294fed2..8b66bcf 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_8-a-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_8-a-sysregs.d @@ -1,4 +1,4 @@ -#as: -march=armv8.8-a +#as: -menable-sysreg-checking -march=armv8.8-a #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.d b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.d index a2cb5fe..862d474 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.d @@ -1,3 +1,3 @@ #source: armv8_9-a-sysregs.s -#as: -march=armv8.8-a -I$srcdir/$subdir --no-info +#as: -menable-sysreg-checking -march=armv8.8-a -I$srcdir/$subdir --no-info #error_output: armv8_9-a-sysregs-bad.l diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d index ca675c4..91e77bc 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d @@ -1,5 +1,5 @@ #source: armv8_9-a-sysregs.s -#as: -march=armv8.9-a -I$srcdir/$subdir +#as: -menable-sysreg-checking -march=armv8.9-a -I$srcdir/$subdir #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d index 8ad01bc..61054ae 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d @@ -1,3 +1,3 @@ #source: armv9_5-a-sysregs.s -#as: -march=armv9.4-a -I$srcdir/$subdir +#as: -menable-sysreg-checking -march=armv9.4-a -I$srcdir/$subdir #error_output: armv9_5-a-sysregs-archv9_4-unsupported.l diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d index c52142d..55a534e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d @@ -1,5 +1,5 @@ #source: armv9_5-a-sysregs.s -#as: -march=armv9.5-a -I$srcdir/$subdir +#as: -menable-sysreg-checking -march=armv9.5-a -I$srcdir/$subdir #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/fp8-feature-enables-fpmr.d b/gas/testsuite/gas/aarch64/sysreg/fp8-feature-enables-fpmr.d index edef376..b6a4706 100644 --- a/gas/testsuite/gas/aarch64/sysreg/fp8-feature-enables-fpmr.d +++ b/gas/testsuite/gas/aarch64/sysreg/fp8-feature-enables-fpmr.d @@ -1,6 +1,6 @@ #name: Test that fpmr register is gated and available via the fp8 feature #source: fpmr.s -#as: -march=armv9.2-a+fp8 +#as: -menable-sysreg-checking -march=armv9.2-a+fp8 #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/fpmr-unsupported-by-default.d b/gas/testsuite/gas/aarch64/sysreg/fpmr-unsupported-by-default.d index c0b30c2..5f116e6 100644 --- a/gas/testsuite/gas/aarch64/sysreg/fpmr-unsupported-by-default.d +++ b/gas/testsuite/gas/aarch64/sysreg/fpmr-unsupported-by-default.d @@ -1,4 +1,4 @@ #name: Test that fpmr register is not supported by default #source: fpmr.s -#as: -march=armv9.2-a +#as: -menable-sysreg-checking -march=armv9.2-a #error_output: fpmr-unsupported-by-default.l diff --git a/gas/testsuite/gas/aarch64/sysreg/gcs-sysregs-bad.d b/gas/testsuite/gas/aarch64/sysreg/gcs-sysregs-bad.d index 439c1bd..3201a84 100644 --- a/gas/testsuite/gas/aarch64/sysreg/gcs-sysregs-bad.d +++ b/gas/testsuite/gas/aarch64/sysreg/gcs-sysregs-bad.d @@ -1,3 +1,3 @@ -#as: -march=armv8-a +#as: -menable-sysreg-checking -march=armv8-a #source: gcs-sysregs.s #error_output: gcs-sysregs-bad.l diff --git a/gas/testsuite/gas/aarch64/sysreg/gcs-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/gcs-sysregs.d index f75c270..9d8082d 100644 --- a/gas/testsuite/gas/aarch64/sysreg/gcs-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/gcs-sysregs.d @@ -1,5 +1,5 @@ #name: Test of Guarded Control Stack system registers -#as: -march=armv8.8-a+gcs +#as: -menable-sysreg-checking -march=armv8.8-a+gcs #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-3.d b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-3.d index 1c5c9d9..b07919d 100644 --- a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-3.d +++ b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-3.d @@ -1,3 +1,3 @@ #source: sysreg-3.s -#as: -march=armv8-a -I$srcdir/$subdir --no-info +#as: -menable-sysreg-checking -march=armv8-a -I$srcdir/$subdir --no-info #error_output: illegal-sysreg-3.l diff --git a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4.d index 34dd4e4..5a11d2e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4.d +++ b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4.d @@ -1,3 +1,3 @@ #source: sysreg-4.s -#as: -march=armv8-a +#as: -menable-sysreg-checking -march=armv8-a #error_output: illegal-sysreg-4.l diff --git a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4b.d b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4b.d index 1504f5f..d32c1a2 100644 --- a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4b.d +++ b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4b.d @@ -1,2 +1,2 @@ -#as: -march=armv8-a +#as: -menable-sysreg-checking -march=armv8-a #error_output: illegal-sysreg-4b.l diff --git a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-5.d b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-5.d index d108d0f..4815663 100644 --- a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-5.d +++ b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-5.d @@ -1,3 +1,3 @@ -#as: -march=armv8.3-a +#as: -menable-sysreg-checking -march=armv8.3-a #source: sysreg-5.s #error_output: illegal-sysreg-5.l diff --git a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-7.d b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-7.d index 98bc9a0..72311a7 100644 --- a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-7.d +++ b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-7.d @@ -1,2 +1,3 @@ +#as: -menable-sysreg-checking #source: illegal-sysreg-7.s #error_output: illegal-sysreg-7.l diff --git a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-8.d b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-8.d index 1e91d49..5b88d3e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-8.d +++ b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-8.d @@ -1,2 +1,2 @@ -#as: --no-info +#as: -menable-sysreg-checking --no-info #error_output: illegal-sysreg-8.l diff --git a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-8b.d b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-8b.d index aed5b17..9d3f32b 100644 --- a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-8b.d +++ b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-8b.d @@ -1,2 +1,2 @@ -#as: --no-info +#as: -menable-sysreg-checking --no-info #warning_output: illegal-sysreg-8b.l diff --git a/gas/testsuite/gas/aarch64/sysreg/mpam-bad.d b/gas/testsuite/gas/aarch64/sysreg/mpam-bad.d index c3ec372..7d9938e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/mpam-bad.d +++ b/gas/testsuite/gas/aarch64/sysreg/mpam-bad.d @@ -1,3 +1,3 @@ -#as: -march=armv9.3-a +#as: -march=armv9.3-a -menable-sysreg-checking #source: mpam-bad.s #error_output: mpam-bad.l diff --git a/gas/testsuite/gas/aarch64/sysreg/pops-sysregs-bad.d b/gas/testsuite/gas/aarch64/sysreg/pops-sysregs-bad.d index 61a6b21..58d05bf 100644 --- a/gas/testsuite/gas/aarch64/sysreg/pops-sysregs-bad.d +++ b/gas/testsuite/gas/aarch64/sysreg/pops-sysregs-bad.d @@ -1,3 +1,3 @@ #source: pops-sysregs-bad.s -#as: -I$srcdir/$subdir +#as: -menable-sysreg-checking -I$srcdir/$subdir #error_output: pops-sysregs-bad.l diff --git a/gas/testsuite/gas/aarch64/sysreg/pops-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/pops-sysregs.d index db04ab8..83729b4 100644 --- a/gas/testsuite/gas/aarch64/sysreg/pops-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/pops-sysregs.d @@ -1,5 +1,5 @@ #source: pops-sysregs.s -#as: -I$srcdir/$subdir +#as: -menable-sysreg-checking -I$srcdir/$subdir #objdump: -dr [^:]+: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sme-sysreg-illegal.d b/gas/testsuite/gas/aarch64/sysreg/sme-sysreg-illegal.d index ff0e855..6eae656 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sme-sysreg-illegal.d +++ b/gas/testsuite/gas/aarch64/sysreg/sme-sysreg-illegal.d @@ -1,3 +1,3 @@ -#as: -march=armv8-a+sme +#as: -menable-sysreg-checking -march=armv8-a+sme #source: sme-sysreg-illegal.s #warning_output: sme-sysreg-illegal.l diff --git a/gas/testsuite/gas/aarch64/sysreg/sme-sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sme-sysreg.d index 8eaf73c..f51c56e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sme-sysreg.d +++ b/gas/testsuite/gas/aarch64/sysreg/sme-sysreg.d @@ -1,5 +1,5 @@ #name: SME extension (system registers) -#as: -march=armv8-a+sme +#as: -menable-sysreg-checking -march=armv8-a+sme #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sve-sysreg-invalid.d b/gas/testsuite/gas/aarch64/sysreg/sve-sysreg-invalid.d index bfe2d27..03a72b7 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sve-sysreg-invalid.d +++ b/gas/testsuite/gas/aarch64/sysreg/sve-sysreg-invalid.d @@ -1,3 +1,3 @@ -#as: -march=armv8-a+nosve +#as: -menable-sysreg-checking -march=armv8-a+nosve #source: sve-sysreg.s #error_output: sve-sysreg-invalid.l diff --git a/gas/testsuite/gas/aarch64/sysreg/sve-sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sve-sysreg.d index 22d9e5ac..2b3a24b 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sve-sysreg.d +++ b/gas/testsuite/gas/aarch64/sysreg/sve-sysreg.d @@ -1,4 +1,4 @@ -#as: -march=armv8-a+sve +#as: -menable-sysreg-checking -march=armv8-a+sve #objdump: -dr diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d index cecb1ad..d770133 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d @@ -1,5 +1,5 @@ #source: sysreg-1.s -#as: -I$srcdir/$subdir +#as: -menable-sysreg-checking -I$srcdir/$subdir #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-10-bad.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-10-bad.d index 628de52..b47e92c 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-10-bad.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-10-bad.d @@ -1,3 +1,3 @@ #source: sysreg-10.s -#as: -march=armv8.7-a -I$srcdir/$subdir +#as: -menable-sysreg-checking -march=armv8.7-a -I$srcdir/$subdir #error_output: sysreg-10-bad.l diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-10.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-10.d index f07df91..55ab50e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-10.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-10.d @@ -1,5 +1,5 @@ #source: sysreg-10.s -#as: -march=armv8.8-a -I$srcdir/$subdir +#as: -menable-sysreg-checking -march=armv8.8-a -I$srcdir/$subdir #objdump: -dr [^:]+: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d index 1845902..140d462 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d @@ -1,5 +1,5 @@ #source: sysreg-2.s -#as: -march=armv8.2-a+profile -I$srcdir/$subdir +#as: -menable-sysreg-checking -march=armv8.2-a+profile -I$srcdir/$subdir #objdump: -dr .*: file .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d index 0135762..7f2ece1 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d @@ -1,5 +1,5 @@ #source: sysreg-3.s -#as: -march=armv8.3-a -I$srcdir/$subdir +#as: -menable-sysreg-checking -march=armv8.3-a -I$srcdir/$subdir #objdump: -dr .*: file .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-4.d index f0fffbe..dd832c2 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-4.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-4.d @@ -1,5 +1,5 @@ #source: sysreg-4.s -#as: -march=armv8.5-a+rng+memtag +#as: -menable-sysreg-checking -march=armv8.5-a+rng+memtag #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-6.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-6.d index cb9c46e..ef8560f 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-6.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-6.d @@ -1,5 +1,5 @@ #source: sysreg-6.s -#as: -I$srcdir/$subdir +#as: -menable-sysreg-checking -I$srcdir/$subdir #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d index 846ab8b..df65924 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d @@ -1,5 +1,5 @@ #source: sysreg-7.s -#as: -I$srcdir/$subdir +#as: -menable-sysreg-checking -I$srcdir/$subdir #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d index 4ee851f..8a1b07f 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d @@ -1,5 +1,5 @@ #source: sysreg-8.s -#as: -I$srcdir/$subdir +#as: -menable-sysreg-checking -I$srcdir/$subdir #objdump: -dr .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-9-bad.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-9-bad.d index a1ebac6..72d188e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-9-bad.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-9-bad.d @@ -1,3 +1,3 @@ #source: sysreg-9-bad.s -#as: -I$srcdir/$subdir +#as: -menable-sysreg-checking -I$srcdir/$subdir #error_output: sysreg-9-bad.l diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-9.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-9.d index 61b63ce..a7fa07e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-9.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-9.d @@ -1,5 +1,5 @@ #source: sysreg-9.s -#as: -I$srcdir/$subdir +#as: -menable-sysreg-checking -I$srcdir/$subdir #objdump: -dr diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.d index 55cdf09..35267f5 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.d @@ -1,5 +1,5 @@ #objdump: -dr -M notes -#as: -march=armv8-a +#as: -menable-sysreg-checking -march=armv8-a #warning_output: sysreg-diagnostic.l .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sysreg.d index 9aba548..d17c77f 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.d @@ -1,5 +1,5 @@ #source: sysreg.s -#as: -I$srcdir/$subdir +#as: -menable-sysreg-checking -I$srcdir/$subdir #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg128.d b/gas/testsuite/gas/aarch64/sysreg/sysreg128.d index 22df5e2..ffd7517 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg128.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg128.d @@ -1,5 +1,5 @@ #source: sysreg128.s -#as: -I$srcdir/$subdir +#as: -menable-sysreg-checking -I$srcdir/$subdir #objdump: -dr .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.d b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.d new file mode 100644 index 0000000..95ddd32 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.d @@ -0,0 +1,3 @@ +#source: sysregs_with_no_restrictions.s +#as: -menable-sysreg-checking -I$srcdir/$subdir +#error_output: sysregs_with_no_restrictions-bad.l diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l new file mode 100644 index 0000000..f70dba9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l @@ -0,0 +1,173 @@ +.*: Assembler messages: +.*: Error: selected processor does not support system register name 'mpuir_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'afsr0_el12' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'afsr0_el12' +.*: Info: macro invoked from here +.*: Error: selected processor does not support PSTATE field name 'uao' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'uao' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'uao' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'apdakeyhi_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'apdakeyhi_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'amcfgr_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'vsttbr_el2' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'vsttbr_el2' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'scxtnum_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'scxtnum_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'id_pfr2_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'amcg1idr_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'hcrx_el2' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'hcrx_el2' +.*: Info: macro invoked from here +.*: Error: selected processor does not support PSTATE field name 'allint' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'allint' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'allint' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pfar_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pfar_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pir_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pir_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmecr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmecr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'hdfgrtr2_el2' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'hdfgrtr2_el2' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'mdselr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'mdselr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmicfiltr_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmicfiltr_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmsdsfr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmsdsfr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmuacr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmuacr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'por_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'por_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 's2pir_el2' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 's2pir_el2' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 's2por_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 's2por_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'sctlr2_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'sctlr2_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'spmaccessr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'spmaccessr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'tcr2_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'tcr2_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'amair2_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'amair2_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmccntsvr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'vdisr_el3' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'vdisr_el3' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'spmzr_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'spmzr_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'mdstepop_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'mdstepop_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'gpcbw_el3' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'gpcbw_el3' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmbmar_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmbmar_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'erxgsr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'fpmr' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'fpmr' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'id_aa64zfr0_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'lorc_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'lorc_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmbidr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'gcspr_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'gcspr_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'id_aa64smfr0_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'trcitecr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'trcitecr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'gcr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'gcr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'rndr' +.*: Info: macro invoked from here +.*: Error: selected processor does not support PSTATE field name 'pan' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pan' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pan' +.*: Info: macro invoked from here +.*: Error: selected processor does not support PSTATE field name 'ssbs' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'ssbs' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'ssbs' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'rcwmask_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'rcwmask_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'ttbr1_el2' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'ttbr1_el2' +.*: Info: macro invoked from here diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d new file mode 100644 index 0000000..f311c23 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d @@ -0,0 +1,95 @@ +#as: -I$srcdir/$subdir +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d5380080 mrs x0, mpuir_el1 +.*: d51d5100 msr afsr0_el12, x0 +.*: d53d5100 mrs x0, afsr0_el12 +.*: d5184280 msr uao, x0 +.*: d5384280 mrs x0, uao +.*: d5182220 msr apdakeyhi_el1, x0 +.*: d5382220 mrs x0, apdakeyhi_el1 +.*: d53bd220 mrs x0, amcfgr_el0 +.*: d51c2600 msr vsttbr_el2, x0 +.*: d53c2600 mrs x0, vsttbr_el2 +.*: d51bd0e0 msr scxtnum_el0, x0 +.*: d53bd0e0 mrs x0, scxtnum_el0 +.*: d5380380 mrs x0, id_pfr2_el1 +.*: d53bd2c0 mrs x0, amcg1idr_el0 +.*: d51c1240 msr hcrx_el2, x0 +.*: d53c1240 mrs x0, hcrx_el2 +.*: d5184300 msr allint, x0 +.*: d5384300 mrs x0, allint +.*: d51860a0 msr pfar_el1, x0 +.*: d53860a0 mrs x0, pfar_el1 +.*: d518a260 msr pir_el1, x0 +.*: d538a260 mrs x0, pir_el1 +.*: d5189ea0 msr pmecr_el1, x0 +.*: d5389ea0 mrs x0, pmecr_el1 +.*: d51c3100 msr hdfgrtr2_el2, x0 +.*: d53c3100 mrs x0, hdfgrtr2_el2 +.*: d5100440 msr mdselr_el1, x0 +.*: d5300440 mrs x0, mdselr_el1 +.*: d51b9600 msr pmicfiltr_el0, x0 +.*: d53b9600 mrs x0, pmicfiltr_el0 +.*: d5189a80 msr pmsdsfr_el1, x0 +.*: d5389a80 mrs x0, pmsdsfr_el1 +.*: d5189e80 msr pmuacr_el1, x0 +.*: d5389e80 mrs x0, pmuacr_el1 +.*: d51ba280 msr por_el0, x0 +.*: d53ba280 mrs x0, por_el0 +.*: d51ca2a0 msr s2pir_el2, x0 +.*: d53ca2a0 mrs x0, s2pir_el2 +.*: d518a2a0 msr s2por_el1, x0 +.*: d538a2a0 mrs x0, s2por_el1 +.*: d5181060 msr sctlr2_el1, x0 +.*: d5381060 mrs x0, sctlr2_el1 +.*: d5109d60 msr spmaccessr_el1, x0 +.*: d5309d60 mrs x0, spmaccessr_el1 +.*: d5182060 msr tcr2_el1, x0 +.*: d5382060 mrs x0, tcr2_el1 +.*: d518a320 msr amair2_el1, x0 +.*: d538a320 mrs x0, amair2_el1 +.*: d530ebe0 mrs x0, pmccntsvr_el1 +.*: d51ec120 msr vdisr_el3, x0 +.*: d53ec120 mrs x0, vdisr_el3 +.*: d5139c80 msr spmzr_el0, x0 +.*: d5339c80 mrs x0, spmzr_el0 +.*: d5100540 msr mdstepop_el1, x0 +.*: d5300540 mrs x0, mdstepop_el1 +.*: d51e21a0 msr gpcbw_el3, x0 +.*: d53e21a0 mrs x0, gpcbw_el3 +.*: d5189aa0 msr pmbmar_el1, x0 +.*: d5389aa0 mrs x0, pmbmar_el1 +.*: d5385340 mrs x0, erxgsr_el1 +.*: d51b4440 msr fpmr, x0 +.*: d53b4440 mrs x0, fpmr +.*: d5380480 mrs x0, id_aa64zfr0_el1 +.*: d518a460 msr lorc_el1, x0 +.*: d538a460 mrs x0, lorc_el1 +.*: d5389ae0 mrs x0, pmbidr_el1 +.*: d51b2520 msr gcspr_el0, x0 +.*: d53b2520 mrs x0, gcspr_el0 +.*: d53804a0 mrs x0, id_aa64smfr0_el1 +.*: d5181260 msr trcitecr_el1, x0 +.*: d5381260 mrs x0, trcitecr_el1 +.*: d51810c0 msr gcr_el1, x0 +.*: d53810c0 mrs x0, gcr_el1 +.*: d53b2400 mrs x0, rndr +.*: d518c120 msr disr_el1, x0 +.*: d538c120 mrs x0, disr_el1 +.*: d5184260 msr pan, x0 +.*: d5384260 mrs x0, pan +.*: d51b42c0 msr ssbs, x0 +.*: d53b42c0 mrs x0, ssbs +.*: d558d0c2 msrr rcwmask_el1, x2, x3 +.*: d578d0c2 mrrs x2, x3, rcwmask_el1 +.*: d55c2002 msrr ttbr0_el2, x2, x3 +.*: d57c2002 mrrs x2, x3, ttbr0_el2 +.*: d55c2022 msrr ttbr1_el2, x2, x3 +.*: d57c2022 mrrs x2, x3, ttbr1_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s new file mode 100644 index 0000000..f5c1138 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s @@ -0,0 +1,56 @@ + .include "sysreg-test-utils.inc" +.text + rw_sys_reg mpuir_el1 w=0 // V8R + rw_sys_reg afsr0_el12 // V8_1A + rw_sys_reg uao // V8_2A + rw_sys_reg apdakeyhi_el1 // V8_3A + rw_sys_reg amcfgr_el0 w=0 // V8_4A + rw_sys_reg vsttbr_el2 // V8A && V8_4A + rw_sys_reg scxtnum_el0 // SCXTNUM + rw_sys_reg id_pfr2_el1 w=0 // ID_PFR2 + rw_sys_reg amcg1idr_el0 w=0 // V8_6A + rw_sys_reg hcrx_el2 // V8_7A + rw_sys_reg allint // V8_8A + + rw_sys_reg pfar_el1 // PFAR + rw_sys_reg pir_el1 // S1PIE + rw_sys_reg pmecr_el1 // SEBEP + rw_sys_reg hdfgrtr2_el2 // FGT2 + rw_sys_reg mdselr_el1 // DEBUGv8p9 + rw_sys_reg pmicfiltr_el0 // PMUv3_ICNTR + rw_sys_reg pmsdsfr_el1 // SPE_FDS + rw_sys_reg pmuacr_el1 // PMUv3p9 + rw_sys_reg por_el0 // S1POE + rw_sys_reg s2pir_el2 // S2PIE + rw_sys_reg s2por_el1 // S2POE + rw_sys_reg sctlr2_el1 // SCTLR2 + rw_sys_reg spmaccessr_el1 // SPMU + rw_sys_reg tcr2_el1 // TCR2 + rw_sys_reg amair2_el1 // AIE + rw_sys_reg pmccntsvr_el1 w=0 // PMUv3_SS + + rw_sys_reg vdisr_el3 // E3DES + rw_sys_reg spmzr_el0 // SPMU2 + rw_sys_reg mdstepop_el1 // STEP2 + rw_sys_reg gpcbw_el3 // V9_5A + + rw_sys_reg pmbmar_el1 // PROFILE && V9_5A + + rw_sys_reg erxgsr_el1 w=0 // RASv2 + rw_sys_reg fpmr // FP8 + rw_sys_reg id_aa64zfr0_el1 w=0 // SVE + rw_sys_reg lorc_el1 // LOR + rw_sys_reg pmbidr_el1 w=0 // PROFILE + rw_sys_reg gcspr_el0 // GCS + rw_sys_reg id_aa64smfr0_el1 w=0 // SME + rw_sys_reg trcitecr_el1 // ITE + rw_sys_reg gcr_el1 // MEMTAG + rw_sys_reg rndr w=0 // RNG + rw_sys_reg disr_el1 // RAS + rw_sys_reg pan // PAN + rw_sys_reg ssbs // SSBS + + .arch_extension d128 // For the msrr and mrrs instructions. + rw_sys_reg_128 rcwmask_el1 xreg1=x2 xreg2=x3 // THE + rw_sys_reg_128 ttbr0_el2 xreg1=x2 xreg2=x3 // V8A + rw_sys_reg_128 ttbr1_el2 xreg1=x2 xreg2=x3 // V8A && V8_1A diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d new file mode 100644 index 0000000..bca119d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d @@ -0,0 +1,95 @@ +#as: -menable-sysreg-checking -I$srcdir/$subdir +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d5380080 mrs x0, mpuir_el1 +.*: d51d5100 msr afsr0_el12, x0 +.*: d53d5100 mrs x0, afsr0_el12 +.*: d5184280 msr uao, x0 +.*: d5384280 mrs x0, uao +.*: d5182220 msr apdakeyhi_el1, x0 +.*: d5382220 mrs x0, apdakeyhi_el1 +.*: d53bd220 mrs x0, amcfgr_el0 +.*: d51c2600 msr vsttbr_el2, x0 +.*: d53c2600 mrs x0, vsttbr_el2 +.*: d51bd0e0 msr scxtnum_el0, x0 +.*: d53bd0e0 mrs x0, scxtnum_el0 +.*: d5380380 mrs x0, id_pfr2_el1 +.*: d53bd2c0 mrs x0, amcg1idr_el0 +.*: d51c1240 msr hcrx_el2, x0 +.*: d53c1240 mrs x0, hcrx_el2 +.*: d5184300 msr allint, x0 +.*: d5384300 mrs x0, allint +.*: d51860a0 msr pfar_el1, x0 +.*: d53860a0 mrs x0, pfar_el1 +.*: d518a260 msr pir_el1, x0 +.*: d538a260 mrs x0, pir_el1 +.*: d5189ea0 msr pmecr_el1, x0 +.*: d5389ea0 mrs x0, pmecr_el1 +.*: d51c3100 msr hdfgrtr2_el2, x0 +.*: d53c3100 mrs x0, hdfgrtr2_el2 +.*: d5100440 msr mdselr_el1, x0 +.*: d5300440 mrs x0, mdselr_el1 +.*: d51b9600 msr pmicfiltr_el0, x0 +.*: d53b9600 mrs x0, pmicfiltr_el0 +.*: d5189a80 msr pmsdsfr_el1, x0 +.*: d5389a80 mrs x0, pmsdsfr_el1 +.*: d5189e80 msr pmuacr_el1, x0 +.*: d5389e80 mrs x0, pmuacr_el1 +.*: d51ba280 msr por_el0, x0 +.*: d53ba280 mrs x0, por_el0 +.*: d51ca2a0 msr s2pir_el2, x0 +.*: d53ca2a0 mrs x0, s2pir_el2 +.*: d518a2a0 msr s2por_el1, x0 +.*: d538a2a0 mrs x0, s2por_el1 +.*: d5181060 msr sctlr2_el1, x0 +.*: d5381060 mrs x0, sctlr2_el1 +.*: d5109d60 msr spmaccessr_el1, x0 +.*: d5309d60 mrs x0, spmaccessr_el1 +.*: d5182060 msr tcr2_el1, x0 +.*: d5382060 mrs x0, tcr2_el1 +.*: d518a320 msr amair2_el1, x0 +.*: d538a320 mrs x0, amair2_el1 +.*: d530ebe0 mrs x0, pmccntsvr_el1 +.*: d51ec120 msr vdisr_el3, x0 +.*: d53ec120 mrs x0, vdisr_el3 +.*: d5139c80 msr spmzr_el0, x0 +.*: d5339c80 mrs x0, spmzr_el0 +.*: d5100540 msr mdstepop_el1, x0 +.*: d5300540 mrs x0, mdstepop_el1 +.*: d51e21a0 msr gpcbw_el3, x0 +.*: d53e21a0 mrs x0, gpcbw_el3 +.*: d5189aa0 msr pmbmar_el1, x0 +.*: d5389aa0 mrs x0, pmbmar_el1 +.*: d5385340 mrs x0, erxgsr_el1 +.*: d51b4440 msr fpmr, x0 +.*: d53b4440 mrs x0, fpmr +.*: d5380480 mrs x0, id_aa64zfr0_el1 +.*: d518a460 msr lorc_el1, x0 +.*: d538a460 mrs x0, lorc_el1 +.*: d5389ae0 mrs x0, pmbidr_el1 +.*: d51b2520 msr gcspr_el0, x0 +.*: d53b2520 mrs x0, gcspr_el0 +.*: d53804a0 mrs x0, id_aa64smfr0_el1 +.*: d5181260 msr trcitecr_el1, x0 +.*: d5381260 mrs x0, trcitecr_el1 +.*: d51810c0 msr gcr_el1, x0 +.*: d53810c0 mrs x0, gcr_el1 +.*: d53b2400 mrs x0, rndr +.*: d518c120 msr disr_el1, x0 +.*: d538c120 mrs x0, disr_el1 +.*: d5184260 msr pan, x0 +.*: d5384260 mrs x0, pan +.*: d51b42c0 msr ssbs, x0 +.*: d53b42c0 mrs x0, ssbs +.*: d558d0c2 msrr rcwmask_el1, x2, x3 +.*: d578d0c2 mrrs x2, x3, rcwmask_el1 +.*: d55c2002 msrr ttbr0_el2, x2, x3 +.*: d57c2002 mrrs x2, x3, ttbr0_el2 +.*: d55c2022 msrr ttbr1_el2, x2, x3 +.*: d57c2022 mrrs x2, x3, ttbr1_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s new file mode 100644 index 0000000..0cdb822 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s @@ -0,0 +1,93 @@ + .include "sysreg-test-utils.inc" +.text + .arch armv8-r + rw_sys_reg mpuir_el1 w=0 // V8R + + .arch armv8.1-a + rw_sys_reg afsr0_el12 // V8_1A + + .arch armv8.2-a + rw_sys_reg uao // V8_2A + + .arch armv8.3-a + rw_sys_reg apdakeyhi_el1 // V8_3A + + .arch armv8.4-a + rw_sys_reg amcfgr_el0 w=0 // V8_4A + rw_sys_reg vsttbr_el2 // V8A && V8_4A + + .arch armv8.5-a + rw_sys_reg scxtnum_el0 // SCXTNUM + rw_sys_reg id_pfr2_el1 w=0 // ID_PFR2 + + .arch armv8.6-a + rw_sys_reg amcg1idr_el0 w=0 // V8_6A + + .arch armv8.7-a + rw_sys_reg hcrx_el2 // V8_7A + + .arch armv8.8-a + rw_sys_reg allint // V8_8A + + .arch armv8.9-a + rw_sys_reg pfar_el1 // PFAR + rw_sys_reg pir_el1 // S1PIE + rw_sys_reg pmecr_el1 // SEBEP + rw_sys_reg hdfgrtr2_el2 // FGT2 + rw_sys_reg mdselr_el1 // DEBUGv8p9 + rw_sys_reg pmicfiltr_el0 // PMUv3_ICNTR + rw_sys_reg pmsdsfr_el1 // SPE_FDS + rw_sys_reg pmuacr_el1 // PMUv3p9 + rw_sys_reg por_el0 // S1POE + rw_sys_reg s2pir_el2 // S2PIE + rw_sys_reg s2por_el1 // S2POE + rw_sys_reg sctlr2_el1 // SCTLR2 + rw_sys_reg spmaccessr_el1 // SPMU + rw_sys_reg tcr2_el1 // TCR2 + rw_sys_reg amair2_el1 // AIE + rw_sys_reg pmccntsvr_el1 w=0 // PMUv3_SS + + .arch armv9.5-a + rw_sys_reg vdisr_el3 // E3DES + rw_sys_reg spmzr_el0 // SPMU2 + rw_sys_reg mdstepop_el1 // STEP2 + rw_sys_reg gpcbw_el3 // V9_5A + + .arch armv9.5-a+profile + rw_sys_reg pmbmar_el1 // PROFILE && V9_5A + + .arch_extension rasv2 + rw_sys_reg erxgsr_el1 w=0 // RASv2 + .arch_extension fp8 + rw_sys_reg fpmr // FP8 + .arch_extension sve + rw_sys_reg id_aa64zfr0_el1 w=0 // SVE + .arch_extension lor + rw_sys_reg lorc_el1 // LOR + .arch_extension profile + rw_sys_reg pmbidr_el1 w=0 // PROFILE + .arch_extension gcs + rw_sys_reg gcspr_el0 // GCS + .arch_extension sme + rw_sys_reg id_aa64smfr0_el1 w=0 // SME + .arch_extension ite + rw_sys_reg trcitecr_el1 // ITE + .arch_extension memtag + rw_sys_reg gcr_el1 // MEMTAG + .arch_extension rng + rw_sys_reg rndr w=0 // RNG + .arch_extension ras + rw_sys_reg disr_el1 // RAS + .arch_extension pan + rw_sys_reg pan // PAN + .arch_extension ssbs + rw_sys_reg ssbs // SSBS + + .arch_extension d128 // For the msrr and mrrs instructions. + .arch_extension the + rw_sys_reg_128 rcwmask_el1 xreg1=x2 xreg2=x3 // THE + + .arch armv8-a+d128 + rw_sys_reg_128 ttbr0_el2 xreg1=x2 xreg2=x3 // V8A + .arch armv8.1-a+d128 + rw_sys_reg_128 ttbr1_el2 xreg1=x2 xreg2=x3 // V8A && V8_1A diff --git a/gas/testsuite/gas/aarch64/sysreg/v8-r-bad-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/v8-r-bad-sysregs.d index 6677f3b..a228b59 100644 --- a/gas/testsuite/gas/aarch64/sysreg/v8-r-bad-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/v8-r-bad-sysregs.d @@ -1,3 +1,4 @@ #name: invalid system registers for Armv8-R AArch64 +#as: -menable-sysreg-checking #source: v8-r-bad-sysregs.s #error_output: v8-r-bad-sysregs.l diff --git a/gas/testsuite/gas/aarch64/sysreg/v8-r-sysregs-need-arch.d b/gas/testsuite/gas/aarch64/sysreg/v8-r-sysregs-need-arch.d index af83196..98756de 100644 --- a/gas/testsuite/gas/aarch64/sysreg/v8-r-sysregs-need-arch.d +++ b/gas/testsuite/gas/aarch64/sysreg/v8-r-sysregs-need-arch.d @@ -1,3 +1,4 @@ #name: check that Armv8-R system registers are rejected without -march=armv8-r +#as: -menable-sysreg-checking #source: v8-r-sysregs.s #error_output: v8-r-sysregs-need-arch.l diff --git a/gas/testsuite/gas/aarch64/sysreg/v8-r-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/v8-r-sysregs.d index aa8321e..03e7fab 100644 --- a/gas/testsuite/gas/aarch64/sysreg/v8-r-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/v8-r-sysregs.d @@ -1,5 +1,5 @@ #name: Exhaustive test of Armv8-R system registers -#as: -march=armv8-r +#as: -menable-sysreg-checking -march=armv8-r #objdump: -dr -m aarch64:armv8-r .*: file format .* diff --git a/gas/testsuite/gas/aarch64/uao-directive.d b/gas/testsuite/gas/aarch64/uao-directive.d index 1dbe847..617d73f 100644 --- a/gas/testsuite/gas/aarch64/uao-directive.d +++ b/gas/testsuite/gas/aarch64/uao-directive.d @@ -1,5 +1,5 @@ #objdump: -dr -#as: --defsym DIRECTIVE=1 +#as: -menable-sysreg-checking --defsym DIRECTIVE=1 #source: uao.s .*: file format .* diff --git a/gas/testsuite/gas/aarch64/uao.d b/gas/testsuite/gas/aarch64/uao.d index 2fb67b1..387654c 100644 --- a/gas/testsuite/gas/aarch64/uao.d +++ b/gas/testsuite/gas/aarch64/uao.d @@ -1,5 +1,5 @@ #objdump: -dr -#as: -march=armv8.2-a +#as: -menable-sysreg-checking -march=armv8.2-a .*: file format .* diff --git a/gas/testsuite/gas/aarch64/virthostext-directive.d b/gas/testsuite/gas/aarch64/virthostext-directive.d index 22e8d54..5e23cad 100644 --- a/gas/testsuite/gas/aarch64/virthostext-directive.d +++ b/gas/testsuite/gas/aarch64/virthostext-directive.d @@ -1,5 +1,5 @@ #objdump: -dr -#as: --defsym DIRECTIVE=1 +#as: -menable-sysreg-checking --defsym DIRECTIVE=1 #source: virthostext.s diff --git a/gas/testsuite/gas/aarch64/virthostext.d b/gas/testsuite/gas/aarch64/virthostext.d index 8e63efa..2181906 100644 --- a/gas/testsuite/gas/aarch64/virthostext.d +++ b/gas/testsuite/gas/aarch64/virthostext.d @@ -1,5 +1,5 @@ #objdump: -dr -#as: -march=armv8.1-a +#as: -menable-sysreg-checking -march=armv8.1-a #source: virthostext.s diff --git a/gas/testsuite/gas/cfi-sframe/cfi-sframe-common-1b.d b/gas/testsuite/gas/cfi-sframe/cfi-sframe-common-1b.d new file mode 100644 index 0000000..c6ddfba --- /dev/null +++ b/gas/testsuite/gas/cfi-sframe/cfi-sframe-common-1b.d @@ -0,0 +1,6 @@ +#as: --gsframe +#readelf: -S +#name: SFrame section header in readelf output +#... +[ ]*\[.*\][ ]+\.sframe[ ]+GNU_SFRAME.* +#... diff --git a/gas/testsuite/gas/cfi-sframe/cfi-sframe-common-1b.s b/gas/testsuite/gas/cfi-sframe/cfi-sframe-common-1b.s new file mode 100644 index 0000000..ac9c6ca --- /dev/null +++ b/gas/testsuite/gas/cfi-sframe/cfi-sframe-common-1b.s @@ -0,0 +1,3 @@ + .cfi_sections .sframe + .cfi_startproc + .cfi_endproc diff --git a/gas/testsuite/gas/cfi-sframe/cfi-sframe.exp b/gas/testsuite/gas/cfi-sframe/cfi-sframe.exp index 9c5a16f..8a42419 100644 --- a/gas/testsuite/gas/cfi-sframe/cfi-sframe.exp +++ b/gas/testsuite/gas/cfi-sframe/cfi-sframe.exp @@ -72,6 +72,7 @@ if { ([istarget "x86_64-*-*"] || [istarget "aarch64*-*-*"] set old_ASFLAGS "$ASFLAGS" run_dump_test "cfi-sframe-common-1" + run_dump_test "cfi-sframe-common-1b" run_dump_test "cfi-sframe-common-2" run_dump_test "cfi-sframe-common-3" run_dump_test "cfi-sframe-common-4" diff --git a/gdb/MAINTAINERS b/gdb/MAINTAINERS index 79b2233..9284c46 100644 --- a/gdb/MAINTAINERS +++ b/gdb/MAINTAINERS @@ -608,6 +608,7 @@ Raoul Gough RaoulGough@yahoo.co.uk Anthony Green green@redhat.com Matthew Green mrg@eterna.com.au Matthew Gretton-Dann matthew.gretton-dann@arm.com +Aaron Griffith aargri@gmail.com Maxim Grigoriev maxim2405@gmail.com Jerome Guitton guitton@act-europe.fr Alexandra Hájková ahajkova@redhat.com diff --git a/include/elf/aarch64.h b/include/elf/aarch64.h index e218e07..74bd7b4 100644 --- a/include/elf/aarch64.h +++ b/include/elf/aarch64.h @@ -52,6 +52,8 @@ #define DT_AARCH64_BTI_PLT (DT_LOPROC + 1) #define DT_AARCH64_PAC_PLT (DT_LOPROC + 3) #define DT_AARCH64_VARIANT_PCS (DT_LOPROC + 5) +#define DT_AARCH64_MEMTAG_MODE (DT_LOPROC + 9) +#define DT_AARCH64_MEMTAG_STACK (DT_LOPROC + 12) /* AArch64-specific values for st_other. */ #define STO_AARCH64_VARIANT_PCS 0x80 /* Symbol may follow different call diff --git a/include/elf/common.h b/include/elf/common.h index f395278..0d9a7b7 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -568,6 +568,7 @@ #define SHT_ANDROID_RELR 0x6fffff00 +#define SHT_GNU_SFRAME 0x6ffffff4 /* SFrame stack trace information. */ #define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes */ #define SHT_GNU_HASH 0x6ffffff6 /* GNU style symbol hash table */ #define SHT_GNU_LIBLIST 0x6ffffff7 /* List of prelink dependencies */ diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 826bd7d..4425dd4 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -304,6 +304,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_V9_4A, /* Armv9.5-A processors. */ AARCH64_FEATURE_V9_5A, + /* Armv9.6-A processors. */ + AARCH64_FEATURE_V9_6A, /* FPRCVT instructions. */ AARCH64_FEATURE_FPRCVT, /* Point of Physical Storage. */ @@ -473,6 +475,12 @@ static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL, | AARCH64_FEATBIT (X, SPMU2) \ | AARCH64_FEATBIT (X, STEP2) \ ) +#define AARCH64_ARCH_V9_6A_FEATURES(X) (AARCH64_FEATBIT (X, V9_6A) \ + | AARCH64_FEATBIT (X, CMPBR) \ + | AARCH64_FEATBIT (X, FPRCVT) \ + | AARCH64_FEATBIT (X, LSUI) \ + | AARCH64_FEATBIT (X, OCCMO) \ + | AARCH64_FEATBIT (X, SVE2p2)) /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \ @@ -512,6 +520,8 @@ static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL, | AARCH64_ARCH_V9_4A_FEATURES (X)) #define AARCH64_ARCH_V9_5A(X) (AARCH64_ARCH_V9_4A (X) \ | AARCH64_ARCH_V9_5A_FEATURES (X)) +#define AARCH64_ARCH_V9_6A(X) (AARCH64_ARCH_V9_5A (X) \ + | AARCH64_ARCH_V9_6A_FEATURES (X)) #define AARCH64_ARCH_NONE(X) 0 @@ -1541,7 +1551,24 @@ extern const aarch64_opcode aarch64_opcode_table[]; /* For LSFE instructions with size[30:31] field. */ #define F_LSFE_SZ (1ULL << 41) -/* Next bit is 42. */ + +/* When parsing immediate values, register names should not be misinterpreted + as symbols. However, for backwards compatibility we need to permit some + newer register names within older instructions. These flags specify which + register names are invalid immediate value, and are required for all + instructions with immediate operands (and are otherwise ignored). */ +#define F_INVALID_IMM_SYMS (3ULL << 42) + +/* Any GP or SIMD register except WSP/SP. */ +#define F_INVALID_IMM_SYMS_1 (1ULL << 42) + +/* As above, plus WSP/SP, and Z and P registers. */ +#define F_INVALID_IMM_SYMS_2 (2ULL << 42) + +/* As above, plus PN registers. */ +#define F_INVALID_IMM_SYMS_3 (3ULL << 42) + +/* Next bit is 44. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ diff --git a/include/sframe-api.h b/include/sframe-api.h index ac4f19a..8c26257 100644 --- a/include/sframe-api.h +++ b/include/sframe-api.h @@ -153,14 +153,6 @@ sframe_decoder_get_fixed_fp_offset (sframe_decoder_ctx *dctx); extern int8_t sframe_decoder_get_fixed_ra_offset (sframe_decoder_ctx *dctx); -/* Find the function descriptor entry which contains the specified address. - - Note: This function is deprecated and will be removed from future release - X+2 of the library. */ -extern void * -sframe_get_funcdesc_with_addr (sframe_decoder_ctx *dctx, int32_t addr, - int *errp); - /* Find the SFrame Frame Row Entry which contains the PC. Returns SFRAME_ERR if failure. */ @@ -9,6 +9,8 @@ sfde_func_start_address field in the SFrame section. Relocatable SFrame links are now fixed. + ELF SFrame sections now have section type set to SHT_GNU_SFRAME. + * On RISC-V, add new PLT formats, and GNU property merge rules for zicfiss and zicfilp extensions. @@ -35,6 +37,12 @@ * On s390, add support for linker option --[no-]ld-generated-unwind-info. +* On LoongArch, linker relaxation time complexity is no longer quadratic with + respect to relocation counts. Linking time of large software should be + improved. + +* On LoongArch, R_LARCH_32_PCREL records are now checked for overflow. + Changes in 2.44: * Support for Nios II target has been removed, as this architecture has been diff --git a/ld/emultempl/aarch64elf.em b/ld/emultempl/aarch64elf.em index afa91af..66eaf1c 100644 --- a/ld/emultempl/aarch64elf.em +++ b/ld/emultempl/aarch64elf.em @@ -42,6 +42,11 @@ static aarch64_protection_opts sw_protections = { .gcs_report_dynamic = MARKING_UNSET, }; +static aarch64_memtag_opts memtag_opts = { + .memtag_mode = AARCH64_MEMTAG_MODE_NONE, + .memtag_stack = 0, +}; + #define COMPILE_TIME_STRLEN(s) \ (sizeof(s) - 1) @@ -335,7 +340,8 @@ aarch64_elf_create_output_section_statements (void) pic_veneer, fix_erratum_835769, fix_erratum_843419, no_apply_dynamic_relocs, - &sw_protections); + &sw_protections, + &memtag_opts); stub_file = lang_add_input_file ("linker stubs", lang_input_file_is_fake_enum, @@ -440,6 +446,31 @@ aarch64_parse_gcs_option (const char *_optarg) #undef GCS #undef GCS_LEN } + +static bool +aarch64_parse_memtag_mode_option (const char *optarg) +{ + #define MEMTAG_MODE "memtag-mode" + #define MEMTAG_MODE_LEN COMPILE_TIME_STRLEN (MEMTAG_MODE) + + if (strncmp (optarg, MEMTAG_MODE, MEMTAG_MODE_LEN) != 0) + return false; + + if (strcmp (optarg + MEMTAG_MODE_LEN, "=none") == 0) + memtag_opts.memtag_mode = AARCH64_MEMTAG_MODE_NONE; + else if (strcmp (optarg + MEMTAG_MODE_LEN, "=sync") == 0) + memtag_opts.memtag_mode = AARCH64_MEMTAG_MODE_SYNC; + else if (strcmp (optarg + MEMTAG_MODE_LEN, "=async") == 0) + memtag_opts.memtag_mode = AARCH64_MEMTAG_MODE_ASYNC; + else + einfo (_("%X%P: error: unrecognized value '-z %s'\n"), optarg); + + return true; + + #undef MEMTAG_MODE + #undef MEMTAG_MODE_LEN +} + EOF # Define some shell vars to insert bits of code into the standard elf @@ -518,6 +549,17 @@ PARSE_AND_LIST_OPTIONS=' and output have GCS marking.\n\ error: Emit error when the input objects are missing GCS markings\n\ and output have GCS marking.\n")); + fprintf (file, _("\ + -z memtag-mode[=none|sync|async] Select Memory Tagging Extension mode of operation to use.\n\ + Emits a DT_AARCH64_MEMTAG_MODE dynamic tag for the binary.\n\ + This entry is only valid on the main executable. It is\n\ + ignored in the dynamically loaded objects by the loader.\n\ + none (default): Disable MTE checking of memory reads and writes.\n\ + sync: Enable precise exceptions when mismatched address and\n\ + allocation tags detected on load/store operations.\n\ + async: Enable imprecise exceptions.\n")); + fprintf (file, _("\ + -z memtag-stack Mark program stack with MTE protection.\n")); ' PARSE_AND_LIST_ARGS_CASE_Z_AARCH64=' @@ -533,6 +575,10 @@ PARSE_AND_LIST_ARGS_CASE_Z_AARCH64=' {} else if (aarch64_parse_gcs_option (optarg)) {} + else if (aarch64_parse_memtag_mode_option (optarg)) + {} + else if (strcmp (optarg, "memtag-stack") == 0) + memtag_opts.memtag_stack = 1; ' PARSE_AND_LIST_ARGS_CASE_Z="$PARSE_AND_LIST_ARGS_CASE_Z $PARSE_AND_LIST_ARGS_CASE_Z_AARCH64" @@ -8374,6 +8374,21 @@ GCS markings. If issues are found, a maximum of 20 messages will be emitted, and then a summary with the total number of issues will be displayed at the end. +@kindex -z memtag-mode=@var{mode} +@cindex MTE modes of operation +The @samp{-z memtag-mode=mode} specifies the MTE mode of operation. +The value of @samp{mode} can be one of @samp{none}, @samp{sync} or +@samp{async}. The specified modes determine the value of the +@samp{DT_AARCH64_MEMTAG_MODE} dynamic tag. The @samp{sync} mode +implies precise exceptions, with the runtime providing the exact +instruction where the fault occurred, and the exact faulting address. +The @samp{async} mode implies imprecise exceptions. + +@kindex -z memtag-stack +@cindex Mark program stack for MTE protection +The @samp{-z memtag-stack} specifies that output object uses MTE +instructions for stack memory usage. + @ifclear GENERIC @lowersections @end ifclear diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp index 4de498f..8d56beb 100644 --- a/ld/testsuite/ld-aarch64/aarch64-elf.exp +++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp @@ -376,6 +376,10 @@ run_dump_test_lp64 "variant_pcs-r" run_dump_test_lp64 "variant_pcs-shared" run_dump_test_lp64 "variant_pcs-now" +run_dump_test_lp64 "mte-tagged-frame" +run_dump_test_lp64 "dt-memtag-mode" +run_dump_test_lp64 "dt-memtag-stack" + set aarch64elflinktests { {"ld-aarch64/so with global symbol" "-shared" "" "" {copy-reloc-so.s} {} "copy-reloc-so.so"} diff --git a/ld/testsuite/ld-aarch64/dt-memtag-mode.d b/ld/testsuite/ld-aarch64/dt-memtag-mode.d new file mode 100644 index 0000000..21670bc --- /dev/null +++ b/ld/testsuite/ld-aarch64/dt-memtag-mode.d @@ -0,0 +1,7 @@ +#source: dt-memtag.s +#ld: -shared -z memtag-mode=async +#readelf: -d + +#... + 0x0000000070000009 \(AARCH64_MEMTAG_MODE\) 0x1 +#... diff --git a/ld/testsuite/ld-aarch64/dt-memtag-stack.d b/ld/testsuite/ld-aarch64/dt-memtag-stack.d new file mode 100644 index 0000000..242f61f --- /dev/null +++ b/ld/testsuite/ld-aarch64/dt-memtag-stack.d @@ -0,0 +1,7 @@ +#source: dt-memtag.s +#ld: -shared -z memtag-stack +#readelf: -d + +#... + 0x000000007000000c \(AARCH64_MEMTAG_STACK\) 0x1 +#... diff --git a/ld/testsuite/ld-aarch64/dt-memtag.s b/ld/testsuite/ld-aarch64/dt-memtag.s new file mode 100644 index 0000000..51f3ba5 --- /dev/null +++ b/ld/testsuite/ld-aarch64/dt-memtag.s @@ -0,0 +1,7 @@ +// Test DT_AARCH64_MEMTAG_MODE. + +.text +.p2align 3 +.global foo +foo: +.xword foo diff --git a/ld/testsuite/ld-aarch64/mte-tagged-frame-bar.s b/ld/testsuite/ld-aarch64/mte-tagged-frame-bar.s new file mode 100644 index 0000000..0bd5619 --- /dev/null +++ b/ld/testsuite/ld-aarch64/mte-tagged-frame-bar.s @@ -0,0 +1,17 @@ + .text + .global bar + .type bar, %function +bar: + .cfi_startproc + .cfi_mte_tagged_frame + stp x19, x20, [sp, -144]! + .cfi_def_cfa_offset 144 + .cfi_offset 19, -144 + .cfi_offset 20, -136 + ldp x19, x20, [sp], 144 + .cfi_restore 20 + .cfi_restore 19 + .cfi_def_cfa_offset 0 + ret + .cfi_endproc + .size bar, .-bar diff --git a/ld/testsuite/ld-aarch64/mte-tagged-frame-foo.s b/ld/testsuite/ld-aarch64/mte-tagged-frame-foo.s new file mode 100644 index 0000000..af5a8c4 --- /dev/null +++ b/ld/testsuite/ld-aarch64/mte-tagged-frame-foo.s @@ -0,0 +1,16 @@ + .text + .global foo + .type foo, %function +foo: + .cfi_startproc + stp x19, x20, [sp, -32]! + .cfi_def_cfa_offset 32 + .cfi_offset 19, -32 + .cfi_offset 20, -16 + ldp x19, x20, [sp], 32 + .cfi_restore 20 + .cfi_restore 19 + .cfi_def_cfa_offset 0 + ret + .cfi_endproc + .size foo, .-foo diff --git a/ld/testsuite/ld-aarch64/mte-tagged-frame.d b/ld/testsuite/ld-aarch64/mte-tagged-frame.d new file mode 100644 index 0000000..dd667fe --- /dev/null +++ b/ld/testsuite/ld-aarch64/mte-tagged-frame.d @@ -0,0 +1,35 @@ +#source: mte-tagged-frame-foo.s +#source: mte-tagged-frame-bar.s +#ld: -shared +#objdump: -Wf +#name: MTE tagged EH Frame FDE + +#... +Contents of the .eh_frame section: + +00000000 0000000000000010 00000000 CIE + Version: 1 + Augmentation: "zR" + Code alignment factor: 4 + Data alignment factor: -8 + Return address column: 30 + Augmentation data: 1b + DW_CFA_def_cfa: r31 \(sp\) ofs 0 + +00000014 0000000000000020 00000018 FDE cie=00000000 pc=[a-f0-9]+\.\.[a-f0-9]+ +#... + +00000038 0000000000000014 00000000 CIE + Version: 1 + Augmentation: "zRG" + Code alignment factor: 4 + Data alignment factor: -8 + Return address column: 30 + Augmentation data: 1b + DW_CFA_def_cfa: r31 \(sp\) ofs 0 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +00000050 000000000000001c 0000001c FDE cie=00000038 pc=[a-f0-9]+\.\.[a-f0-9]+ +#... diff --git a/libsframe/doc/sframe-spec.texi b/libsframe/doc/sframe-spec.texi index ecc333d..7307789 100644 --- a/libsframe/doc/sframe-spec.texi +++ b/libsframe/doc/sframe-spec.texi @@ -77,9 +77,10 @@ Appendices @section Overview @cindex Overview -The SFrame stack trace information is provided in a loaded section, known as the -@code{.sframe} section. When available, the @code{.sframe} section appears in -a new segment of its own, PT_GNU_SFRAME. +The SFrame stack trace information is provided in a loaded section, known as +the @code{.sframe} section. When available, the @code{.sframe} section appears +in segment of type PT_GNU_SFRAME. An ELF SFrame section will have the type +SHT_GNU_SFRAME. The SFrame format is currently supported only for select ABIs, namely, AMD64, AAPCS64, and s390x. diff --git a/libsframe/libsframe.ver b/libsframe/libsframe.ver index 06324ee..8cc80da 100644 --- a/libsframe/libsframe.ver +++ b/libsframe/libsframe.ver @@ -1,6 +1,6 @@ LIBSFRAME_0.0 { }; -LIBSFRAME_1.0 { +LIBSFRAME_2.0 { global: sframe_decoder_free; sframe_fde_create_func_info; @@ -11,12 +11,13 @@ LIBSFRAME_1.0 { sframe_fre_get_ra_offset; sframe_fre_get_ra_mangled_p; sframe_decode; + sframe_decoder_get_flags; sframe_decoder_get_hdr_size; sframe_decoder_get_abi_arch; sframe_decoder_get_version; + sframe_decoder_get_offsetof_fde_start_addr; sframe_decoder_get_fixed_fp_offset; sframe_decoder_get_fixed_ra_offset; - sframe_get_funcdesc_with_addr; sframe_find_fre; sframe_decoder_get_num_fidx; sframe_decoder_get_funcdesc; @@ -24,9 +25,11 @@ LIBSFRAME_1.0 { sframe_decoder_get_fre; sframe_encode; sframe_encoder_free; + sframe_encoder_get_flags; sframe_encoder_get_hdr_size; sframe_encoder_get_abi_arch; sframe_encoder_get_version; + sframe_encoder_get_offsetof_fde_start_addr; sframe_encoder_get_num_fidx; sframe_encoder_add_fre; sframe_encoder_add_funcdesc; @@ -38,10 +41,3 @@ LIBSFRAME_1.0 { local: *; } LIBSFRAME_0.0; - -LIBSFRAME_1.1 { - sframe_decoder_get_flags; - sframe_decoder_get_offsetof_fde_start_addr; - sframe_encoder_get_flags; - sframe_encoder_get_offsetof_fde_start_addr; -} LIBSFRAME_1.0; diff --git a/libsframe/libtool-version b/libsframe/libtool-version index 9dcbe48..e06835d 100644 --- a/libsframe/libtool-version +++ b/libsframe/libtool-version @@ -27,4 +27,4 @@ # then set age to 0. # # CURRENT:REVISION:AGE -1:0:0 +2:0:0 diff --git a/libsframe/sframe.c b/libsframe/sframe.c index d482d58..7357fc1 100644 --- a/libsframe/sframe.c +++ b/libsframe/sframe.c @@ -876,7 +876,7 @@ sframe_decode_fre (const char *fre_buf, sframe_frame_row_entry *fre, return 0; } -/* Decode the specified SFrame buffer CF_BUF of size CF_SIZE and return the +/* Decode the specified SFrame buffer SF_BUF of size SF_SIZE and return the new SFrame decoder context. Sets ERRP for the caller if any error. Frees up the allocated memory in @@ -1079,18 +1079,6 @@ sframe_decoder_get_offsetof_fde_start_addr (sframe_decoder_ctx *dctx, + offsetof (sframe_func_desc_entry, sfde_func_start_address)); } -/* Find the function descriptor entry which contains the specified address - ADDR. - This function is deprecated and will be removed from libsframe.so.2. */ - -void * -sframe_get_funcdesc_with_addr (sframe_decoder_ctx *ctx __attribute__ ((unused)), - int32_t addr __attribute__ ((unused)), - int *errp) -{ - return sframe_ret_set_errno (errp, SFRAME_ERR_INVAL); -} - /* Find the function descriptor entry starting which contains the specified address ADDR. */ @@ -1639,7 +1627,7 @@ sframe_encoder_add_funcdesc (sframe_encoder_ctx *encoder, int32_t start_addr, uint32_t func_size, unsigned char func_info, - uint32_t num_fres __attribute__ ((unused))) + uint32_t num_fres ATTRIBUTE_UNUSED) { sframe_header *ehp; sf_fde_tbl *fd_info; @@ -1721,7 +1709,7 @@ sframe_encoder_add_funcdesc_v2 (sframe_encoder_ctx *encoder, uint32_t func_size, unsigned char func_info, uint8_t rep_block_size, - uint32_t num_fres __attribute__ ((unused))) + uint32_t num_fres ATTRIBUTE_UNUSED) { sf_fde_tbl *fd_info; int err; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 4de7965..9c4e181 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -5720,10 +5720,21 @@ verify_constraints (const struct aarch64_inst *inst, { /* Check to see if the MOVPRFX SVE instruction is followed by an SVE instruction for better error messages. */ - if (!opcode->avariant - || (!AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE) - && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2) - && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2p1))) + bool sve_operand_p = false; + for (int i = 0; i < AARCH64_MAX_OPND_NUM; ++i) + { + enum aarch64_operand_class op_class + = aarch64_get_operand_class (opcode->operands[i]); + if (op_class == AARCH64_OPND_CLASS_SVE_REG + || op_class == AARCH64_OPND_CLASS_SVE_REGLIST + || op_class == AARCH64_OPND_CLASS_PRED_REG) + { + sve_operand_p = true; + break; + } + } + + if (!sve_operand_p) { mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR; mismatch_detail->error = _("SVE instruction expected after " diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 71563b0..b23fc7c 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2789,12 +2789,7 @@ QLF3(V_4S, V_8H, S_H), \ } -/* Opcode table. - - Any SVE or SVE2 feature must include AARCH64_FEATURE_{SVE|SVE2} in its - bitmask, even if this is implied by other selected feature bits. This - allows verify_constraints to identify SVE instructions when selecting an - error message for MOVPRFX constraint violations. */ +/* Opcode table. */ static const aarch64_feature_set aarch64_feature_v8 = AARCH64_FEATURE (V8); @@ -2873,23 +2868,23 @@ static const aarch64_feature_set aarch64_feature_sve2 = static const aarch64_feature_set aarch64_feature_sve2aes = AARCH64_FEATURES (2, SVE_AES, SVE2_SSVE_AES); static const aarch64_feature_set aarch64_feature_sve2sha3 = - AARCH64_FEATURES (2, SVE2, SVE2_SHA3); + AARCH64_FEATURE (SVE2_SHA3); static const aarch64_feature_set aarch64_feature_sve2sm4 = - AARCH64_FEATURES (2, SVE2, SVE2_SM4); + AARCH64_FEATURE (SVE2_SM4); static const aarch64_feature_set aarch64_feature_sve2bitperm = - AARCH64_FEATURES (2, SVE2, SVE2_BITPERM); + AARCH64_FEATURE (SVE2_BITPERM); static const aarch64_feature_set aarch64_feature_sme = - AARCH64_FEATURES (2, SVE2, SME); + AARCH64_FEATURE (SME); static const aarch64_feature_set aarch64_feature_sme_f64f64 = - AARCH64_FEATURES (3, SVE2, SME, SME_F64F64); + AARCH64_FEATURE (SME_F64F64); static const aarch64_feature_set aarch64_feature_sme_i16i64 = - AARCH64_FEATURES (3, SVE2, SME, SME_I16I64); + AARCH64_FEATURE (SME_I16I64); static const aarch64_feature_set aarch64_feature_sme2 = - AARCH64_FEATURES (3, SVE2, SME, SME2); + AARCH64_FEATURE (SME2); static const aarch64_feature_set aarch64_feature_sme2_i16i64 = - AARCH64_FEATURES (2, SME2, SME_I16I64); + AARCH64_FEATURE (SME_I16I64); static const aarch64_feature_set aarch64_feature_sme2_f64f64 = - AARCH64_FEATURES (2, SME2, SME_F64F64); + AARCH64_FEATURE (SME_F64F64); static const aarch64_feature_set aarch64_feature_i8mm = AARCH64_FEATURE (I8MM); static const aarch64_feature_set aarch64_feature_i8mm_sve = @@ -2929,7 +2924,7 @@ static const aarch64_feature_set aarch64_feature_the = static const aarch64_feature_set aarch64_feature_d128_the = AARCH64_FEATURES (2, D128, THE); static const aarch64_feature_set aarch64_feature_sve_b16b16_sve2 = - AARCH64_FEATURES (2, SVE_B16B16, SVE2); + AARCH64_FEATURES (2, SVE_B16B16, SVE2_SME2); static const aarch64_feature_set aarch64_feature_sve_b16b16_sme2 = AARCH64_FEATURES (2, SVE_B16B16, SME2); static const aarch64_feature_set aarch64_feature_sme_b16b16 = @@ -2961,7 +2956,7 @@ static const aarch64_feature_set aarch64_feature_faminmax = static const aarch64_feature_set aarch64_feature_faminmax_sve2 = AARCH64_FEATURES (2, FAMINMAX, SVE2); static const aarch64_feature_set aarch64_feature_faminmax_sme2 = - AARCH64_FEATURES (3, SVE2, FAMINMAX, SME2); + AARCH64_FEATURES (2, FAMINMAX, SME2); static const aarch64_feature_set aarch64_feature_fp8 = AARCH64_FEATURE (FP8); static const aarch64_feature_set aarch64_feature_fp8_sve2 = @@ -2989,31 +2984,31 @@ static const aarch64_feature_set aarch64_feature_fp8dot4 = static const aarch64_feature_set aarch64_feature_fp8dot2 = AARCH64_FEATURE (FP8DOT2); static const aarch64_feature_set aarch64_feature_fp8fma_sve = - AARCH64_FEATURES (2, FP8FMA_SVE, SVE); + AARCH64_FEATURE (FP8FMA_SVE); static const aarch64_feature_set aarch64_feature_fp8dot4_sve = - AARCH64_FEATURES (2, FP8DOT4_SVE, SVE); + AARCH64_FEATURE (FP8DOT4_SVE); static const aarch64_feature_set aarch64_feature_fp8dot2_sve = - AARCH64_FEATURES (2, FP8DOT2_SVE, SVE); + AARCH64_FEATURE (FP8DOT2_SVE); static const aarch64_feature_set aarch64_feature_sme_f8f32 = - AARCH64_FEATURES (2, SME_F8F32, SME2); + AARCH64_FEATURE (SME_F8F32); static const aarch64_feature_set aarch64_feature_sme_f8f16 = - AARCH64_FEATURES (2, SME_F8F16, SME2); + AARCH64_FEATURE (SME_F8F16); static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 = - AARCH64_FEATURES (2, SME_F16F16_F8F16, SME2); + AARCH64_FEATURE (SME_F16F16_F8F16); static const aarch64_feature_set aarch64_feature_sme_f16f16 = - AARCH64_FEATURES (2, SME_F16F16, SME2); + AARCH64_FEATURE (SME_F16F16); static const aarch64_feature_set aarch64_feature_sve2p1_sme = - AARCH64_FEATURES (2, SVE2p1_SME, SVE); + AARCH64_FEATURE (SVE2p1_SME); static const aarch64_feature_set aarch64_feature_sve2p1_sme2 = - AARCH64_FEATURES (2, SVE2p1_SME2, SVE); + AARCH64_FEATURE (SVE2p1_SME2); static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = - AARCH64_FEATURES (2, SVE2p1_SME2p1, SVE); + AARCH64_FEATURE (SVE2p1_SME2p1); static const aarch64_feature_set aarch64_feature_sme2p2 = - AARCH64_FEATURES (2, SME2p2, SME); + AARCH64_FEATURE (SME2p2); static const aarch64_feature_set aarch64_feature_sve_sme2p2 = - AARCH64_FEATURES (2, SVE_SME2p2, SVE); + AARCH64_FEATURE (SVE_SME2p2); static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = - AARCH64_FEATURES (2, SVE2p2_SME2p2, SVE); + AARCH64_FEATURE (SVE2p2_SME2p2); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -3126,11 +3121,11 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define SVE2p2_SME2p2 &aarch64_feature_sve2p2_sme2p2 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \ { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER } #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3150,21 +3145,21 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, 0, 0, NULL } #define FF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define FPRCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FPRCVT, OPS, QUALS, FLAGS, 0, 0, NULL } #define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, 0, TIED, NULL } #define _SVE_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } #define PAUTH_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, PAUTH, OPS, QUALS, FLAGS, 0, 0, NULL } #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define JSCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, JSCVT, OPS, QUALS, FLAGS, 0, 0, NULL } #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3176,7 +3171,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, 0, NULL } #define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP16_V8_2A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3192,30 +3187,30 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL } #define CMPBR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, CMPBR, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, CMPBR, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, 0, TIED, NULL } #define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } #define SVE_F16F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } #define F8F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, F8F32MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F8F32MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } #define F8F16MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, F8F16MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F8F16MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } #define B16B16_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -3254,7 +3249,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, 0, TIED, NULL } #define SME_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME_F64F64, OPS, QUALS, \ F_STRICT | FLAGS, 0, TIED, NULL } @@ -3266,7 +3261,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_3 | FLAGS, 0, TIED, NULL } #define SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } @@ -3280,36 +3275,34 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } #define SVE_BFSCALE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS, 0, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } #define SVE_BFSCALE_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE_SME2, OPS, QUALS, FLAGS, 0, TIED, NULL } -#define BFLOAT16_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE_SME2, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } #define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS | F_STRICT, \ CONSTRAINTS, TIED, NULL } #define BFLOAT16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16, OPS, QUALS, FLAGS, 0, 0, NULL } #define INT8MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define INT8MATMUL_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, I8MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F64MATMUL_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, 0, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } #define F64MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define F32MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define V8R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL } #define XS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, XS, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, XS, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define WFXT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, WFXT, OPS, QUALS, FLAGS, 0, 0, NULL } #define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL } #define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define MOPS_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \ { NAME, OPCODE, MASK, CLASS, 0, MOPS, OPS, QUALS, FLAGS, CONSTRAINTS, \ 0, VERIFIER } @@ -3319,13 +3312,13 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL } #define CSSC_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define CHK_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL } #define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL } #define D128_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define THE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, the, 0, THE, OPS, QUALS, FLAGS, 0, 0, NULL } #define D128_THE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ @@ -3341,10 +3334,10 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = { NAME, OPCODE, MASK, asimdsame, 0, FAMINMAX, OPS, QUALS, FLAGS, 0, 0, NULL } #define FAMINMAX_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,CONSTRAINTS) \ { NAME, OPCODE, MASK, sve_size_hsd, 0, FAMINMAX_SVE2, OPS, QUALS, \ - 0 | F_STRICT, CONSTRAINTS, 2, NULL } + F_STRICT, CONSTRAINTS, 2, NULL } #define FAMINMAX_SME2_INSN(NAME,OPCODE,MASK,OPS,QUALS) \ { NAME, OPCODE, MASK, sme_size_22_hsd, 0, FAMINMAX_SME2, OPS, QUALS, \ - F_STRICT | 0, 0, 1, NULL } + F_STRICT, 0, 1, NULL } #define FP8_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FP8, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP8_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ @@ -3356,16 +3349,16 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define LUT_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, lut, 0, LUT, OPS, QUALS, FLAGS, 0, 0, NULL } #define LUT_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS,CONSTRAINTS) \ - { NAME, OPCODE, MASK, lut, 0, LUT_SVE2, OPS, QUALS, \ - FLAGS, CONSTRAINTS, 0, NULL } + { NAME, OPCODE, MASK, sve_misc, 0, LUT_SVE2, OPS, QUALS, \ + FLAGS | F_STRICT, CONSTRAINTS, 0, NULL } #define BRBE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, BRBE, OPS, QUALS, FLAGS, 0, 0, NULL } #define LUTv2_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2, OPS, QUALS, \ - FLAGS, 0, 0, NULL } + FLAGS | F_STRICT, 0, 0, NULL } #define LUTv2_SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2p1, OPS, QUALS, \ - FLAGS, 0, 0, NULL } + FLAGS | F_STRICT, 0, 0, NULL } #define FP8FMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FP8FMA, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP8DOT4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3395,7 +3388,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define SVE2p1_SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, 0, TIED, NULL } #define SVE2p1_SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2, OPS, QUALS, \ F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } @@ -3404,7 +3397,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = F_STRICT | FLAGS, 0, TIED, NULL } #define SVE2p1_SME2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2p1, OPS, QUALS, \ - F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, CONSTRAINTS, TIED, NULL } #define SVE_SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE_SME2p2, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } |