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VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As
long as the immediate has the top 4 bits clear, they are equivalent to
the earlier VEX-encoded insns, and hence can be used to permit use of
eGPR-s in the memory operand. Since this is the normal way of using
these insns, also alter the resulting diagnostic to complain about the
immediate, not the eGPR use.
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EVexMap4 already covers that.
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This was missed in 6177c84d5edc ("Support APX GPR32 with extend evex
prefix").
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Some x86 instructions affect the stack pointer implicitly. Add a new
operand constraint to reflect this. This will be useful for SCFI
implmentation to ensure its correctness.
Mark all push, pop, call, ret, enter, leave, INT, iret instructions.
opcodes/
* i386-gen.c: Update opcode_modifiers.
* i386-opc.h: Add a new constraint.
* i386-opc.tbl: Update the affected instructions.
* i386-tbl.h: Regenerated.
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Rex2 is currently an operand constraint. For the upcoming SCFI
implementation in GAS, we need to identify operations which implicitly
update the stack pointer. An operand constraint enumerator for implicit
stack op seems more appropriate than an attribute. However, two opcodes
currently necessitate both Rex2 and an implicit stack op marker; this
prompts revisiting the current representations a bit.
Make Rex2 a standalone attribute, so that later a new operand constraint
may be added for IMPLICIT_STACK_OP.
ChangeLog:
* gas/config/tc-i386.c (is_apx_rex2_encoding): Update the check.
* opcodes/i386-gen.c: Add a new BITFIELD for Rex2.
* opcodes/i386-opc.h (REX2_REQUIRED): Remove.
* opcodes/i386-opc.tbl: Remove Rex2 operand constraint.
* opcodes/i386-tbl.h: Regenerated.
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As already indicated during review, we can't get away without certain
adjustments here: Without these, respective {evex}-prefixed insns are
assembled to APX encodings even when APX_F is turned off.
While there also extend the respective comment in the opcode table, to
explain why this construct is used.
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Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:
1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
author I haven't committed, 'Kalray SA.', to cover gas testsuite
files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
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gas/ChangeLog:
* config/tc-i386.c (process_operands): Handle "PUSHP/POPP requires
rex2.w == 1."
* testsuite/gas/i386/x86-64.exp: Add new test for PUSHP/POPP.
* testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s: Ditto.
* testsuite/gas/i386/x86-64-apx-pushp-popp.d: Ditto.
* testsuite/gas/i386/x86-64-apx-pushp-popp.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (putop): print pushp and popp.
* i386-opc.tbl: Added new insns.
* i386-init.h : Regenerated.
* i386-mnem.h : Regenerated.
* i386-tbl.h: Regenerated.
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PPX functionality for PUSH/POP is not implemented in this patch
and will be implemented separately.
gas/ChangeLog:
2023-12-28 Zewei Mo <zewei.mo@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
* config/tc-i386.c: (enum i386_error):
New unsupported_rsp_register and invalid_src_register_set.
(md_assemble): Add handler for unsupported_rsp_register and
invalid_src_register_set.
(check_APX_operands): Add invalid check for push2/pop2.
(match_template): Handle check_APX_operands.
* testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/x86-64-apx-push2pop2.d: New test.
* testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto.
* testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto.
* testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto.
* testsuite/gas/i386/apx-push2pop2-inval.s: Ditto.
* testsuite/gas/i386/apx-push2pop2-inval.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad
testcases for POP2.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F.
* i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6
* i386-dis-evex.h: Add REG_EVEX_MAP4_8F.
* i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2.
(get_valid_dis386): Add handler for vector length and address_mode for
APX-Push2/Pop2 insn.
(nd): define nd as b for EVEX-promoted instrutions.
(OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn.
* i386-gen.c: Add Push2Pop2 bitfield.
* i386-opc.h: Regenerated.
* i386-opc.tbl: Regenerated.
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opcodes/ChangeLog:
* opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80,
REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6,
REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF.
* opcodes/i386-dis-evex.h: Add NDD insn.
* opcodes/i386-dis.c (nd): New define.
(VexGb): Ditto.
(VexGv): Ditto.
(get_valid_dis386): Change for NDD decode.
(print_insn): Ditto.
(putop): Ditto.
(intel_operand_size): Ditto.
(OP_E_memory): Ditto.
(OP_VEX): Ditto.
* opcodes/i386-opc.h (VexVVVV_DST): New.
* opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV.
* opcodes/i386-tbl.h: Regenerated.
gas/ChangeLog:
* gas/config/tc-i386.c (operand_size_match):
Support APX NDD that the number of operands is 3.
(build_apx_evex_prefix): Change for ndd encode.
(process_operands): Ditto.
(build_modrm_byte): Ditto.
(match_template): Support swap the first two operands for
APX NDD.
* testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd.
* testsuite/gas/i386/x86-64-apx-ndd.d: New test.
* testsuite/gas/i386/x86-64-apx-ndd.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos.d: Add test.
* testsuite/gas/i386/x86-64-pseudos.s: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
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This patch adds non-ND, non-NF forms of EVEX promotion insn.
EVEX extension of legacy instructions:
All promoted legacy instructions are placed in EVEX map 4, which is
currently reserved.
EVEX extension of EVEX instructions:
All existing EVEX instructions are extended by APX using the extended
EVEX prefix, so that they can access all 32 GPRs.
EVEX extension of VEX instructions:
Promoting a VEX instruction into the EVEX space does not change the map
id, the opcode, or the operand encoding of the VEX instruction.
Note: The promoted versions of MOVBE will be extended to include the “MOVBE
reg1, reg2”.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* config/tc-i386.c (struct _i386_insn): Add has_egpr.
(need_evex_encoding): Adjusted for apx.
(cpu_flags_match): Ditto.
(install_template): Handled APX combines.
(is_apx_evex_encoding): Test apx evex encoding.
(build_apx_evex_prefix): Enabe APX evex prefix.
(md_assemble): Handle apx with evex encoding.
(process_suffix): Handle apx map4 prefix.
(check_register): Assign i.vec_encoding for APX evex instructions.
* testsuite/gas/i386/x86-64-evex.d: Adjust test cases.
* testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe.
opcodes/ChangeLog:
* i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3.
* i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0,
PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8,
PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB,
PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD,
PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF,
PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1,
PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8.
* i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0.
* i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn
promote to apx to use gpr32
* opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90,
X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2,
X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6,
X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91.
* i386-dis.c
(struct instr_info): Deleted bool r.
(PREFIX_NP_OR_DATA): New.
(NO_PREFIX): New.
(putop): Ditto.
(X86_64_EVEX_FROM_VEX_TABLE): Diito.
(get_valid_dis386): Decode insn erex in extend evex prefix.
Handle EVEX_MAP4
(print_insn): Handle PREFIX_DATA_AND_NP_ONLY.
(print_register): Handle apx instructions decode.
(OP_E_memory): Diito.
(OP_G): Diito.
(OP_XMM): Diito.
(DistinctDest_Fixup): Diito.
* i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4.
* i386-opc.h (SPACE_EVEXMAP4): Add legacy insn
promote to evex.
* i386-opc.tbl: Handle some legacy and vex insns don't
support gpr32. And add some legacy insn (map2 / 3) promote
to evex.
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APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy
instructions. We added the NoEgpr flag in i386-gen.c for instructions
that do not support EGPR.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* config/tc-i386.c
(enum i386_error): Add unsupported_EGPR_for_addressing
and invalid_pseudo_prefix.
(struct _i386_insn): Add rex2 and rex2_encoding for
gpr32.
(cpu_arch): Add apx_f.
(is_cpu): Ditto.
(register_number): Handle RegRex2 for gpr32.
(is_apx_rex2_encoding): New func. Test rex2 prefix encoding.
(build_rex2_prefix): New func. Build legacy insn in
opcode 0/1 use gpr32 with rex2 prefix.
(establish_rex): Handle rex2 and rex2_encoding.
(optimize_encoding): Handel add r16-r31 for registers.
(md_assemble): Handle apx encoding.
(parse_insn): Handle Prefix_REX2.
(check_EgprOperands): New func. Check if Egprs operands
are valid for the instruction
(match_template): Handle Egpr operands check.
(set_rex_rex2): New func. set i.rex and i.rex2.
(build_modrm_byte): Ditto.
(output_insn): Handle rex2 2-byte prefix output.
(check_register): Handle check egpr illegal without
target apx, 64-bit mode and with rex_prefix.
* doc/c-i386.texi: Document .apx.
* testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid
in 64-bit mode.
* testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto.
* testsuite/gas/i386/rex-bad: Adjust rex testcase.
* testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto.
* testsuite/gas/i386/x86-64-opcode-inval.d: Ditto.
* testsuite/gas/i386/x86-64-opcode-inval.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test.
* testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test.
* testsuite/gas/i386/x86-64-pseudos.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Run APX tests.
* testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test.
* testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test.
* testsuite/gas/i386/x86-64-apx-rex2.d: New test.
* testsuite/gas/i386/x86-64-apx-rex2.s: New test.
include/ChangeLog:
* opcode/i386.h (REX2_OPCODE): New.
(REX2_M): Ditto.
opcodes/ChangeLog:
* i386-dis.c (struct instr_info): Add erex for gpr32.
Add last_erex_prefix for rex2 prefix.
(REX2_M): Extend for gpr32.
(PREFIX_REX2): Ditto.
(PREFIX_REX2_ILLEGAL): Ditto.
(ckprefix): Ditto.
(prefix_name): Ditto.
(print_insn): Ditto.
(print_register): Ditto.
(OP_E_memory): Ditto.
(OP_REG): Ditto.
(OP_EX): Ditto.
* i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix.
(process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions.
(output_i386_opcode): Handle if_entry_needs_special_handle.
* i386-init.h : Regenerated.
* i386-mnem.h : Regenerated.
* i386-opc.h (enum i386_cpu): Add CpuAPX_F.
(NoEgpr): New.
(Prefix_NoOptimize): Ditto.
(Prefix_REX2): Ditto.
(RegRex2): Ditto.
* i386-opc.tbl: Add rex2 prefix.
* i386-reg.tbl: Add egprs (r16-r31).
* i386-tbl.h: Regenerated.
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Since AVX10.1/256 will also allow 64 bit mask register, we will
remove the restriction for size of the mask register in AVX10.
gas/ChangeLog:
* config/tc-i386.c (VSZ128, VSZ256, VSZ512): New.
(VEX_check_encoding): Remove opcode_modifier check for vsz.
* testsuite/gas/i386/avx10-vsz.l: Remove testcases for mask
registers since they are not needed.
* testsuite/gas/i386/avx10-vsz.s: Ditto.
opcodes/ChangeLog:
* i386-gen.c: Remove Vsz.
* i386-opc.h: Ditto.
* i386-opc.tbl: Remove kvsz.
* i386-tbl.h: Regenerated.
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This reverts commit 1f865bae65db9588f6994c02a92355bfb4e3d955. The
specification is going to by updated in a way rendering this change
wrong.
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Now that ATTSyntax and ATTMnemonic aren't use in combination anymore,
fold them and IntelSyntax into a single, enum-like attribute. Note that
this shrinks i386_opcode_modifier back to 2 32-bit words (albeit that's
not for long, seeing in-flight additions for APX).
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As noted in the context of d53e6b98a259 ("x86/Intel: correct disassembly
of fsub*/fdiv*") there's no such thing as Intel syntax without Intel
mnemonics. Enforce this on the assembler side, and disentangle command
line option handling on the disassembler side accordingly.
As a result in the opcode table specifying ATTMnemonic|ATTSyntax becomes
redundant with just ATTMnemonic. Drop the now meaningless ATTSyntax and
remove the then no longer accessible templates.
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opcodes/ChangeLog:
* i386-opc.tbl: Remove redundant Byte, Word, Dword and Qword.
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... as MSR index specifier: It is unreasonable to demand that people
write less readable / understandable code, just because the present
documentation mentions only Reg64. Whether to also adjust the
disassembler is a separate question, perhaps indeed more tightly tied
to what the spec says.
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Deal with what 58bceb182740 ("x86: prefer VEX encodings over EVEX ones
when possible") left out, for being slightly less straightforward.
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{disp16} is invalid to use in 64-bit mode, while {disp32} is invalid to
use on pre-386 CPUs. The latter, also affecting other (real) prefixes,
further requires that like for insns we fully check the CPU flags; till
now only Cpu64/CpuNo64 were taken into consideration.
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As indicated during review already, doing the swapping early is overall
cheaper than doing it only after operand matching.
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Right now the opcode table has entries with ISA restrictions of the form
FEAT1|FEAT2, the meaning of which depends on context and requires
special treatment in tc-i386.c: Sometimes this means "both features
requires", whereas originally it was intended to solely mean "all of
these features required". Split the field, with the original one
regaining its original meaning. The new field now truly means "any of
these". The combination of both fields is still and &&-type check, i.e.
(all of these) && (any of these). In the opcode table more involved
combinations of features then also need expressing this way: "all"
entities first, follow by "any" entities enclosed in parentheses, e.g.
x64&(AVX|AVX512F). If the "all" part is empty, parentheses may not be
added around the "any" part (unless parsing logic was further relaxed).
Note that this way AVX512VL no longer needs as much special treatment,
and hence templates previously using AVX512F|AVX512VL are switched to
just AVX512VL.
Note further that this requires FMA handling as resulting from
da0784f961d8 ("x86: fold FMA VEX and EVEX templates") to be slightly
re-done: FMA now becomes more similar to AVX and AVX2.
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First of all we want to also accumulate its reverse dependencies, such
that we can use them in cpu_flags_match(). This is in particular in
preparation of APX additions, such that e.g. BMI VEX-encoding templates
can become combined VEX/EVEX ones.
Once we have the reverse dependencies, we can further leverage them to
omit explicit "&x64" from any insn templates dealing with 64-bit-mode-
only ISA extensions. Besides helping readability for several insn
templates we already have, this will also help with what is going to be
added for APX (as all of the new templates would otherwise need to have
"&x64").
Note that rather than leaving a meaningless CPU_64_FLAGS (which is
unused anyway), its emitting is now also suppressed.
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This patches aims to support Intel USER_MSR. In addition to the usual
support, this patch includes encoding and decoding support for MAP7 and
immediate numbers as the last operand (ATT style).
gas/ChangeLog:
* NEWS: Support Intel USER_MSR.
* config/tc-i386.c (smallest_imm_type): Reject imm32 in 64bit
mode.
(build_vex_prefix): Add VEXMAP7.
(md_assemble): Handling the imm32 of USER_MSR.
(match_template): Handling the unusual immediate.
* doc/c-i386.texi: Document .user_msr.
* testsuite/gas/i386/i386.exp: Run USER_MSR tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/user_msr-inval.l: New test.
* testsuite/gas/i386/user_msr-inval.s: Ditto.
* testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto.
* testsuite/gas/i386/x86-64-user_msr-inval.l: Ditto.
* testsuite/gas/i386/x86-64-user_msr-inval.s: Ditto.
* testsuite/gas/i386/x86-64-user_msr.d: Ditto.
* testsuite/gas/i386/x86-64-user_msr.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (struct instr_info): Add a new attribute
has_skipped_modrm.
(Gq): New.
(Rq): Ditto.
(q_mm_mode): Ditto.
(Nq): Change mode from q_mode to q_mm_mode.
(VEX_LEN_TABLE):
(get_valid_dis386): Add VEX_MAP7 in VEX prefix.
and handle the map7_f8 for save space.
(OP_Skip_MODRM): Set has_skipped_modrm.
(OP_E): Skip codep++ when has skipped modrm byte.
(OP_R): Support q_mode and q_mm_mode.
(REG_VEX_MAP7_F8_L_0_W_0): New.
(PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto.
(X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto.
(VEX_LEN_MAP7_F8): Ditto.
(VEX_W_MAP7_F8_L_0): Ditto.
(MOD_0F38F8): Ditto.
(PREFIX_0F38F8_M_0): Ditto.
(PREFIX_0F38F8_M_1_X86_64): Ditto.
(X86_64_0F38F8_M_1): Ditto.
(PREFIX_0F38F8): Remove.
(prefix_table): Add PREFIX_0F38F8_M_1_X86_64.
Remove PREFIX_0F38F8.
(reg_table): Add REG_VEX_MAP7_F8_L_0_W_0,
PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64.
(x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1,
X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1.
(vex_table): Add VEX_MAP7.
(vex_len_table): Add VEX_LEN_MAP7_F8,
VEX_W_MAP7_F8_L_0.
(mod_table): New entry for USER_MSR and
add MOD_0F38F8.
* i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and
CPU_ANY_USER_MSR_FLAGS. Add add VEXMAP7.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (SPACE_VEXMAP7): New.
(CPU_USER_MSR_FLAGS): Ditoo.
(CPU_ANY_USER_MSR_FLAGS): Ditto.
(i386_cpu_flags): Add cpuuser_msr.
* i386-opc.tbl: Add USER_MSR instructions.
* i386-tbl.h: Regenerated.
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Following the folding of some generic AVX/AVX2 templates with their
AVX512F counterpart ones, do this for FMA ones as well, requiring one
further adjustment to cpu_flags_match().
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Following the folding of some generic AVX/AVX2 templates with their
AVX512F counterpart ones, do this for VAES and VPCLMULQDQ ones as well.
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In anticipation of APX introduce logic to reduce the number of templates
we have now, allowing to limit some the number of ones we then need to
gain.
The fundamental requirements are that
- attributes be compatible, which specifically means VexW needs to be
the same in the templates (which often isn't the case, for VEX
encodings having far more WIG tha, EVEX ones),
- the EVEX form being AVX512F (with or without AVX512VL), not any of its
extensions (the same will then be required for APX - it'll need to be
APX_F).
Note that in check_register() there's now a redundant zmm check. Since
this logic will need revisiting for APX anyway, I'd like to keep it that
way for now. (Similarly a couple of if()-s which could be folded are
kept separate, to reduce code churn when adding APX support.)
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Looking at the VEX and EVEX forms of vcvtneps2bf16 I noticed that
operand purpose isn't properly reflected in Vxy's definition. Rename
"dst" to "src", thus bringing things in line with Exy.
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Recognize "/<number>" suffixes on both -march=+avx10.1 and the
corresponding .arch directive, setting an upper bound on the vector size
that insns may use. Such a restriction can be reset by setting a new base
architecture, by using a suffix-less form, by disabling AVX10, or by
enabling any other VEX/EVEX-based vector extension.
While for most insns we can suppress their use with too wide operands
via registers becoming unavailable (or in Intel syntax memory operand
size specifiers not being recognized), mask register insns have to have
their minimum required vector size specified in a new attribute. (Of
course this new attribute could also be used on other insns.)
Note that .insn continues to be permitted to emit EVEX{512,256} (and
VEX256 ones) encodings regardless of vector size restrictions in place.
Of course these can't be expressed using zmm (or ymm) operands then,
but need using the EVEX.512.* forms (broadcast forms may be usable right
now, but this may go away so shouldn't be relied upon). This is why no
assertions should be added to build_{e,}vex_prefix().
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These probably should have been put in place already anyway, but they're
very much wanted in order to then put AVX10.1 support on top. Note that
to avoid reverse dependencies towards SSE (just like we already do for
AVX and XOP), add_isa_dependencies() needs some further tweaking.
While there also address a related anomaly: Disabling AES but neither
AVX nor VAES (similarly for {,V}PCLMULQDQ) would better keep the 128-bit
VEX-encoded forms available. Note that for this the VAES insns are moved
past the AVX+AES ones, to avoid the property-11 test suddenly failing.
The test really is wrong, but let's not also make things inconsistent:
Without the movement, YMM use would be correctly recorded for the
128-bit forms simply because the first template already matches, as long
as VAES wasn't disabled. Yet it still wouldn't be if only AVX+AES were
enabled. Nor would behavior here then be the same as for VPCLMUL* insns.
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The name we use internally isn't in line with the SDM, and also isn't in
line with CpuVPCLMULQDQ. Add the missing suffix, but of course leave
alone user facing names.
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Commit 916fae91358d ("Add Size64 to movq/vmovq with Reg64 operand" was
right in adding the attribute to MOVQ, but there was no need to add it
to VMOVQ. (See also the AVX512F form, which doesn't have the attribute
either.)
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This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d.
See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
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gas/ChangeLog:
* NEWS: Support Intel PBNDKB.
* config/tc-i386.c: Add pbndkb.
* doc/c-i386.texi: Document .pbndkb.
* testsuite/gas/i386/i386.exp: Add PBNDKB tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/pbndkb-inval.l: New test.
* testsuite/gas/i386/pbndkb-inval.s: Ditto.
* testsuite/gas/i386/x86-64-pbndkb-intel.d: Ditto.
* testsuite/gas/i386/x86-64-pbndkb.d: Ditto.
* testsuite/gas/i386/x86-64-pbndkb.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_7): New.
(X86_64_0F01_REG_0_MOD_3_RM_7_P_0): Ditto.
(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_7.
(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_7_P_0.
(rm_table): New entry for pbndkb.
* i386-gen.c (cpu_flag): Add PBNDKB.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (CpuPBNDKB): New.
(i386_cpu_flags): Add cpupbndkb.
* i386-opc.tbl: Add PBNDKB instructions.
* i386-tbl.h: Regenerated.
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gas/ChangeLog:
* NEWS: Support Intel SM4.
* config/tc-i386.c: Add sm4.
* doc/c-i386.texi: Document .sm4.
* testsuite/gas/i386/i386.exp: Run SM4 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/sm4-intel.d: Add SM4 tests.
* testsuite/gas/i386/sm4.d: Ditto.
* testsuite/gas/i386/sm4.s: Ditto.
* testsuite/gas/i386/x86-64-sm4-intel.d: Ditto.
* testsuite/gas/i386/x86-64-sm4.d: Ditto.
* testsuite/gas/i386/x86-64-sm4.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (prefix_table): Add SM4 instructions.
* i386-gen.c (isa_dependencies): Add SM4.
(cpu_flags): Ditto.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (CpuSM4): New.
(i386_cpu_flags): Add cpusm4.
* i386-opc.tbl: Add SM4 instructions.
* i386-tbl.h: Regenerated.
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gas/ChangeLog:
* NEWS: Support Intel SM3.
* config/tc-i386.c: Add sm3.
* doc/c-i386.texi: Document .sm3.
* testsuite/gas/i386/i386.exp: Run sm3 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/sm3-intel.d: New test.
* testsuite/gas/i386/sm3.d: Ditto.
* testsuite/gas/i386/sm3.s: Ditto.
* testsuite/gas/i386/x86-64-sm3-intel.d: Ditto.
* testsuite/gas/i386/x86-64-sm3.d: Ditto.
* testsuite/gas/i386/x86-64-sm3.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_VEX_0F38DA_W_0): New.
(VEX_LEN_0F38DA_W_0_P_0): Ditto.
(VEX_LEN_0F38DA_W_0_P_2): Ditto.
(VEX_LEN_0F3ADE_W_0): Ditto.
(VEX_W_0F38DA): Ditto.
(VEX_W_0F3ADE): Ditto.
(prefix_table): Add PREFIX_VEX_0F38DA_W_0.
(vex_len_table): Add VEX_LEN_0F38DA_W_0_P_0,
VEX_LEN_0F38DA_W_0_P_2, VEX_LEN_0F3ADE_W_0.
(vex_w_table): Add VEX_W_0F38DA, VEX_W_0F3ADE.
* i386-gen.c (isa_dependencies): Add SM3.
(cpu_flags): Ditto.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (CpuSM3): New.
(i386_cpu_flags): Add cpusm3.
* i386-opc.tbl: Add SM3 instructions.
* i386-tbl.h: Regenerated.
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gas/ChangeLog:
* NEWS: Support Intel SHA512.
* config/tc-i386.c: Add sha512.
* doc/c-i386.texi: Document .sha512.
* testsuite/gas/i386/disassem.d: Add SHA512 tests.
* testsuite/gas/i386/disassem.s: Ditto.
* testsuite/gas/i386/i386.exp: Run SHA512 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/sha512-intel.d: New test.
* testsuite/gas/i386/sha512-inval.l: Ditto.
* testsuite/gas/i386/sha512-inval.s: Ditto.
* testsuite/gas/i386/sha512.d: Ditto.
* testsuite/gas/i386/sha512.s: Ditto.
* testsuite/gas/i386/x86-64-sha512-intel.d: Ditto.
* testsuite/gas/i386/x86-64-sha512-inval.l: Ditto.
* testsuite/gas/i386/x86-64-sha512-inval.s: Ditto.
* testsuite/gas/i386/x86-64-sha512.d: Ditto.
* testsuite/gas/i386/x86-64-sha512.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (Rxmmq): New.
(Rymm): Ditto.
(PREFIX_VEX_0F38CB): Ditto.
(PREFIX_VEX_0F38CC): Ditto.
(PREFIX_VEX_0F38CD): Ditto.
(VEX_LEN_0F38CB_P_3_W_0): Ditto.
(VEX_LEN_0F38CC_P_3_W_0): Ditto.
(VEX_LEN_0F38CD_P_3_W_0): Ditto.
(VEX_W_0F38CB_P_3): Ditto.
(VEX_W_0F38CC_P_3): Ditto.
(VEX_W_0F38CD_P_3): Ditto.
(prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC,
PREFIX_VEX_0F38CD.
(vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0,
VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0.
(vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3.
* i386-gen.c (isa_dependencies): Add SHA512.
(cpu_flags): Ditto.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (CpuSHA512): New.
(i386_cpu_flags): Add cpusha512.
* i386-opc.tbl: Add SHA512 instructions.
* i386-tbl.h: Regenerated.
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gas/ChangeLog:
* NEWS: Support Intel AVX-VNNI-INT16.
* config/tc-i386.c: Add avx_vnni_int16.
* doc/c-i386.texi: Document avx_vnni_int16.
* testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/avx-vnni-int16-intel.d: New test.
* testsuite/gas/i386/avx-vnni-int16.d: New test.
* testsuite/gas/i386/avx-vnni-int16.s: New test.
* testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test.
* testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test.
* testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_VEX_0F38D2_W_0): New.
(PREFIX_VEX_0F38D3_W_0): Ditto.
(VEX_W_0F38D2_P_0): Ditto.
(VEX_W_0F38D2_P_1): Ditto.
(VEX_W_0F38D2_P_2): Ditto.
(VEX_W_0F38D3_P_0): Ditto.
(VEX_W_0F38D3_P_1): Ditto.
(VEX_W_0F38D3_P_2): Ditto.
(prefix_table): Add PREFIX_VEX_0F38D2_W_0 and
PREFIX_VEX_0F38D3_W_0.
(vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3.
(vex_w_table): Ditto.
* i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16.
(cpu_flag): Ditto.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h: (CpuAVX_VNNI_INT16): New.
* i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions.
* i386-tbl.h: Regenerated.
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The alternative is 1 byte shorter when the source is %xmm0-7, as a
2-byte VEX prefix can then be used.
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These are better expressed by the zeroing idiom {,V}PXOR. In some cases
this also results in a shorter encoding.
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The {,V}PCMPEQD alternative is 1 byte shorter in many cases.
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The logic can actually be expressed with less code that way, utilizing
that there are common patterns of when which form of masking is
permitted. This then also eliminates the large set of open-codings of
BOTH_MASKING in the opcode table.
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gas/ChangeLog:
* NEWS: Support Intel FRED LKGS.
* config/tc-i386.c: Add fred lkgs
* doc/c-i386.texi: Document .fred, .lkgs.
* testsuite/gas/i386/i386.exp: Add FRED LKGS tests
* testsuite/gas/i386/x86-64-fred-intel.d: Ditto.
* testsuite/gas/i386/x86-64-fred.d: Ditto.
* testsuite/gas/i386/x86-64-fred.s: Ditto.
* testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto.
* testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto.
* testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto.
* testsuite/gas/i386/x86-64-lkgs.d: Ditto.
* testsuite/gas/i386/x86-64-lkgs.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c: New entry for fred, lkgs.
* i386-gen.c: Add CPU_FRED CPU_LKGS.
* i386-init.h : Regenerated.
* i386-mnem.h : Regenerated.
* i386-opc.h: Add fred, lkgs.
* i386-opc.tbl: Add FRED, LKGS instructions.
* i386-tbl.h: Regenerated.
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This reverts commit e5a497fe38e0ab19e16bdd9e4b4ed5e4d0056478.
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gas/ChangeLog:
* NEWS: Support Intel FRED LKGS.
* config/tc-i386.c: Add fred lkgs
* doc/c-i386.texi: Document .fred, .lkgs.
* testsuite/gas/i386/i386.exp: Add FRED LKGS tests
* testsuite/gas/i386/x86-64-fred-intel.d: Ditto.
* testsuite/gas/i386/x86-64-fred.d: Ditto.
* testsuite/gas/i386/x86-64-fred.s: Ditto.
* testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto.
* testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto.
* testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto.
* testsuite/gas/i386/x86-64-lkgs.d: Ditto.
* testsuite/gas/i386/x86-64-lkgs.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c: New entry for fred, lkgs.
* i386-gen.c: Add CPU_FRED CPU_LKGS.
* i386-init.h : Regenerated.
* i386-mnem.h : Regenerated.
* i386-opc.h: Add fred, lkgs.
* i386-opc.tbl: Add FRED, LKGS instructions.
* i386-tbl.h: Regenerated.
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gas/ChangeLog:
* NEWS: Support Intel AMX-COMPLEX.
* config/tc-i386.c: Add amx_complex.
* doc/c-i386.texi: Document .amx_complex.
* testsuite/gas/i386/i386.exp: Run AMX-COMPLEX tests.
* testsuite/gas/i386/amx-complex-inval.l: New test.
* testsuite/gas/i386/amx-complex-inval.s: Ditto.
* testsuite/gas/i386/x86-64-amx-complex-bad.d: Ditto.
* testsuite/gas/i386/x86-64-amx-complex-bad.s: Ditto.
* testsuite/gas/i386/x86-64-amx-complex-intel.d: Ditto.
* testsuite/gas/i386/x86-64-amx-complex.d: Ditto.
* testsuite/gas/i386/x86-64-amx-complex.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (MOD_VEX_0F386C_X86_64_W_0): New.
(PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0): Ditto.
(X86_64_VEX_0F386C): Ditto.
(VEX_LEN_0F386C_X86_64_W_0_M_1): Ditto.
(VEX_W_0F386C_X86_64): Ditto.
(mod_table): Add MOD_VEX_0F386C_X86_64_W_0.
(prefix_table): Add PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0.
(x86_64_table): Add X86_64_VEX_0F386C.
(vex_len_table): Add VEX_LEN_0F386C_X86_64_W_0_M_1.
(vex_w_table): Add VEX_W_0F386C_X86_64.
* i386-gen.c (cpu_flag_init): Add CPU_AMX_COMPLEX_FLAGS and
CPU_ANY_AMX_COMPLEX_FLAGS.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (CpuAMX_COMPLEX): New.
(i386_cpu_flags): Add cpuamx_complex.
* i386-opc.tbl: Add AMX-COMPLEX instructions.
* i386-tbl.h: Regenerated.
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With VexVVVV only being boolean, the SSE shift-by-immediate instructions
don't need special casing anymore for SSE2AVX handling. Simplify the two
respective templates. (No change to generated tables.)
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With the SDM long having dropped the NDS/NDD/DDS concept of identifying
encoding variants, we can finally do away with this concept as well. Of
the few consumers of the attribute, only an assertion was still checking
for a particular value, which we don't really need to retain.
When touching lines anyway, modernize other aspects as well. This often
improves similarity to adjacent lines.
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The function has accumulated a number of special cases for no real
reason. Some were necessary because insn attributes (SwapSources in
particular) weren't suitably utilized instead. Note that the addition of
SwapSources actually increases consistency among the templates: Like
others which already have the attribute, these are all insns where the
VEX.VVVV-encoded register comes first (or last when looking at the SDM).
Note that the vexvvvv attribute now has merely boolean meaning anymore,
in line with the SDM long having dropped the NDS/NDD/DDS concept of
identifying encoding variants. The fallout will be taken care of
subsequently, though, to not further clutter the change here.
As to the TILEZERO special case: If more instructions like this
appeared, a new attribute would likely be the way to go. But as long as
it's only a single insn, going from the mnemonic is cheaper.
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