| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-03-28 | x86: templatize ADX insns | Jan Beulich | 1 | -6/+5 |
| 2024-03-28 | x86: templatize shift-double insns | Jan Beulich | 1 | -13/+9 |
| 2024-03-28 | x86: templatize shift/rotate insns | Jan Beulich | 1 | -71/+22 |
| 2024-03-28 | x86: templatize binary ALU insns | Jan Beulich | 1 | -59/+23 |
| 2024-03-28 | x86: templatize unary ALU insns | Jan Beulich | 1 | -10/+16 |
| 2024-03-28 | x86: templatize INC/DEC | Jan Beulich | 1 | -8/+8 |
| 2024-03-01 | x86/APX: optimize certain XOR and SUB forms | Jan Beulich | 1 | -2/+2 |
| 2024-02-23 | x86/APX: INV{EPT,PCID,VPID} are WIG | Jan Beulich | 1 | -3/+3 |
| 2024-02-16 | x86/APX: drop stray IgnoreSize | Jan Beulich | 1 | -11/+11 |
| 2024-02-16 | x86: don't use VexWIG in SSE2AVX templates | Jan Beulich | 1 | -4/+4 |
| 2024-02-16 | x86: drop redundant Xmmword | Jan Beulich | 1 | -8/+8 |
| 2024-02-09 | x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressed | Jan Beulich | 1 | -4/+16 |
| 2024-02-09 | x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL} | Jan Beulich | 1 | -2/+2 |
| 2024-01-26 | x86/APX: optimize MOVBE | Jan Beulich | 1 | -2/+4 |
| 2024-01-19 | x86/APX: VROUND{P,S}{S,D} can generally be encoded | Jan Beulich | 1 | -0/+4 |
| 2024-01-19 | x86: drop redundant EVex128 from PUSH2/POP2 | Jan Beulich | 1 | -4/+4 |
| 2024-01-19 | x86: support APX forms of U{RD,WR}MSR | Jan Beulich | 1 | -2/+4 |
| 2024-01-15 | opcodes: x86: new marker for insns that implicitly update stack pointer | Indu Bhagat | 1 | -52/+53 |
| 2024-01-15 | opcodes: gas: x86: define and use Rex2 as attribute not constraint | Indu Bhagat | 1 | -1/+0 |
| 2024-01-09 | x86: add missing APX logic to cpu_flags_match() | Jan Beulich | 1 | -1/+7 |
| 2024-01-04 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2023-12-28 | Support APX pushp/popp | Cui, Lili | 1 | -0/+3 |
| 2023-12-28 | Support APX Push2/Pop2 | Mo, Zewei | 1 | -0/+9 |
| 2023-12-28 | Support APX NDD | konglin1 | 1 | -0/+75 |
| 2023-12-28 | Support APX GPR32 with extend evex prefix | Cui, Lili | 1 | -25/+65 |
| 2023-12-28 | Support APX GPR32 with rex2 prefix | Cui, Lili | 1 | -13/+14 |
| 2023-12-19 | x86: Remove the restriction for size of the mask register in AVX10 | Haochen Jiang | 1 | -22/+19 |
| 2023-12-15 | revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR" | Jan Beulich | 1 | -2/+2 |
| 2023-12-15 | x86: fold assembly dialect attributes | Jan Beulich | 1 | -0/+4 |
| 2023-12-15 | x86: Intel syntax implies Intel mnemonics | Jan Beulich | 1 | -20/+16 |
| 2023-12-14 | Remove redundant Byte, Word, Dword and Qword from insn templates. | Cui, Lili | 1 | -123/+123 |
| 2023-12-01 | x86: allow 32-bit reg to be used with U{RD,WR}MSR | Jan Beulich | 1 | -2/+2 |
| 2023-11-24 | x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possible | Jan Beulich | 1 | -0/+6 |
| 2023-11-17 | x86: CPU-qualify {disp16} / {disp32} | Jan Beulich | 1 | -1/+1 |
| 2023-11-09 | x86: rework UWRMSR operand swapping | Jan Beulich | 1 | -1/+3 |
| 2023-11-09 | x86: split insn templates' CPU field | Jan Beulich | 1 | -289/+289 |
| 2023-11-09 | x86: Cpu64 handling improvements | Jan Beulich | 1 | -37/+39 |
| 2023-10-31 | Support Intel USER_MSR | Hu, Lin1 | 1 | -0/+11 |
| 2023-09-27 | x86: fold FMA VEX and EVEX templates | Jan Beulich | 1 | -26/+15 |
| 2023-09-27 | x86: fold VAES/VPCLMULQDQ VEX and EVEX templates | Jan Beulich | 1 | -28/+9 |
| 2023-09-27 | x86: fold certain VEX and EVEX templates | Jan Beulich | 1 | -73/+41 |
| 2023-09-14 | x86: Vxy naming correction | Jan Beulich | 1 | -5/+5 |
| 2023-09-14 | x86: support AVX10.1 vector size restrictions | Jan Beulich | 1 | -19/+22 |
| 2023-09-14 | x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQ | Jan Beulich | 1 | -12/+14 |
| 2023-09-01 | x86: rename CpuPCLMUL | Jan Beulich | 1 | -12/+12 |
| 2023-09-01 | x86: drop Size64 from VMOVQ | Jan Beulich | 1 | -1/+1 |
| 2023-08-02 | Revert "2.41 Release sources" | Sam James | 1 | -9/+48 |
| 2023-08-02 | 2.41 Release sourcesbinutils-2_41-release | Nick Clifton | 1 | -48/+9 |
| 2023-07-27 | Support Intel PBNDKB | Hu, Lin1 | 1 | -0/+6 |
| 2023-07-27 | Support Intel SM4 | Haochen Jiang | 1 | -0/+7 |
