* Add header to debug_defines.h

Also cleaned up the Makefile so `make debug_defines.h` actually works
right, and mentioned this make target in README.md.

* Include hash in debug_defines header.

* Remove end of line whitespace.

1. Add more whitespace around << and - to satisfy OpenOCD style guides.
2. Don't define register addresses that we don't have (e.g. in abstract
commands).
3. Make comments look right, with a leading space before the star.

* Add dmcontrol.relaxedpriv

* Restore accidental whitespace changes

* Build draft PDF

* Point to relaxedpriv in section 4.1

* Revert PDF since it didn't build nicely.

* Add abstractcs.relaxedpriv

Address #531.

* Explicitly allow uni-directional external triggers.

Also document a convention for trigger number by direction.

* Incorporate Ernie's feedback.

* Revert "fix" to external trigger number convention.

* Appendix B: Added suggested signals for the DMI

* Added reference to the DMI implementation of the rocket-chip

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Converted bare hyper link into a latex href structure

* Added width to suggested DMI signals

* Added a reference from DMI to DMI signal suggestion

* Example read/write with the suggested DMI signals

* Moved suggested DMI signals into hardware implementations chapter

* Fixed spelling errors and improved wording for suggested DMI signals

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* All tdata functionality is optional...

... so don't mention on a few bits that they are optional, because
that's confusing (see #441).

* Update hwbp_registers.xml

* Adding version encoding for 0.14 spec.

* Remove sneaky tab characters.

If a privilege mode is not supported by the core, or if a privilege
change is not allowed, the dcsr.prv register is set to a supported
value. This makes this register WARL, not R/W, as indicated in the
table.

This is important, because there is literally no space in the register
for the field when XLEN is 32.

Problem reported by Allen Baum.

Clarify what happens when those occur during single step. Hopefully
clarifies #510.

* Recommend clearing action when dmode is cleared.

Otherwise you might end up in a situation where regular software can
control when to enter debug mode.

* Recommend hardware ignore illegal triggers.

* Change to use WARL.

Hopefully I found some language that makes sense when csrci is used to
clear just dmode, as well as writing a brand new value, and only changes
action if it's actually necessary.

* Fix conflict in sbdata0/sbautoincrement definition.

Autoincrement only happens if an access actually takes place.

On the list, see subject:"sbaccess ambiguity".

* Only increment on successful reads.

This mirrors the write case, and allows debuggers to batch a large
number of reads and only check the error bits once, at the end.

* Add resume groups.

Mostly inspired by e-mail discussion with Subject:"resume groups in
addition to halt groups".

* Clarifications requested by review.

* Make haltsum0 optional if there is only one hart.

This is not forwards compatible. Debuggers that rely on haltsum0 would
break with this change. But it makes the debug interface on tiny 1-hart
systems smaller, especially because it allows the number of address bits
in the DMI to be 1 less. (Haltsum0 at 0x40 due to other efforts to
maintain backwards compatibility.)

Fixes #389.

* Make language more precise.

* Halt state may not be preserved across reset.

It's not necessary to have this requirement, since there are other
mechanisms to ensure harts halt out of reset if that's what the debugger
wants.

Fixes #357.

* Slight rephrasing.

This mirrors a change made in the privileged spec:
https://github.com/riscv/riscv-isa-manual/commit/569d07195a8495460f04592d8455153f730a0f54

* Time may pass before dmactive becomes high.

This addresses a concern of how the debugger can know when hardware is
ready to be debugged, discussed on the mailing list. subject:"Email
discussion: how can a debugger know when a target is ready for it?"

* Rephrase.

Make the emitted registers chisel3

Previously they were emitted in Chisel._ (compatability mode). As part of upgrading to chisel3, export them as chisel3 (note this doesn't actually change anything).

* Document forward progress guarantees in Debug Mode.

Alternative to #481.

* Small progbuf execution clarifications.

* Rewrite/clarify DM Reset Control

Hopefully fixes #480.

* Clarifications from review.

* Another clarification.

* There's no way to tell when reset has started.

I don't think that's very important. If it is, we'll probably have to
add a status bit that indicates a hart is held in reset.

* Fix wrong table reference

The label is named dtmTable:jtagregisters, not table:jtag_registers.

* Remove reference to non-existent table

The referenced table was removed in
b0420b3a.

Alternative to #488.

Addresses #489.

The spec says about the dmcontrol.hartreset field:
 "If this feature is not implemented, the bit always
stays 0, so after writing 1 the debugger can read
the register back to see if the feature is supported."

That makes it a WARL field not a R/W field. Changing the annotation to
make it more obvious to the reader.