This helps some hardware implementations be simpler.  Addresses #550.

We used to not do this because those fields would often have the same
name as some other field, and there was a name collision. Now however we
have long, fully qualified names. This change is needed for #588 which
references \FcsrTextraSixtyfourSselect.

Fixes #462.

* Recommend mprven=1

* Review feedback: links

* Add pending state/bit to icount.

See mailing list. Subject:"On icount triggers"

* Fix typo.

* Explicitly mention s/u bits are 0 if not supported.

* Allow count decrement when triggers are disabled.

This reverts #557 because the issue raised in #555 is already solved by
the new pending bit.

Fixes #448

* textra32/64 also affects the new mcontrol6 triggers

* Provide clarity on textra64.  Don't refer to non-existent textra.

* List all DM registers in Table 3.8.

But don't give them each a description if it's redundant.

The main change here is that registers.py now generates an "index" table
that can be split across pages.

This change supersedes #560.

* Review feedback.

* Add support for the A extension

* Review feedback

* Handle instruction mnemonics consistently.  Reduce empty space.

* Remove all uses of the ambiguous term "may not"

* Review feedback

* It's legal to implement the CSRs even if there are no triggers

Co-authored-by: Tim Newsome <tim@sifive.com>

heterogeneous systems with some control processor harts that only support M
mode and some full-featured harts that support more.

* Added exttrigger capability as type 7

* Review feedback.
- don't limit implementation to a pulse
- allow multiple inputs to be selected and fire if any of them signals

* Revert PDF

* Change names to DM external trigger and TM external trigger

* Define TM

* Debuggers should know when harts are unavailable.

Make unavail sticky, needing to be acknowledged with new ackunavail bit.

This is a backwards incompatible change. I think it's OK because
implementations that support unavailable harts are rare (I don't know of
any), and the change only means that debuggers must be updated. If
hardware doesn't implement this then everything will still work,
although users might not be notified when harts become unavailable.

Fixes #461.

* Add stickyunavail bit.

Every other way to ensure hardware backwards compatibility was getting
too convoluted.

* Clean up a little.

Keep definition of the bits in the register definition, and definition
of states in the DM section.

* Don't decrement icount.count when exception is blocked by tcontrol.mte

Since it wouldn't be able to take the breakpoint trap anyway.

Fixes #555.

* Expand count decrement exception to include other trap-suppression mechanisms

Thank you!

Co-authored-by: Benjamin Staveley <ben@Benjamins-MacBook-Pro.local>

* clarify that PMP must allow access for debug to be possible

* rephrase

* Update implementations.tex

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* Add most hypervisor support

* Don't check in PDF changes.

* Add vu/vs bits to various triggers
Clarify that registers are "accessible" in specified modes, not just "writable"
Prohibit hcontext alias when the H extension isn't supported since this is in
  the CSR address space that's normally just for hypervisor.

* Clarify that the backwards-compatible mscontext is optional.

* Update core_debug.tex

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Fix curly braces

* Fix textra64.mhselect
Remove comments about future H mode support

* scontext is accessible from VS mode.
Clarify in various places that enables are for "S/HS" instead of just "S" mode.

* Use decimal values in field descriptions to match the rest of the spec.
VMID is in hgatp, not satp.

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

Changed the dret section in the normative architecture section to only
include architectural requirements and refer to the appendix for implementation
details.
Added UNSPECIFIED to the preamble to conform to the overall architecture.

* Add mcontrol6.
Mcontrol6 is like mcontrol but without a maskmax field and with a sizehi field on RV32.
A recipe is provided for determining the max mask when mcontrol6.match=1 (NAPOT).

* Apply suggestions from code review

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Added caveat about data value matches larger than XLEN.

* Review feedback:
- don't duplicate timing table. mcontrol6 is authoritative.
- use register/field macros
- unify size field in mcontrol6

* Revert PDF

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Add scontext2 alias for scontext

* Fix links to scontext

* Changed scontext to mscontext and scontext2 to scontext

* Change long names too

* Added scxe, hcxe per review comments on Priv Spec

* Review comment: hyperlinks

Adding a brief clarification of "aamvirtual" bit behavior, per
the following discussion:
https://lists.riscv.org/g/tech-debug/topic/72759746



Co-authored-by: Jan Matyas <jmatyas@codasip.com>

* Add header to debug_defines.h

Also cleaned up the Makefile so `make debug_defines.h` actually works
right, and mentioned this make target in README.md.

* Include hash in debug_defines header.

* Remove end of line whitespace.

1. Add more whitespace around << and - to satisfy OpenOCD style guides.
2. Don't define register addresses that we don't have (e.g. in abstract
commands).
3. Make comments look right, with a leading space before the star.

* Add dmcontrol.relaxedpriv

* Restore accidental whitespace changes

* Build draft PDF

* Point to relaxedpriv in section 4.1

* Revert PDF since it didn't build nicely.

* Add abstractcs.relaxedpriv

Address #531.

* Explicitly allow uni-directional external triggers.

Also document a convention for trigger number by direction.

* Incorporate Ernie's feedback.

* Revert "fix" to external trigger number convention.