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riscv
riscv-debug-spec
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debug_defines_make
0b46055c
·
Fix debug_defines make process.
·
Nov 01, 2023
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dmi_address
470ca90a
·
Clarify that each DMI address points at a 32-bit register.
·
Aug 24, 2023
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exception
4970b557
·
AR: Can't require exception for CSR access.
·
Aug 22, 2023
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nonexistent
83483b1f
·
AR: Don't use "non-existent" in reference to register.
·
Aug 21, 2023
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message_reg
b6cbb1cb
·
AR: Clarify message register uses.
·
Aug 15, 2023
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execute_cache
e3671acb
·
Recommend debug ROM is not cached.
·
Aug 15, 2023
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native
5a5c86fc
·
AR: Define "native debug" in Background section.
·
Aug 15, 2023
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makefile
c287f4ff
·
Make `make clean` more exhaustive.
·
Aug 15, 2023
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master_slave
f44beaf1
·
AR: Use manager/subordinate for master/slave.
·
Jul 31, 2023
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implementations
314b09fc
·
Fix type in execution appendix: execute -> postexec
·
Jul 26, 2023
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halt_resume_groups
6a56dea7
·
External trigger signals inputs don't cause trigger output.
·
Jun 12, 2023
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a_extension
2fdf271e
·
Document trigger behavior with vector/push/pop accesses.
·
Mar 08, 2023
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timing_compatibility
b1260894
·
Debuggers should accept mcontrol6.20 reading back 1.
·
Feb 10, 2023
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dmi_clarify
67fbfe78
·
dmi.{data,address} are unspecified after write/nop
·
Oct 14, 2022
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license
57816130
·
Be more verbose about the license.
·
Jun 09, 2021
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maskmax
59c2d52e
·
Improve formatting.
·
Dec 18, 2020
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for_riscv
95a7f792
·
Rename to Debug Specification for RISC-V.
·
Jul 14, 2020
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resumegroup
b5b33391
·
Add resume groups.
·
Dec 03, 2019
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mwachs5-patch-1
9d55a575
·
Make the emitted registers chisel3
·
Nov 21, 2019
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command_discovery
2e1fef23
·
Allow trigger section to be parsed without knowing DXLEN.
·
Nov 06, 2019
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