- Apr 28, 2018
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Megan Wachs authored
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- Apr 25, 2018
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Tim Newsome authored
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- Apr 17, 2018
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Tim Newsome authored
Compute gdb command timeout based on ops estimate
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- Apr 10, 2018
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Tim Newsome authored
The caller of gdb.command() should estimate how much work gdb needs to do, and testlib then scales this up proportional to the general gdb timeout we configured. This hopefully allows us to configure a tighter timeout, so we don't have to have a multi-hour timeout just for something that takes long like `load` on a really slow simulator. Hopefully this addresses #122.
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Andrei Tatarnikov authored
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- Apr 03, 2018
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Tim Newsome authored
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- Mar 28, 2018
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Tim Newsome authored
Also halt instead of reset spike targets, which tests a more complicated code path.
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- Mar 24, 2018
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Tim Newsome authored
This makes it much easier to look at a log if you see a failure scrolling by on your terminal.
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- Mar 22, 2018
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- Mar 21, 2018
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Palmer Dabbelt authored
Update Makefile to allow for RISCV_PREFIX to be set by the configure
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- Mar 20, 2018
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rishi authored
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- Mar 02, 2018
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Tim Newsome authored
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Tim Newsome authored
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- Feb 27, 2018
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- Feb 10, 2018
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Tim Newsome authored
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- Feb 08, 2018
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Tim Newsome authored
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- Jan 09, 2018
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Tim Newsome authored
It's an optional register.
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- Jan 06, 2018
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Tim Newsome authored
Specifically, make sure that after resuming all cores, and halting core 0, that OpenOCD's poll() doesn't mess up the currently selected hart to the point where memory accesses intended for core 0 go to core 1.
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- Jan 03, 2018
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Andrew Waterman authored
OK'd by @palmer-dabbelt
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- Dec 28, 2017
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Tim Newsome authored
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
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- Dec 22, 2017
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Tim Newsome authored
I hope to use this in riscv-tools' regression.sh.
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Megan Wachs authored
tests: bump env to pick up new names for CSRs
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Megan Wachs authored
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- Dec 21, 2017
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Tim Newsome authored
gdb gets target XLEN from register width now, so this is taken care of automatically.
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Tim Newsome authored
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- Dec 13, 2017
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Tim Newsome authored
This makes it a little easier to just cut and paste from the log when reproducing a failure. (The port number still needs changing though.)
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- Dec 02, 2017
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Tim Newsome authored
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- Dec 01, 2017
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Tim Newsome authored
Clean up VcsSim init()
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Tim Newsome authored
Use a unique log file, so you can run multiple instances at once. Add time out to waiting for the simulator to be ready.
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- Nov 28, 2017
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Andrew Waterman authored
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- Nov 27, 2017
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Torbjørn authored
* Probably implemented the changes required to support fadd test for rv32ud * Created test files in rv32ud, implemented working(?) test for ldst * fclass, fcvt_w, fmin and recoding seem to be working now * Got fdiv (and sqrt) tests working * fmadd tests seem to work * fcmp works * [WIP] fcvt working, but lacks a 32-bit implementation of the final test * Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST * Added Makefrag for rv32ud tests and included in main isa Makefile * Don't run 64-bit tests if the defined XLEN is 32
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- Nov 23, 2017
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Christopher Celio authored
Closes #105.
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- Nov 21, 2017
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Andrew Waterman authored
Closes #103
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- Nov 20, 2017
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Tim Newsome authored
Fixes --print-failures sometimes not actually printing out details about failures.
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Tim Newsome authored
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- Nov 18, 2017
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Megan Wachs authored
debug: Fix the XLEN command line check
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Megan Wachs authored
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- Nov 17, 2017
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Megan Wachs authored
* Debug: Actually use the --32 and --64 command line arguments * debug: make XLEN mismatch message clearer
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Tim Newsome authored
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- Nov 16, 2017
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Tim Newsome authored
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